JPS63222549A - Reception buffer management equipment - Google Patents

Reception buffer management equipment

Info

Publication number
JPS63222549A
JPS63222549A JP62057323A JP5732387A JPS63222549A JP S63222549 A JPS63222549 A JP S63222549A JP 62057323 A JP62057323 A JP 62057323A JP 5732387 A JP5732387 A JP 5732387A JP S63222549 A JPS63222549 A JP S63222549A
Authority
JP
Japan
Prior art keywords
buffer
frame
reception
received
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62057323A
Other languages
Japanese (ja)
Inventor
Yoichi Oteru
大照 洋一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62057323A priority Critical patent/JPS63222549A/en
Publication of JPS63222549A publication Critical patent/JPS63222549A/en
Pending legal-status Critical Current

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  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To use a buffer while packing its memory from its end by discriminating the necessity of a received frame and resetting the address generating circuit designating the address of the reception buffer to be restored in case of an undesired frame. CONSTITUTION:A sequence circuit 4 selects the 1st buffer 5 and the 2nd buffer 7 alternately for each reception frame and gives a signal to corresponding address generating circuits 6, 8. The address generating circuit gives an address to each buffer and stores a reception frame. A discrimination controller 9 reads a control information area written in a specific location of the reception frame from the buffer received just now and gives a reset signal to the corresponding address generator 6 or 8 when an unrequired frame is discriminated. The address generation circuit restores the address counter for write to a value before the unrequired frame is received to prepare the reception of the succeeding frame. Thus, only the required frame is stored continuously in the area at all times.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は受信バッファ管理装置に関し、特に通信装置の
受信部における受信バッファ管理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reception buffer management device, and particularly to a reception buffer management device in a reception section of a communication device.

〔従来の技術〕[Conventional technology]

通信装置の受信部においては、伝送路から入来する受信
フレームはまず受信用のバッファに格納される。バッフ
ァは有限長でバッファに入れないフレームは捨てられる
ためバッファの効率よい使用方法が重要となる。通常の
受信装置ではバッファに入れる前にオンライン的に受信
する必要があるフレームかどうかの判別を行っており、
したがってバッファには受信する必要のあるフレームし
か格納されない。また一般に受信したフレームの処理は
受信された順に行われるので常に空き領域は連続した領
域になる。従来のバッファ管理の方法はこのような場合
を想定したものである。
In a receiving unit of a communication device, a received frame coming from a transmission path is first stored in a receiving buffer. Since the buffer has a finite length and frames that cannot be stored in the buffer are discarded, it is important to use the buffer efficiently. A normal receiving device determines whether the frame needs to be received online before buffering it.
Therefore, only the frames that need to be received are stored in the buffer. In addition, since the received frames are generally processed in the order in which they are received, the empty area is always a continuous area. Conventional buffer management methods assume such a case.

しかし複数の通信網を接続する接続装置などでは一般に
受信する必要があるフレームかどうかの判別を実時間で
行うことが難しいため、一旦すべてのフレームをバッフ
ァに格納した後に判別を行う場合が多い。このような場
合には必要ないことが判明したフレームが格納されてい
るバッファ領域は空き領域と同様に次のフレームのため
に使うことができるが、これらはバッファ領域中で分散
した配置となるため、従来の方法では効率のよいバッフ
ァ管理が行えない。
However, in connection devices that connect multiple communication networks, it is generally difficult to determine in real time whether or not a frame needs to be received, so the determination is often made after all frames have been stored in a buffer. In such a case, the buffer area in which frames that are found to be unnecessary can be used for the next frame in the same way as free space, but these will be distributed in the buffer area. , conventional methods cannot perform efficient buffer management.

従来の第1の方法はバッファのはしから順に格納してゆ
く方法で、バッファ管理は簡単でただ単にカウンターを
進めていけばよい。また従来の第2の方法はバッファ領
域を小領域に分割しそれら小領域のつながりを自由に設
定できる方法でありデータチェイニング法と呼ばれてい
る。
The first conventional method is to sequentially store data from the edge of the buffer.Buffer management is simple, and all you have to do is advance the counter. A second conventional method is a method in which the buffer area is divided into small areas and connections between these small areas can be set freely, and is called a data chaining method.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の第1の方法ではバ、ツファは常にはしか
ら順にしか使えないため・、必要ないことが判明してい
るフレームであってもその前に処理の終っていない必要
なフレームが格納されている場合には、その不必要フレ
ームの格納されているバッファ領域を用いることができ
ないため効率が悪いという欠点がある。また従来の第2
の方法によれば、たとえ空き領域が分散し5ていてら、
塞がっている領域を飛ばして空いている領域をつないで
使うことができるので第1の方法のような無駄は生じな
い。しか1−この第2の方法では頻繁に不必要フレーム
の受信による歯抜けがあった場合にはバッファ領域は徐
々に細分化されてゆき、細分化された領域のつながりの
管理が非常に複雑になることが予想されるという問題点
がある。
In the first conventional method described above, the frames can only be used in order from the edge to the edge. Therefore, even if a frame is known to be unnecessary, a necessary frame that has not yet been processed is stored before it. If the unnecessary frames are stored, the buffer area in which the unnecessary frames are stored cannot be used, resulting in poor efficiency. Also, the conventional second
According to the method, even if the free space is distributed 5,
Since the occupied areas can be skipped and the empty areas can be used by connecting them, there is no waste as in the first method. However, 1 - In this second method, if there are gaps due to frequent reception of unnecessary frames, the buffer area will be gradually fragmented, and management of the connections between the fragmented areas will become very complicated. The problem is that it is expected that this will happen.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は受信フレームを格納するバッファを複数の領域
に分割し、受信フレームを交互にこの複数のバッファ領
域に格納してゆき、他のバッファ領域に受信している間
にすでに受信したフレームの判別を行い、もし不必要な
フレームであった場合には、その受信バッファのアドレ
スを指定するアドレスカウンターを元に戻すことにより
、両バッファ共必要なフレームが順に格納されることを
可能とする受信バッファ管理装置である。
The present invention divides a buffer for storing received frames into multiple areas, stores the received frames alternately in the multiple buffer areas, and determines which frames have already been received while the received frames are being received in other buffer areas. If the received frame is an unnecessary frame, the address counter that specifies the address of the receive buffer is reset to the original value, allowing both buffers to store the necessary frames in order. It is a management device.

本発明の受信バッファ管理装置は、通信装置の受信部に
おいて、受信フレームを格納する複数領域に分割された
バッファと、この複数のバッファ領域に対して書込みお
よび読出しアドレスを指定するアドレス発生回路と、受
信制御装置よりフレームの受信を示す受信信号を入力し
受信フレームを前記複数のバッファ領域に順に格納して
ゆくための順序回路と、すでに受信したフレームの要不
要の判別を行いもし不必要なフレームであった場合には
その受信バッファのアドレスを指定する前記アドレス発
生回路の再設定を指示する判別制御装置とからなること
を特徴とする。
A reception buffer management device of the present invention includes, in a reception unit of a communication device, a buffer divided into a plurality of areas for storing received frames, an address generation circuit that specifies write and read addresses for the plurality of buffer areas, A sequential circuit inputs a reception signal indicating frame reception from a reception control device and sequentially stores the received frames in the plurality of buffer areas, and a sequential circuit that determines whether already received frames are necessary or unnecessary, and stores unnecessary frames if they are unnecessary. If so, the present invention is characterized by comprising a determination control device which instructs resetting of the address generation circuit to designate the address of the reception buffer.

〔実施例〕〔Example〕

次に本発明の実施例について図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.

第1図は本発明の受信バッファ管理装置の一実施例を示
すブロック図で、バッファを2つの領域に分けた場合を
示している。第1図において、1は受信制御装置、2は
受信バッファ管理装置である。受信制御装置1は伝送路
上の情報フレームを取り込んでデータバス3上に流すと
共に受信信号を出力する。順序回路4は受信フレームご
とに第1のバッファ5と第2のバッファ7を交互に選び
、各々に対応したアドレス発生回路6および8に信号を
出す。順序回路4で指定された方のアドレス発生回路6
または8は各々のバッファ5または7にアドレスを与え
受信フレームを格納する。受信の終了を受信制御装置1
からの受信信号により知った順序回路4は判別制御袋W
9に判別を指令する。判別制御装置9はたった今受信し
た方のバッファから受信フレームの特定の位置に書かれ
た制御情報領域を読み込み、受信する必要のあるフレー
ムであるかどうかの判別を行う。判別の結果、不必要な
フレームであることが判明した場合には、判別制御装置
9は対応するアドレス発生装置6または8にリセット信
号を出す。リセット信号を受けたアドレス発生回路は書
き込み用のアドレスカウンター(図示省略)をこの不必
要なフレームを受信する前の値に戻し次のフレームの受
信に備える。これらの操作を1フレーム受信する毎に、
しかも最小フレームの受信時間以内に行えば、連続して
複数フレームを受信する場合でも、次に同一のバッファ
が使われる前に書込みアドレスのリセットが終了してい
るため、常に必要フレームだけが連続領域に格納される
FIG. 1 is a block diagram showing an embodiment of the reception buffer management device of the present invention, in which the buffer is divided into two areas. In FIG. 1, 1 is a reception control device, and 2 is a reception buffer management device. A reception control device 1 takes in information frames on a transmission path, sends them onto a data bus 3, and outputs a reception signal. The sequential circuit 4 alternately selects the first buffer 5 and the second buffer 7 for each received frame and outputs signals to the corresponding address generation circuits 6 and 8, respectively. Address generation circuit 6 specified by sequential circuit 4
or 8 gives an address to each buffer 5 or 7 to store the received frame. The reception control device 1 indicates the end of reception.
The sequential circuit 4 learned from the received signal from the discrimination control bag W
9 to make a determination. The determination control device 9 reads the control information area written at a specific position of the received frame from the buffer that has just been received, and determines whether the frame needs to be received. As a result of the determination, if the frame is found to be unnecessary, the determination control device 9 issues a reset signal to the corresponding address generator 6 or 8. Upon receiving the reset signal, the address generation circuit returns a write address counter (not shown) to the value before receiving this unnecessary frame and prepares for reception of the next frame. Each time one frame of these operations is received,
Furthermore, if you do this within the minimum frame reception time, even if you receive multiple frames consecutively, the write address will have been reset before the same buffer is used next time, so only the necessary frames will always be in the continuous area. is stored in

なお、上記実施例ではバッファを2つの領域に分割して
用いているが、3つ以上の領域に分割することも考えら
れる。
In the above embodiment, the buffer is divided into two areas, but it is also conceivable to divide it into three or more areas.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、不必要なフレーム
を頻繁に受信する場合であっても複雑なチェイニングの
操作なしで、単にカウンターを1フレ一ム分前に戻す操
作だけで、バッファを無駄なくはしから詰めて使うこと
ができる効果がある。
As explained above, according to the present invention, even if unnecessary frames are frequently received, the buffer can be saved by simply returning the counter one frame to the previous one without the need for complicated chaining operations. It has the effect of being able to be used by filling it with chopsticks without wasting it.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の受信バッファ管理装置の一実施例を示
すブロック図である。 1・・・受信制御装置、2・・・受信バッファ管理装置
、3・・・データバス、4・・・順序回路、5,7・・
・バッファ、6.8・・・アドレス発生回路、9・・・
判別制御装置。 l:“ご、゛ 代理人 弁理士  内 原  晋− ぐ3ゴ“j
FIG. 1 is a block diagram showing an embodiment of a reception buffer management device of the present invention. DESCRIPTION OF SYMBOLS 1... Reception control device, 2... Reception buffer management device, 3... Data bus, 4... Sequential circuit, 5, 7...
・Buffer, 6.8...Address generation circuit, 9...
Discrimination control device. 1: “Representative Patent Attorney Susumu Uchihara”

Claims (1)

【特許請求の範囲】[Claims] 通信装置の受信部において、受信フレームを格納する複
数領域に分割されたバッファと、この複数のバッファ領
域に対して書込みおよび読出しアドレスを指定するアド
レス発生回路と、受信制御装置よりフレームの受信を示
す受信信号を入力し受信フレームを前記複数のバッファ
領域に順に格納してゆくための順序回路と、すでに受信
したフレームの要不要の判別を行いもし不必要なフレー
ムであった場合にはその受信バッファのアドレスを指定
する前記アドレス発生回路の再設定を指示する判別制御
装置とからなることを特徴とする受信バッファ管理装置
In the reception unit of the communication device, there is a buffer divided into multiple areas for storing received frames, an address generation circuit that specifies write and read addresses for the multiple buffer areas, and a reception control device that indicates frame reception. A sequential circuit inputs a received signal and sequentially stores the received frames in the plurality of buffer areas, and a sequential circuit that determines whether already received frames are necessary or unnecessary, and if the received frames are unnecessary, stores the received frames in the received buffer area in sequence. 1. A reception buffer management device comprising: a determination control device for instructing resetting of said address generation circuit to specify an address of said reception buffer management device.
JP62057323A 1987-03-11 1987-03-11 Reception buffer management equipment Pending JPS63222549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62057323A JPS63222549A (en) 1987-03-11 1987-03-11 Reception buffer management equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62057323A JPS63222549A (en) 1987-03-11 1987-03-11 Reception buffer management equipment

Publications (1)

Publication Number Publication Date
JPS63222549A true JPS63222549A (en) 1988-09-16

Family

ID=13052370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62057323A Pending JPS63222549A (en) 1987-03-11 1987-03-11 Reception buffer management equipment

Country Status (1)

Country Link
JP (1) JPS63222549A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04101232A (en) * 1990-08-20 1992-04-02 Nec Corp Information processing unit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5535571A (en) * 1978-09-06 1980-03-12 Fujitsu Ltd Communication control system
JPS6240525A (en) * 1985-08-19 1987-02-21 Fujitsu Ltd Data transfer buffer system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5535571A (en) * 1978-09-06 1980-03-12 Fujitsu Ltd Communication control system
JPS6240525A (en) * 1985-08-19 1987-02-21 Fujitsu Ltd Data transfer buffer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04101232A (en) * 1990-08-20 1992-04-02 Nec Corp Information processing unit

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