JPS5535571A - Communication control system - Google Patents

Communication control system

Info

Publication number
JPS5535571A
JPS5535571A JP10935578A JP10935578A JPS5535571A JP S5535571 A JPS5535571 A JP S5535571A JP 10935578 A JP10935578 A JP 10935578A JP 10935578 A JP10935578 A JP 10935578A JP S5535571 A JPS5535571 A JP S5535571A
Authority
JP
Japan
Prior art keywords
reception
reception buffer
holding device
head address
characters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10935578A
Other languages
Japanese (ja)
Other versions
JPS6119145B2 (en
Inventor
Yoshihiko Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10935578A priority Critical patent/JPS5535571A/en
Publication of JPS5535571A publication Critical patent/JPS5535571A/en
Publication of JPS6119145B2 publication Critical patent/JPS6119145B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To secure an effective use of the reception buffer as well as to reduce the ineffective interruption to the CPU by transferring the contents of the head address holding device to the storage destination address indicating device of the reception characters and then storing the characters received next into the same reception buffer region again. CONSTITUTION:The head address holding device of reception buffer region 19 is installed within communication control unit 1 along with reception character storage destination address indicating device 14 of region 19. Thus the characters received at unit 1 are stored in sequence into the reception buffer addresses indicated by device 14, and at the same time the reception character blocks are assembled. In the cource of after assembly 5 of the reception character blocks, some error is detected for the reception blocks. In such case, the contents of the head address holding device is transferred to device 14, and the characters received next are stored again into the same region19. In such way, the reception buffer can be utilized effectively, at the same time reducing the ineffective interruption to CPU3.
JP10935578A 1978-09-06 1978-09-06 Communication control system Granted JPS5535571A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10935578A JPS5535571A (en) 1978-09-06 1978-09-06 Communication control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10935578A JPS5535571A (en) 1978-09-06 1978-09-06 Communication control system

Publications (2)

Publication Number Publication Date
JPS5535571A true JPS5535571A (en) 1980-03-12
JPS6119145B2 JPS6119145B2 (en) 1986-05-15

Family

ID=14508116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10935578A Granted JPS5535571A (en) 1978-09-06 1978-09-06 Communication control system

Country Status (1)

Country Link
JP (1) JPS5535571A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63222549A (en) * 1987-03-11 1988-09-16 Nec Corp Reception buffer management equipment
JPH01109837A (en) * 1987-10-23 1989-04-26 Nec Corp Fifo device for frame reception

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63222549A (en) * 1987-03-11 1988-09-16 Nec Corp Reception buffer management equipment
JPH01109837A (en) * 1987-10-23 1989-04-26 Nec Corp Fifo device for frame reception

Also Published As

Publication number Publication date
JPS6119145B2 (en) 1986-05-15

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