JPS6119145B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication control method, and more particularly to a communication control method in a system using a transmission control procedure for continuously transferring transmission blocks.

A communication control system generally consists of a communication control device that receives data from a line and performs character assembly and character processing, a main storage device that stores transmission block data transferred from the communication control device, and a main storage device that stores transmission block data transferred from the communication control device. It is equipped with a central processing unit that processes transmission block data.

Here, a reception buffer is prepared for each transmission block in the main memory, and the received characters received and assembled by the communication control device are sequentially stored in this reception buffer. The present invention attempts to utilize this reception buffer effectively.

Figure 1 shows one of the transmission block sequences that are transmitted sequentially.
As an example, assume that an error has now occurred in the second block.

FIG. 2 is a diagram showing how to use a conventional receive buffer. A reception buffer is assigned to each transmission block, and transmission data blocks 1, 2, 3, 4, . . . are sequentially stored in reception buffers 1, 2, 3, 4, . Even if an error occurs in block 2 as shown in FIG. 1, block 2 will be stored in reception buffer 2. here,
A data block in which an error has occurred is an invalid block and should be discarded. Conventionally, software intervenes to detect the erroneous data block and invalidate the receive buffer that had stored the erroneous data block, thereby making the receive buffer available for reuse as an empty buffer.

In other words, in the conventional system, even if a block with an error was received, it was stored as is in the reception buffer, so the block with the error invalidates the reception buffer until the buffer is invalidated by software intervention. was occupied by
Also, since an error block was received, an invalid interrupt was made to the central processing unit.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks, make effective use of the reception buffer, and reduce invalid interruptions to the central processing unit. In a communication control system in which a communication control device including a transfer control circuit transfers received characters received from a line to a reception buffer area in a storage device provided separately from the communication control device, the communication control device includes a buffer area in the reception buffer area. The apparatus comprises a head address holding means and a received character storage destination address indicating means in the receiving buffer area, and sequentially stores the received characters received by the communication control device in the receiving buffer address specified by the received character storage destination address indicating means. At the same time, when a received character block is assembled, and an error is detected in the received block during or after the received character block is assembled, the contents of the first address holding means are transferred to the received character storage destination address indicating means. The present invention is characterized in that the received characters that are transferred and then received are stored again in the same receiving buffer area.

That is, the method of using the reception buffer according to the present invention is as shown in FIG. 3. When an error is detected in the data block being received, the reception of the block is interrupted and the data is returned to the beginning of the reception buffer 2. Therefore, when the next normal block 3 is received, it will be stored in the reception buffer 2.

Next, the present invention will be explained in detail with reference to the drawings. Fourth
The figure is a block diagram of a communication control system according to an embodiment of the present invention. In FIG. 4, 1 is a communication control device, 2 is a main storage device, 3 is a central processing unit, 4 is a common bus, 5 is a character assembly circuit, 6 is a character processing circuit, 4 is a character transfer control circuit, and 8 is a monitor. circuit, 9
is the CCW address register (CCWA), 10 is the assembly buffer (AB), 11 is the character buffer (CB), 12 is the buffer start address holding register (BSA), 13 is the AND circuit, 1
4 is a received character storage destination buffer address holding register (BCA), 15 is a buffer end address holding register (BEA), 16 is a receiving command holding register (READ), 17 is a data buffer, 18 is a channel command word (CCW), 19 is the receiving buffer.

The operation of FIG. 4 is as follows.

The software of the central processing unit 3 is stored in the main memory 2
Above, channel command word (CCW) 18 and
A reception buffer 19 accompanying CCW is created.

The CCW includes the type of input/output command, designation of the command chain, data chain, etc., and the start and end addresses of the receive buffer. ), only the receiving buffer end address (BEA) is shown. Next, the central processing unit 3 stores data on the main memory 2.
After storing the CCW address in the CCW address register (CCWA) 9 in the communication control device 1, the communication control device 1 is activated. The communication control device 1 receives the activation from the central processing device 3 through the monitor circuit 8 . The activated monitor circuit 8 fetches the CCW on the main memory address indicated by CCWA 9 and stores its contents in the corresponding register of the character transfer control circuit 7. In other words, among the CCWs 18 on the main memory 18, the READ command is READ1.
BSA is stored in BSA12,
BEA is stored in BEA15. At this time, BCA1
4 stores the contents of the BSA. Thereafter, the monitor circuit 8 sends a command to the character processing circuit 6 to start it up. Since the current command is a READ command, the character processing circuit 6 performs character reception processing. The received characters assembled in AB10 of the character assembly circuit 5 are temporarily stored in CB11, and then transferred to the character processing circuit 6.
sent to. The character processing circuit 6 detects transmission control characters, performs block check addition, etc. on the received characters, stores the received characters in the DB 17 in the character transfer control circuit 7, and stores the received characters in the main storage 2. The character transfer control circuit 7 is requested to transfer the text to the buffer 19. The character transfer control circuit 7 stores the received characters in the DB 17 at the reception buffer address indicated by the BCA 14. BCA
14 is incremented by 1 each time a received character is stored in the reception buffer address. If the last character of the block is successfully received,
The character processing circuit 6 requests the monitor circuit 8 to terminate the command and fetch the next command. At the end of the command, the monitor circuit 8 updates the BEA on the main memory 2 to the value of the BCA 14, and notifies the central processing 3 of the interrupt status. As a result, the software of central processing unit 3 is activated again.
A CCW and an accompanying receive buffer are created, and the same operations as above are repeated.

The above is a case where the receiving operation is executed normally, but on the other hand, when a transmission block error is detected in the character processing circuit 6, the following happens.

Character processing circuit 6 sends an error detection signal to character transfer control circuit 7. As a result, the AND circuit (AND) 13 in the character transfer control circuit 7 opens and the BSA1
The buffer start address (BSA) held in BCA 2 is moved to BCA 14, and BCA 14 is updated to return to its previous state. Character processing circuit 6 resets its current state to prepare for reception of the next correct block. As a result, the next received block is automatically stored again in the block in which the error block was stored, without intervention from the central processing unit.

Although the above description relates to the operation in the event of a transmission block error, the present invention is also applicable to the processing of frames of less than 32 bits in high-level data link control procedures. In high-level data link control procedures, a normal frame is at least 32 bits long, so conventionally a buffer for 32 bits was provided in the communication control equipment to detect and invalidate frames shorter than 32 bits. Ta. On the other hand, each time a byte is received, a byte count that can be counted up to 4 is created, and when a frame with a count value of 3 or less is received, the error detection signal line in FIG. 4 is set to 1 state, Similarly to the above embodiment, if the reception buffer 19 on the main storage device 2 is invalidated and reused, the communication control device 1
It is no longer necessary to provide a 32-bit buffer as in the past, and the amount of hardware can be reduced.

As explained above, the present invention holds the start address of the reception buffer in the communication control device,
If the correct transmission block is received, the next transmission block is stored in a new reception buffer, but
When an erroneous or invalid transmission block is received, the next transmission block is stored from the head address of the reception buffer that was originally held, so the reception buffer can be used effectively.

It also has the advantage of reducing invalid interruptions to the central processing unit due to reception of erroneous blocks.

[Brief explanation of the drawing]

FIG. 1 is an example of a transmission block sequence, FIG. 2 is a diagram showing how to use a conventional receiving buffer, FIG. 3 is a diagram showing how to use a receiving buffer according to the present invention, and FIG. 4 is a diagram showing how to use a receiving buffer according to the present invention. 1 shows a block diagram of a communication control system according to an embodiment. In FIG. 4, 1 is a communication control device, 2 is a main memory, 3 is a central processing unit, 7 is a character transfer control circuit, 12 is a buffer start address holding register, and 14 is a buffer address holding destination for storing received characters. Register 19 is a receiving buffer.

Claims (1)

[Claims] 1. In a communication control system that transfers received characters received from a line in a communication control device including a character assembly circuit, a character processing circuit, and a character transfer control circuit to a reception buffer area in a storage device that is provided separately from the communication control device. , the communication control device includes means for holding the start address of the reception buffer area, and means for indicating a received character storage destination address in the reception buffer area, and the received character storage destination address instruction means for transmitting the received characters received in the communication control device. While assembling a received character block while sequentially storing it in the receiving buffer address indicated by the above, when an error is detected in the received block during or after assembling the received character block, the start address holding means is A communication control system characterized in that the content is transferred to the received character storage destination address indicating means, and the next received character is stored again in the same reception buffer area.