JPS5972533A - Direct memory access system - Google Patents

Abstract

PURPOSE:To increase effectively the processing speed of a microprocessor, by holding temporarily the address information, data and control information at a buffer part and transferring these information between an ROM or an R/WM and an external device. CONSTITUTION:A buffer part 9 consisting of the 1st-3rd buffer memories 6-8 is provided together with a microprocessor 1, an ROM2, an R/WM3, a DMA control part 4 and an external device 5. Then an address bus signal line 101, a data bus signal line 102 and a control bus signal line 103 are connected to the part 9. The processor 1 always gives an access to the R/WM3 via the buffer 9 when no interruption signal 109 exists. While the processor 1 sets the buffer part 9 at a high impedance via the control part 4 when the signal 109 exists. Then a DMA confirming signal is delivered to the device 5 to have a DMA mode between the R/WM3 and the device 5. Meanwhile the processor 1 reads out the ROM2 and accepts an interruption. Thus the processing speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a direct memory access method in a system having a microprocessor, and particularly to a direct memory access method that directly accesses read/write memory accessed by the microprocessor.

An example of a conventional direct memory access method is shown in FIG. In FIG. 1, the direct memory access method is realized by comprising a microprocessor 1, a read-only memory 2, a read/write memo I 73, a DMA control section 4, and an external device 5. That is, in the conventional direct memory access method of this type, as shown in FIG. A hold confirmation signal is sent from the microprocessor to the DMA control section 4 via the microprocessor.

A DMA request signal is sent from the external device 5 to the DMA control section 4 via the signal line 106, and thereby a hold request signal is sent to the microprocessor 1 via the signal line 104. When the system enters the hold state, a DMA confirmation signal is sent from the DMA control unit 4 to the external device 5 via the signal line 107, and the DMA control unit 4 generates addresses for the read/write memory 3 and controls its write/read operations. Start. The read/write memory 3 can be directly accessed by an external device 5 under the control of the DMA control section 4. The read-only memory 2 stores programs executed by the microprocessor 1. - Also, the read/write memory 3 can temporarily hold this program, and the external device 5 can also perform DMA mode transfer.

When the external device 5 does not request access to the read/write memory 3, the microprocessor 1 sends an address bus signal M101, a data bus M-IHo2,
The read/write memory 3 can be accessed at any time via the control bus signal line 103. When the external device 5 requests access to the read/write memory 3, the external device 5 sends a DMA request signal to the DMA control unit 4 via the signal line 106. Therefore, in response to the DMA request signal sent from the external device 5 via the signal line 106, a hold request signal is sent from the DMA control section 4 to the microprocessor 1 via the signal line 104. At this time, the microprocessor 1 is in a hold state, and the address bus signal line 10
1, the data bus signal line 102, and the control bus signal line 103 are at a high level. At this time, the output impedance becomes high impedance, and a hold confirmation signal is sent out via the signal line 105. Therefore, the DMA control unit 4 transmits the DMA confirmation signal to the signal line 1 using the hoard confirmation signal received via the signal line 105.
Send on 07. At this time, the DMA control unit 4 generates address information for the read/write memory 3, sends out the address bus signal line 101K, and sends out the control bus signal l1.
4103, control of the write/read operation is started.

The external device 5 receives the DMA confirmation signal and performs DMA transfer to the read/write memory 3 using data on the address bus signal line 101, the data bus signal line 102, and the control bus signal m103. When the DMA request signal is no longer sent from the external device 105 via the signal line 106, the DMA control unit 4
The hold request signal is no longer sent to the read/write memory 3, and control of the read/write memory 3 is stopped. microprocessor 1
exits the hold state by stopping the hold request signal,
Program processing is restarted and the DMA transfer is completed.

In this case, there is a drawback in FIG. 1 that the microprocessor 1 enters a hold state while the DMA transfer is being performed, and program processing is interrupted. A further drawback is that a microprocessor that does not have a hold function cannot be used with this method.

An object of the present invention is to operate a DMA control unit in synchronization with the interrupt confirmation signal sent by the microprocessor, temporarily hold address information, data, and control information in a buffer unit, and store the address information, data, and control information in a read-only memory or a read-only memory. It is an object of the present invention to provide a direct memory access method which eliminates the drawbacks of the conventional method and effectively improves processing speed by exchanging information between a write memory and an external device.

The direct memory access method according to the present invention includes a microprocessor, a read-only memory, a read/write memory, an external device, a DMA control section, and first to third buffer sections (rough memory). That's what made me laugh.

The microprocessor is used to execute programs, and is connected to address bus signal lines, data bus signal lines, and control bus signal lines.・Read-only memory is for storing this program.0 External devices are read-only memory for storing the program to be executed by the microprocessor, and for temporarily storing this program. This is a device that can perform DMA transfer with read/write memory. The read/write memory is accessed by the microprocessor at any time, and can also be directly accessed by an external device.

The DMA control section controls the read/write memory, buffer section, etc. based on the interrupt confirmation signal sent from the microprocessor, and ends the control after a predetermined time. It consists of a buffer memory, between the microprocessor and the read/write memory, and includes an address bus signal line and a data bus signal line that connect the microprocessor and the external device. It exists between the control signal line and the control signal line, and is used to relay between the two. It will be retransmitted later.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the direct memory access method according to the present invention. In FIG. 2, the direct memory access method includes a microprocessor 1, a read-only memory 2, a read/write memory 3, a DMA control unit 4, an external device 5, and first to third buffers. This is realized by including a buffer section 9 consisting of memories 6 to 8.

The address signal line 101 of the microprocessor 1 is connected to the only memory 2, and is further connected to the read/write memory 3 and D via the first buffer memory 6.
It is connected to the MA control section 4 and an external denostation 5. A data bus signal line 102 of the microprocessor 1 is connected to a read-only memory 2, and further connected to a read/write memory 3 and an external device 5 via a second buffer memory 7. The control bus signal of the microprocessor 1 is connected to the read-only memory 2, and further connected to the read/write memory 3, the DMA control section 4, and the external device 5 via the third buffer memory 8. The interrupt request signal is input to the microprocessor l via a signal line 109 from an input terminal 1° for the interrupt request signal. An interrupt confirmation signal is sent from the microprocessor 1 to the DMA control unit 4 via the signal line 108.

The buffer control signal sent from the DMA control unit 4 via the signal line 110 is transmitted to the first to third backup memories 6 to 6.
8, and a DMA confirmation signal is input to the external device via the signal line 107.

Microprocessor 1 connects address bus signal line 1 old and data bus signal #i! The program is read from the read-only memory 2 via the control path signal line 102 and the control path signal line 103, and the read program is executed. When no interrupt request signal is present on the signal line 109, the microprocessor 1 can access the read/write memory 3 via the buffer section 9 at any time. When an interrupt request signal is input from the interrupt request input terminal lO via the signal line 109, the microprocessor 1
An interrupt confirmation signal is sent out via the , and interrupt acceptance processing begins. The microprocessor 1 is configured so that the need to access the read/write memory 3 does not arise until a predetermined period of time has elapsed from the start of the interrupt process. The length of this time, that is, the length of time T1, can be known in advance by checking the program of the microprocessor 1. Signal line 1
When the interrupt confirmation signal is input to the DMA control unit 4 via the signal line 08, a buffer control signal is sent via the signal line 110, and the output of the buffer unit 9 becomes a high impedance state. Therefore, respective signals are applied from the buffer section 9 to the read/write memory 3 and the external device 5 via the address bus signal line 1 old, the data bus signal line 102, and the control bus signal line 103. At this time,
DMA to external device 5 via signal line 107
i-address bus signal line 101 to which the confirmation signal is sent
The above signal generates an address for the read/write memory 3, and the signal on the control bus signal line 103 starts controlling the write/read operation. DM on signal line 107
The A confirmation signal causes the address bus signal line 101, the data bus signal line 102, and the control bus signal line 10 to
The data sent to 3 and 3 is transferred between the external device 5 and the read/write memory 3 in DMA mode.

During this time, the microprocessor 1 can read the program from the read-only memory 2 and can execute interrupt processing.

The DMA control section 4 ends the control of the buffer section 9 before the end of the time period T1, stops the DMA confirmation signal being sent to the signal line 107, and ends the DMA transfer. Thereafter, the microprocessor 1 can access the read/write memory 3. Normally, interrupt requests occur periodically, so periodic rDMA transfers are performed.

As explained above, the present invention operates the DMA control section in synchronization with the interrupt confirmation signal sent from the microprocessor, holds address information, data, and control information in the buffer section and reads them. Only memory, which includes information, can effectively improve the processing speed of a microprocessor because it does not need to hold the state of the microprocessor by exchanging information between the read/write memory and external devices. This has the advantage that a microprocessor without a hold function can also be used for DMA transfer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a configuration for realizing a direct memory access method according to the prior art. Second
The figure is a block diagram showing an embodiment for realizing the direct memory access method according to the present invention. 1...Microprocessor 2...Read only memory 3...Read/write memory 4...DMA control unit 5...External device 6~
8... Buffer memory 9... Buffer section 10.
...Interrupt request signal input terminals 101 to 110...Signal line Patent applicant NEC Corporation Representative Patent attorney Inoro Jusai Figure 1 - Figure 2 19

Claims (1)

[Claims] a microprocessor for executing a program; a read-only memory for storing the program; an external device for DMA transfer between the read-only memory; The device includes a read/write memory that can be directly accessed by an external device, and a DMA control unit that controls the read/write memory based on an interrupt confirmation signal sent from the microprocessor and ends the control after a predetermined time. In the direct memory access method realized by the method, an address bus signal line and a data bus signal line connecting between the microprocessor and the read/write memory and between the microprocessor and the external device;
A direct memory access system characterized in that it is realized by comprising a buffer section consisting of first to third buffer memories that are located between a control bus signal line and relay the connection.