JPS60158750A - High-speed communication system - Google Patents

Abstract

PURPOSE:To reduce the load of a computer and to reduce the execution time of a control program by providing a circuit between a circuit protocol LSI and a computer to share a part of the process that is executed by the computer when an interruption is produced from said LSI. CONSTITUTION:A terminal device 6, a computer 2 and a circuit control protocol LSI1 are connected via a data bus 9 and then connected to a memory 4, a DMA cintroller 3 and an interruption control circuit 10. The circuit 10 is connected to the LSI1 and the computer 2 via an interruption signal line 7. The memory 4 contains a control program store area (a), a transmission/reception data buffer area (b) and a control parameter area (c). The area (c) stores the DMA information, factors of transmission/reception interruptions, etc. When an interruption is produced, the circuit 10 shares a part of the process to be executed by the computer 2 by the interruption given from the LSI1. This reduces the load of the computer 2 and decreases the execution time of the control program.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high-speed communication system, and more particularly to a control system for a line interface circuit of a terminal device connected to a high-speed communication line.

Prior Art A method for configuring a line interface circuit of a terminal device connected to a high-speed communication line using a line control protocol LSI is well known. A line control protocol LSI converts transmitted data into a signal format that conforms to the line control protocol. Function to serially convert and send, function to convert received data to parallel data.

It operates under the control of the computer, including an automatic check sequence sending function, an automatic checkerage function, and a function to notify the computer of the completion of transmission/reception operations, the occurrence of an error, etc. using an interrupt.

In other words, when initializing the line control protocol L'S I and when an interrupt occurs due to completion of transmission/reception or error occurrence, appropriate control parameters are issued according to the cause of the interrupt in order to transmit/receive the next data normally. It is necessary to execute a control program to However, when a terminal device is connected to a high-speed communication line, the operating speed of the computer is slow compared to the high-speed line speed, and it takes time to execute the interrupt process when the transmission/reception is completed. This method has disadvantages in that the reception preparation operation for receiving data is slow, and it takes time until the next data is sent when the transmission is completed, which impedes high-speed data transmission.

In addition, in order to perform high-speed data transfer between the line control protocol LSI and the transmit/receive data buffer in memory,
In order to perform DMA transfer (direct memory access) under the control of the MA controller, the computer must obtain the information (for example, the address of the transmit/receive buffer) required for the DMA transfer of the next transmit/receive data when an interrupt occurs for the completion of transmit/receive. It is necessary to notify the DMA controller. This processing further increases the burden on the computer when an interrupt occurs and further increases the processing time.

OBJECTS OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks, and to create a circuit between the line control protocol LSI and the computer that shares a part of the processing that the computer should execute when an interrupt occurs from the line control protocol LSI. It is an object of the present invention to provide a high-speed communication method that can reduce the load on a computer and shorten the execution time of a control program by adding the information to the computer.

Composition of the Invention The high-speed communication system of the present invention is connected to a high-speed line, performs serial-to-parallel conversion of transmitted and received data, automatically transmits a check sequence,
A line control protocol LSI that has functions such as automatic checking, completion of transmission/reception operations, and interrupts to the computer when an error occurs, etc., a DMA controller that controls DMA transfer of the transmission/reception data buffer, a control program storage area, and a transmission/reception buffer area. In the high-speed communication method, the memory is provided with a memory to be issued to the line control protocol LSI, and a computer that controls these operations to interface between the high-speed line and the terminal device. It has a parameter area for pre-memorizing control parameters, interrupt factors, information regarding the transmitting/receiving buffer to be notified to the DMA controller, and the memory area is used when an interrupt occurs from the line control protocol LSI. an interrupt control that reads necessary control parameters from the DMA controller and issues them to the line control protocol LSI, simultaneously notifies the DMA controller of buffer information, writes an interrupt cause to the memory area, and sends an interrupt signal to the computer; It is characterized by being equipped with a circuit.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

That is, the terminal device 6, the computer 2, and the line control protocol LSII are connected to the data bus 9, and the transmitted and received data is DMA-transferred to the transmitted and received data buffer under the control of the DMA controller 3. Reference number 8 is the DMA request line.

The line control protocol LSII performs parallel-to-serial conversion of transmitted/received data, interrupts when transmission/reception is completed, or when an error occurs, etc., as in the past.

However, in this embodiment, the interrupt control circuit 10 is connected to the data bus 9, and interrupts from the line control protocol LSII are inputted to the interrupt control circuit IO through the interrupt signal line 7, and are sent to the computer 2. The interrupt signal is output from the interrupt control circuit 10 to the computer 2 via an interrupt signal line 7'. The memory 4 connected to the data bus 9 includes a control program storage area a for storing control programs, a transmission/reception data buffer area b for temporarily storing transmission and reception data, and a storage area for storing control parameters and other information. It has a parameter area C.

FIG. 2 is a diagram showing an example of setting the memory area in the parameter area C. Control parameter area 1
1 is preset with 3Hol (-!-end of interrupt) commands, error reset commands, etc. to be issued to the line control protocol LSII when an interrupt occurs. In the reception DMA information area 12, parameters indicating the DMA transfer destination of the reception data, that is, the address and length of the reception data buffer, are set. The transmission DMA information area 13 is an area for setting parameters indicating the buffer address and length of transmission data. The reception interrupt cause area 14 and the transmission interrupt cause area 15 are areas used by the interrupt control circuit 10 to notify the computer 2 of an interrupt occurrence factor.

Next, we will explain the operation at the time of completion of reception in this embodiment.0 When a reception completion interrupt occurs from the line control protocol LSII and is notified to the interrupt control circuit IO via the interrupt signal line 7, the interrupt control circuit 10 outputs necessary control parameters from the control parameter area 11, and these parameters are input to the line control protocol LSII via the data bus 9. Also, the address information of the receive data buffer to which the next received data should be transferred is read from the receive DMA information area 12 and notified to the DMA controller 3, and a parameter indicating normal completion of reception is set in the receive interrupt cause area 14. After that, an interrupt is made to the computer 2 via the interrupt signal line 7'.

After the computer 2 reads the interrupt cause from the reception interrupt cause area 14 and confirms that the reception has been completed normally,
Buffer information for the next data to be received is prepared in the reception DMA information area 12. This buffer information is sent to the DMA from the interrupt control circuit 10 when the next reception completion interrupt occurs.
This is information for notifying the controller 3. In this way, by preparing all the various parameters required when a reception interrupt occurs in the parameter area C in advance, the 1st interrupt control circuit IO can perform prompt processing according to the cause of the interrupt occurrence. can. The processing executed by the computer 2 upon completion of reception is limited to confirmation of completion of reception and preparation of the reception DMA information area 12, so the program execution time is significantly shortened and the next data can be received quickly. It has the effect of being able to. Regarding the transmission operation, by preparing the necessary parameters in the parameter area C, the interrupt control circuit l
High-speed processing using O is possible.

Effects of the Invention As described above, in the present invention, a parameter area is provided in the memory, parameters necessary for processing when an interrupt occurs are prepared in advance, and the above-described operations are performed by controlling the interrupt control circuit. Since the configuration is such that an interrupt to the computer and preparation for transmission/reception are executed based on the parameters read from the parameter area, the load on the computer is reduced and high-speed processing becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the configuration of a parameter area in the above embodiment. In the figure, two line control protocol LSIs are shown. 2: Computer, 3: DMA controller, 4:
Memory, 5: High-speed line, 6: Terminal device, 7: Interrupt signal line, 8: DMA request line, 9: Data bus, IO: Interrupt control circuit, 112 control parameter area, 12: Reception D
MA information area, 13: Transmission DMA information area, 14:
Reception interrupt cause area, 15: Transmission interrupt cause area, a:
Control program storage area, b: transmission/reception data buffer area, C: parameter area. Applicant: NEC Corporation Agent: Patent Attorney: Toshimune Sumita

Claims (1)

[Claims] A line control protocol LSI that is connected to a high-speed line and has functions such as serial-parallel conversion of transmitted and received data, automatic transmission of check sequences, automatic checks, completion of transmission and reception operations, and interrupt functions to the computer when an error occurs, etc., and a transmission and reception data buffer. A high-speed controller that interfaces between the high-speed line and the terminal device, comprising: a DMA controller that controls DMA transfer; a memory having a control program storage area and a sending/receiving buffer area; and a computer that controls these operations. In the communication method, the memory is configured to store in advance control parameters to be issued to the line control protocol LSI, information regarding the 'M-inclusion factor, and transmission/reception buffers to be notified to the DMA controller. area, and the line control protocol LSI
When an interrupt is issued from the memory area, necessary control parameters are read from the memory area and issued to the line control protocol LSI, and at the same time, buffer information is notified to the DMA controller, and then the interrupt cause is written to the memory area, and the computer A high-speed communication method characterized by being equipped with an interrupt control circuit that sends an interrupt signal.