JP3548948B2 - Crossbar switch - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a crossbar switch, and more particularly to a crossbar switch used for switching a communication network.
[0002]
[Prior art]
FIG. 8 is a configuration diagram of a conventional crossbar switch. Referring to FIG. 8, a conventional crossbar switch includes one crossbar switch LSI X1, a memory M for storing transmission data inside the crossbar switch LSI, and whether or not next data can be transmitted to this memory. Status register T, and interface units IU1 to IU4 for connecting the bidirectional input / output ports 1 to 4 and the crossbar switch LSI.
[0003]
To describe the details of the crossbar switch LSI X1, a pair of transmission / reception paths provided corresponding to each of the interface units IU1 to IU4 are arranged so as to intersect at right angles to each other. A memory M for storing transmission data is provided, and a status register T is provided for each of these memories M. The status register T holds the state of the corresponding memory M.
[0004]
The data transmission path through which the interface unit transmits data to the crossbar switch LSI and the data reception path through which the interface unit receives data from the crossbar switch LSI are both unidirectional transfer paths. At a point where the data transmission path and the data reception path cross each other, a memory M for storing transmission data and a status register T indicating status information of the memory are connected.
[0005]
When transferring data from one port to another port, the interface unit needs to read the status register T, which is status information of the memory M, in order to transfer data to the memory M corresponding to the transfer destination port. In the configuration of FIG. 8, since the crossbar switch LSI can read the information of the status register T from the data receiving path, the interface unit can obtain the status information of the memory M corresponding to the transfer destination port. .
[0006]
[Problems to be solved by the invention]
Here, as shown in FIG. 9, the crossbar switch is generally configured by arranging a plurality of crossbar switch LSIs in a matrix. FIG. 9 shows a case where the four crossbar switches LSI X1-1, X1-2, X2-1, and X2-2 have a 2 × 2 matrix arrangement as shown in FIG. 9 for simplification. In this case, bidirectional input / output ports 1 to 8 are provided, and these ports are connected to respective transmission / reception paths of the crossbar switch LSI via interface units IU1 to IU8.
[0007]
In such a configuration, the interface unit IU1 needs to read the status information in the crossbar switches LSIX1-1 and X1-2, but the interface unit IU1 reads the status information in the crossbar switch LSIX1-1. However, the status information in the crossbar switches LSIX1-2 cannot be read. This is because the reception path of the interface unit IU1 is not connected to the crossbar switches LSIX1-2.
[0008]
As described above, in the conventional configuration, when the crossbar switch LSIs are arranged in a matrix, there is a problem that all the status information of the memory in the crossbar switch LSI into which each interface unit writes data cannot be obtained.
[0009]
As a method for solving such a problem, the number of connection lines may be increased so that each interface unit can read the memory status information of all the crossbar switch LSIs. However, increasing the number of connection lines increases the number of pins of the crossbar switch LSI. There is nothing else. However, since the crossbar switch LSI requires a very large number of input / output pins, such as 64 pins, only data pins per port, it is difficult to further increase the number of output pins.
[0010]
An object of the present invention is to provide a crossbar switch that enables a matrix arrangement of crossbar switch LSIs without newly increasing the number of output pins for status information.
[0011]
[Means for Solving the Problems]
According to the present invention, a plurality of bidirectional input / output ports,
An interface unit provided in correspondence with these bidirectional input / output ports and serving as an interface between the corresponding port and a pair of transmission / reception paths;
A plurality of receiving paths connected to the bidirectional input / output ports, each of which is disposed to intersect with each of the transmitting paths, provided at each intersection of these transmitting / receiving paths to store transmission data from the transmitting paths. A plurality of crossbar switch LSIs, each of which has a data memory capable of reading stored data to the receiving path and a status register indicating the state of the corresponding data memory provided in correspondence with these data memories, are arranged in a matrix, and A matrix circuit in which each corresponding transmission path is commonly connected and each corresponding reception path in the same column is commonly connected;
A crossbar switch including
A crossbar switch is provided, which includes a status mirror register provided corresponding to the data memory and capable of storing information of the status register.
[0012]
The status mirror register is accessible by the interface unit, and transfers data from a first port of the bidirectional input / output port to another second port. An interface unit corresponding to the second port reads status information of a memory connected to the interface unit corresponding to the first port from the status register, and reads the read information to an interface corresponding to the second port. This is characterized in that the data is written in the status mirror register. Further, the operation of the present invention will be described in which the interface unit corresponding to the first port reads the contents of the status mirror register connected to the interface corresponding to the second port. The interface unit of the receiving port reads the status information of the memory from the status register, writes it in the status mirror register connected to the interface unit of the transmitting port, and reads the information of the status mirror register by the interface unit of the transmitting port. The status information of all memories of the crossbar switch LSI arranged in a matrix can be obtained without newly increasing the number of output pins.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of a crossbar switch according to an embodiment of the present invention, and portions equivalent to those in FIGS. The crossbar switch of this embodiment includes four crossbar switches LSIX1-1, X1-2, X2-1, X2-2, a memory M for storing transmission data inside these crossbar switches LSI, and a memory M A status register T indicating whether the next data can be transmitted, a status mirror register R for temporarily storing information of a status register specified in advance, bidirectional input / output ports 1 to 8 and a crossbar switch LSI. It has interface units IU1 to IU8 to be connected.
[0014]
These four crossbar switch LSIs are arranged in a 2 × 2 matrix. The data transmission path through which the interface unit transmits data to the crossbar switch LSI and the data reception path through which the interface unit receives data from the crossbar switch LSI are both unidirectional transfer paths. At each of the points where the data transmission path and the data reception path intersect, a memory M for storing transmission data, a status register T indicating status information of the memory M, and an externally designated (specified from the interface unit) A) a status mirror register R for temporarily storing information of the status register;
[0015]
Next, the operation of the present invention will be described in detail with reference to the drawings. FIG. 2 is an operation explanatory view of the embodiment shown in FIG. A case where data is transferred from port 1 to port 8 will be described with reference to FIG. When transferring data from the port 1 to the port 8, the interface unit IU1 needs to read the status register T1-8, which is status information of the memory M1-8, in order to transfer data to the memory M1-8. However, the interface unit IU1 cannot directly read the status register T1-8 of the crossbar switch LSI2.
[0016]
Then, the interface unit IU8 reads the status register T1-8 and writes the information to the status mirror register R8-1. The information of the status register T1-8 is written into the status mirror register R8-1, and the interface unit IU1 reads the status mirror register R8-1, whereby the interface unit IU1 can obtain the status information of the memory M1-8. It is.
[0017]
Similarly, when transferring data from the port 8 to the port 1, the interface unit IU8 needs to read the status register T8-1, which is the status information of the memory M8-1, in order to transfer the data to the memory M8-1. However, the interface unit IU8 cannot directly read the status register T8-1 of the crossbar switch LSI3. Then, the interface unit IU1 reads the status register T8-1 and writes the information to the status mirror register R1-8. The information of the status register T8-1 is written into the status mirror register R1-8, and the interface unit IU8 reads the status mirror register R1-8, whereby the interface unit IU8 can obtain the status information of the memory M8-1. It is.
[0018]
Here, the interface unit IU will be described with reference to FIGS. When transmitting data to the crossbar switch LSI, the interface unit IU divides the data received from the corresponding port into 64 bytes and transmits the data to the crossbar switch LSI in 64 byte units as shown in FIG. The status register information ST and the status mirror register information SR are transmitted between 64-byte data. If there is no data to be transmitted, the status register information ST and the status mirror register information SR are repeatedly transmitted.
[0019]
The status register information ST includes information indicating to which port the immediately following 64-byte data is to be transferred. Each constituent bit of the status register information ST represents a transfer port number, and 64 bytes of data are stored in the memory M corresponding to the transfer destination port of the bit whose value is “1”.
[0020]
When the interface unit IU receives data from the crossbar switch LSI, as shown in FIG. 4, it receives 64 bytes of data from the crossbar switch LSI, and concatenates the divided 64 bytes of data to the original data size. Send to port. The status register information ST and the status mirror register information SR are transmitted between 64-byte data. If there is no data to be received, status register information ST and status mirror register information SR are repeatedly received.
[0021]
The status register information ST is information as to whether 64 bytes of data are stored in the memory M. Each constituent bit of the status register information ST indicates a transfer source port number, and the interface unit IU is a status register. When the value 1 ”in the information ST is detected, the crossbar switch LSI is instructed to transmit 64 bytes of data to the memory M corresponding to the source port of the bit of the value“ 1 ”. Will be received.
[0022]
The interface unit IU that has received the status register information ST converts the received status register information ST into the status mirror register information SR with the bit array as it is, and transmits the status mirror register information SR to the crossbar switch LSI as the status mirror register information SR. The status mirror register information SR received by the interface unit IU is information on whether data can be transmitted to each memory M in the crossbar switch LSI transmitted by the interface unit IU. That is, the total amount of data stored in the corresponding memory M can be determined by referring to the number of “1” of each configuration bit of the status mirror register information SR.
[0023]
FIG. 5 is a view showing a second embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 5, a configuration using a crossbar switch LSI corresponding to 2n ports is also possible. FIG. 6 is a view showing a third embodiment of the present invention, and the same parts as those in FIGS. As shown in FIG. 6, an m × n matrix configuration is also possible. Further, as in the fourth embodiment shown in FIG. 7, a configuration using a crossbar switch LSI using a bit slice method is also possible. The number of bits J to be sliced can be 1, 2, 4, 8, or 16 bits.
[0024]
【The invention's effect】
As described above, according to the present invention, the interface unit for transmitting data can temporarily obtain the status information of the destination memory by temporarily storing the information of the status register in the status mirror register. There is an effect that the matrix arrangement of the crossbar switch LSI is enabled without increasing the number of output pins.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating a crossbar switch according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating the operation of the crossbar switch according to the first embodiment of the present invention.
FIG. 3 is a time chart of transmission data of the interface unit IU.
FIG. 4 is a time chart of received data of the interface unit IU.
FIG. 5 is a configuration diagram illustrating a crossbar switch according to a second embodiment of the present invention.
FIG. 6 is a configuration diagram illustrating a crossbar switch according to a third embodiment of the present invention.
FIG. 7 is a configuration diagram illustrating a crossbar switch according to a fourth embodiment of the present invention.
FIG. 8 is a configuration diagram illustrating an example of a conventional crossbar switch.
FIG. 9 is a configuration diagram showing another example of a conventional crossbar switch.
[Explanation of symbols]
1-8 Port IU1-IU8 Interface Unit M Memory R Status Mirror Register S Status Register X1-1-X2-2 Crossbar Switch LSI

Claims (4)

Multiple bidirectional input / output ports,
An interface unit provided corresponding to these bidirectional input / output ports and interfacing the corresponding port with a pair of transmission / reception paths;
A plurality of receiving paths connected to the bidirectional input / output ports, each of which is disposed to intersect with each of the transmitting paths, provided at each intersection of these transmitting / receiving paths to store transmission data from the transmitting paths. A plurality of crossbar switch LSIs, each of which has a data memory capable of reading stored data to the receiving path and a status register indicating the state of the corresponding data memory provided in correspondence with these data memories, are arranged in a matrix, and A matrix circuit in which each corresponding transmission path is commonly connected and each corresponding reception path in the same column is commonly connected;
A crossbar switch including
A crossbar switch comprising a status mirror register provided corresponding to the data memory and capable of storing information of the status register. The crossbar switch according to claim 1, wherein the status mirror register is accessible by the interface unit. When transferring data from a first port of the bidirectional input / output port to another second port, an interface unit corresponding to the second port was connected to an interface unit corresponding to the first port. 3. The crossbar switch according to claim 2, wherein status information of a memory is read from the status register, and the read information is written to a status mirror register connected to an interface corresponding to the second port. . 4. The crossbar switch according to claim 3, wherein the interface unit corresponding to the first port reads the contents of a status mirror register connected to the interface corresponding to the second port.

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