JP2000287230A - Crossbar switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain status information of a memory to which data are written without the need for each interface unit to newly increase output pins for the status information in the case of arranging crossbar switch in a matrix form. SOLUTION: In the case of transferring data from a port 1 to a port 8, an interface unit IU1 requiring to read contents of a status register T that is status information of a memory M being a transfer destination cannot directly read the status register T of the crossbar switch LSIX1-2. Then an interface unit IU8 reads the contents of the objective status register T and writes them to a status mirror register R connected to a cross point between a receiving path of the interface unit IU1 and a transmission path of the interface unit IU8. The interface unit IU1 reads the contents of the status mirror register R to obtain status information of the memory M of the transfer destination.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a crossbar switch, and more particularly to a crossbar switch used for switching a communication network.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram of a conventional crossbar switch. Referring to FIG. 8, a conventional crossbar switch includes one crossbar switch LSI X1, a memory M for storing transmission data inside the crossbar switch LSI, and whether or not the next data can be transmitted to this memory. Status register T and bidirectional input / output port 1
To IU4 and the crossbar switch LSI.

The details of the crossbar switch LSI X1 are as follows. A pair of transmission / reception paths provided corresponding to each of the interface units IU1 to IU4 are arranged so as to intersect at right angles to each other. Are provided with a memory M for storing transmission data, and a status register T is provided corresponding to each of these memories M. The status register T holds the state of the corresponding memory M.

A data transmission path through which the interface unit transmits data to the crossbar switch LSI and a data reception path through which the interface unit receives data from the crossbar switch LSI are both unidirectional transfer paths. At a point where the data transmission path and the data reception path cross each other, a memory M for storing transmission data and a status register T indicating status information of the memory are connected.

When data is transferred from one port to another port, the interface unit needs to read a status register T, which is status information of the memory M, in order to transfer data to the memory M corresponding to the transfer destination port. There is. In the configuration of FIG. 8, the crossbar switch LS
Since I is configured to read the information of the status register T from the data receiving path, the interface unit can obtain the status information of the memory M corresponding to the transfer destination port.

[0006]

Here, as shown in FIG. 9, the crossbar switch includes a plurality of crossbar switches LS.
In general, I is arranged in a matrix. In FIG. 9, for simplicity, four crossbar switch LSIs X1-1, X1-2, X2-1, and X2-2 are shown.
Is a 2 × 2 matrix arrangement as shown in the figure. In this case, bidirectional input / output ports 1 to 8 are provided, and these ports and transmission / reception paths of the crossbar switch LSI are connected to the interface units IU1 to IU8.
Is connected via the.

In such a configuration, the interface unit IU1 includes crossbar switches LSIX1-1 and XIX1-1.
Although it is necessary to read the status information in the crossbar switch LSIX1-2, the interface unit IU1 can read the status information in the crossbar switch LSIX1-2. It cannot be read. This is because the receiving path of the interface unit IU1 is a crossbar switch LSI.
This is because it is not connected to X1-2.

As described above, in the conventional configuration, when the crossbar switch LSIs are arranged in a matrix, each interface unit writes the data to the crossbar switch LSI.
There is a problem that all status information of the memory in the SI cannot be obtained.

As a method for solving this problem, each interface unit is composed of all crossbar switch LSIs.
The number of connection lines may be increased so that the memory status information can be read. However, increasing the number of connection lines is nothing less than increasing the number of pins of the crossbar switch LSI. However, since the crossbar switch LSI requires a very large number of input / output pins, such as 64 pins, only data pins per port, it is difficult to further increase the number of output pins.

An object of the present invention is to provide a crossbar switch which enables a matrix arrangement of crossbar switch LSIs without newly increasing the number of output pins for status information.

[0011]

According to the present invention, there are provided a plurality of bidirectional input / output ports, and an interface provided corresponding to the bidirectional input / output ports and serving as an interface between the corresponding ports and a pair of transmission / reception paths. A unit and a plurality of receiving paths arranged crossing each other with respect to each of the transmitting paths and connected to the bidirectional input / output port, and transmitting data from the transmitting path provided at each intersection of these transmitting / receiving paths. A data memory for storing the data and reading the stored data to the receiving path.
A plurality of crossbar switch LSIs provided corresponding to these data memories and having a status register indicating the state of the corresponding data memory are arranged in a matrix, and the corresponding transmission paths in the same row are commonly connected and each A crossbar switch including a matrix circuit in which corresponding reception paths are commonly connected to each other, characterized by including a status mirror register provided corresponding to the data memory and capable of storing information of the status register. A crossbar switch is obtained.

The status mirror register is accessible by the interface unit. When transferring data from a first port of the bidirectional input / output port to another second port, An interface unit corresponding to the second port reads status information of a memory connected to the interface unit corresponding to the first port from the status register, and reads the read information from an interface corresponding to the second port. Is written in the status mirror register connected to the. Further, the operation of the present invention is characterized in that the interface unit corresponding to the first port reads the contents of the status mirror register connected to the interface corresponding to the second port. The interface unit of the receiving port reads the status information of the memory from the status register, writes it in the status mirror register connected to the interface unit of the transmitting port, and reads the information of the status mirror register by the interface unit of the transmitting port. The status information of all memories of the crossbar switch LSI arranged in a matrix can be obtained without newly increasing the number of output pins.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of a crossbar switch according to an embodiment of the present invention, and portions equivalent to those in FIGS. The crossbar switch according to the present embodiment includes four crossbar switches LSIX1-1 and X1-.
2, X2-1, X2-2, and these crossbar switches L
A memory M for storing transmission data inside the SI, a status register T indicating whether the next data can be transmitted to the memory M, and a status mirror register R for temporarily storing information of a status register specified in advance; Interface units IU1 to IU8 for connecting the bidirectional input / output ports 1 to 8 and the crossbar switch LSI.

These four crossbar switch LSIs are 2
They are arranged in a × 2 matrix. A data transmission path in which the interface unit transmits data to the crossbar switch LSI, and a data reception path in which the interface unit receives data from the crossbar switch LSI,
Both are unidirectional transfer paths. At each of the points where the data transmission path and the data reception path intersect, a memory M for storing transmission data, a status register T indicating status information of the memory M, and an externally designated (specified from the interface unit) A) a status mirror register R for temporarily storing information of the status register;

Next, the operation of the present invention will be described in detail with reference to the drawings. FIG. 2 is an operation explanatory diagram of the embodiment shown in FIG. A case where data is transferred from port 1 to port 8 will be described with reference to FIG. When transferring data from the port 1 to the port 8, the interface unit IU1 needs to read the status register T1-8, which is the status information of the memory M1-8, to transfer the data to the memory M1-8. However, the interface unit IU1 cannot directly read the status register T1-8 of the crossbar switch LSI2.

Then, the interface unit IU8 reads the status register T1-8 and writes the information to the status mirror register R8-1. The information of the status register T1-8 is stored in the status mirror register R8.
-1 and the interface unit IU1 reads the status mirror register R8-1 so that the interface unit IU1 can obtain the status information of the memory M1-8.

Similarly, when transferring data from port 8 to port 1, interface unit IU8 needs to read status register T8-1 which is status information of memory M8-1 in order to transfer data to memory M8-1. There is. However, the interface unit IU8
Is the status register T8 of the crossbar switch LSI3
-1 cannot be read directly. Then, the interface unit IU1 reads the status register T8-1 and writes the information to the status mirror register R1-8. The information of the status register T8-1 is written into the status mirror register R1-8, and the interface unit IU8 reads the status mirror register R1-8, whereby the interface unit IU8 can obtain the status information of the memory M8-1. It is.

Here, the interface unit IU will be described with reference to FIGS. When transmitting data to the crossbar switch LSI, the interface unit IU divides the data received from the corresponding port into 64 bytes and transmits the data to the crossbar switch LSI in 64 byte units as shown in FIG. Status register information ST and status mirror register information SR are transmitted between 64-byte data. If there is no data to be transmitted, the status register information ST and the status mirror register information SR are repeatedly transmitted.

The status register information ST includes information indicating to which port the immediately following 64-byte data is to be transferred. Each constituent bit of the status register information ST represents a transfer port number, and the memory M corresponding to the transfer destination port of the bit whose value is “1”
To store 64 bytes of data.

When the interface unit IU receives data from the crossbar switch LSI, as shown in FIG. 4, it receives 64-byte data from the crossbar switch LSI and concatenates the divided 64-byte data to the original data size. And send it to the corresponding port. Status register information ST and status mirror register information SR are transmitted between 64-byte data. If there is no data to receive, the status register information S
T and status mirror register information SR are repeatedly received.

The status register information ST is information as to whether 64-byte data is stored in the memory M. Each constituent bit of the status register information ST indicates a transfer source port number, and the interface unit IU When the value "1" in the status register information ST is detected, the crossbar switch LSI is instructed to transmit 64-byte data to the memory M corresponding to the source port of the bit of the value "1".
64 bits of data will be received from the SI.

The interface unit IU that has received the status register information ST converts the received status register information ST into status mirror register information SR with the bit arrangement as it is, and transmits the status mirror register information SR to the crossbar switch LSI as status mirror register information SR. The status mirror register information SR received by the interface unit IU is information on whether data can be transmitted to each memory M in the crossbar switch LSI transmitted by the interface unit IU. That is, the total amount of data stored in the corresponding memory M can be determined by referring to the number of “1” of each configuration bit of the status mirror register information SR.

FIG. 5 is a view showing a second embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. FIG.
As shown in the figure, a configuration using a crossbar switch LSI corresponding to 2n ports is also possible. FIG. 6 is a view showing a third embodiment of the present invention, and the same parts as those in FIGS. As shown in FIG. 6, an m × n matrix configuration is also possible. Further, as in the fourth embodiment shown in FIG. 7, the crossbar switch LS using the bit slice method is used.
A configuration with I is also possible. The number of bits J to be sliced is
1, 2, 4, 8, and 16 bits are possible.

[0024]

As described above, according to the present invention, the interface unit that transmits data by temporarily storing the information of the status register in the status mirror register can obtain the status information of the transmission destination memory. Thus, there is an effect that the matrix arrangement of the crossbar switch LSI is enabled without increasing the number of output pins for status information.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a crossbar switch according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of the crossbar switch according to the first embodiment of the present invention.

FIG. 3 is a time chart of transmission data of the interface unit IU.

FIG. 4 is a time chart of reception data of the interface unit IU.

FIG. 5 is a configuration diagram illustrating a crossbar switch according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram illustrating a crossbar switch according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram illustrating a crossbar switch according to a fourth embodiment of the present invention.

FIG. 8 is a configuration diagram illustrating an example of a conventional crossbar switch.

FIG. 9 is a configuration diagram showing another example of a conventional crossbar switch.

[Explanation of symbols]

 1 to 8 ports IU1 to IU8 Interface unit M Memory R Status mirror register S Status register X1-1 to X2-2 Crossbar switch LSI

Claims (4)

[Claims] 1. A plurality of bidirectional input / output ports, an interface unit provided corresponding to these bidirectional input / output ports and serving as an interface between a corresponding port and a pair of transmission / reception paths, and each of the transmission paths A plurality of receiving paths connected to the bidirectional input / output port, respectively, and provided at each intersection of these transmitting / receiving paths to store transmission data from the transmission path and read the stored data to the reception path. A plurality of crossbar switch LSIs are provided in the form of a matrix, and are provided in correspondence with these data memories and have status registers indicating the states of the corresponding data memories. And a matrix circuit in which the corresponding reception paths in the same column are connected in common with each other. A crossbar switch including a status mirror register provided corresponding to a memory and capable of storing information of the status register. 2. The crossbar switch according to claim 1, wherein said status mirror register is accessible by said interface unit. 3. When data is transferred from a first port of the bidirectional input / output port to another second port, an interface unit corresponding to the second port is an interface unit corresponding to the first port. The status information of a memory connected to a unit is read from the status register, and the read information is written to a status mirror register connected to an interface corresponding to the second port. 2. The crossbar switch according to item 2. 4. An apparatus according to claim 3, wherein the interface unit corresponding to the first port reads the contents of a status mirror register connected to the interface corresponding to the second port. Crossbar switch.