IES980021A2 - System for the serial-to-parallel conversion of binary data - Google Patents

Abstract

A system for the serial-to-parallel conversion of binary data comprises a random access memory (RAM) 10 into which parallel data bits are written, and from which parallel data bits are read, with a word width of N bits, at least N-1 bit stores S0-S7 connected by an N-bit wide read/write data bus 14 to the RAM. In order to convert each N consecutive bits of a serial input data stream 16, an N-bit data word is repeatedly read from the RAM to the bit stores and written from the bit stores back to the RAM in synchronism with the serial input bits. Each time the word is read out and before it is written back, the then current serial input bit is substituted for a different one of the bits of word. Thus, after N such read/write operations the N-bit word written back to the RAM 10 corresponds to the N consecutive bits of the input data stream 16. The system may be modified to provide parallel-to-serial conversion (not shown) and multiplexed conversion of plural signal channels (Fig 4), e.g. for S-DIF audio signals,

Description

This invention relates to a system for the serial-to-parallel conversion of binary data.

Many systems make use of serial (one-bit-at-a-time) communications links. The serial data will normally need to be converted to parallel form so that it can be processed. This is normally done using a shift register, where each bit in the register is passed on to the next as a new bit is received. When a complete word has been received, the register outputs are accessed in parallel to yield the converted word.

Parallel to serial conversion is achieved using a shift register which is configured slightly differently; the input to each bit in the register is available in parallel, while the output of the first or last bit forms the serial output.

In some cases, there may be a large number of serial interfaces in a single machine e.g. multi-channel digital audio equipment and computer point-of-sale systems.

While shift registers perform the task very well, the storage density of typical shift register components is poor; usually 8 bits per device. A set of 32-bit shift registers will, therefore, normally require 4 devices. Sometimes, the shift register may need to be 'double buffered' to permit reception of a new serial word while the previous word remains available_:_-_Xhis-wiii—eften'double the device count.

INT CL IE 980021 The poor density of discrete shift registers may be partly overcome by using highly integrated serial interface components. These may have two full, double-buffered shift registers with all of the associated formatting logic to implement a particular serial interface type. This offers better density, but restricts the interface types to those implemented by the component manufacturers. i According to the present invention there is provided a system for the serial-to-parallel conversion of an input serial binary data stream, the system comprising a word-organised random access memory (RAM) with a word width of N bits, and a bit-modification means for the serial-to-parallel conversion of each N consecutive serial input bits of the data stream, the bit-modification means including means for repeatedly reading an N-bit data word from, and each time writing the word back to, the RAM in synchronism with the serial input bits, and means for substituting the then current serial input bit for a different one of the bits of the word each time the word is read out and before it is written back, whereby after N read/write operations the N-bit word written back to the RAM corresponds to the N consecutive bits of the input data stream.

The invention allows a versatile, high-density serial-toparallel converter to be implemented by making use of static RAM (SRAM) devices instead of shift registers. SRAM devices are widely available in very high bit densities, often over 130,000 bits per device. This is clearly far more storage than is normally required to implement a reasonable number of serial interface links.

IE 980021 Since SRAM devices are primarily intended for use in parallel applications such as microprocessor memory, there is no facility for writing or modifying an individual bit in a RAM word; all of the bits in a word must be written together.

This is overcome by the bit-modification means of the invention, which is able to retain a word read from RAM, modify a single bit and the result can be written back to the RAM. Although this seems inefficient in that it requires a full memory read and write cycle for every bit received, many serial interfaces operate at low speeds relative to the RAM cycle time, making it completely acceptable.

In fact, the cycle time of the RAM will often be so much shorter than the bit period of the serial interface, that several bit streams can be written to a single memory, as will be described.

In general, the advantages of the invention are that it provides much improved density over conventional serial-toparallel shift registers, and overcomes the need for double buffering which these conventional systems often need. The invention can be adapted to any interface type, thus allowing compatibility between different manufacturers systems; differing protocols can be easily handled in software after the words have been constructed in RAM.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a first embodiment of the invention; IE 980021 Fig. 2 is a block diagram of a bit-modification stage of the embodiment of Fig. 1; Fig. 3 is a logic diagram of a practical implementation of the bit-modification register of Fig. 1; Fig. 4 is a block diagram of a second embodiment of the invention; and Fig. 5 is a timing diagram of the operation of Fig.4.

Fig. 1 is a block diagram of an embodiment of the invention for the serial-to-parallel conversion of a single input serial binary data stream. The system comprises a static RAM 10 and a bit-modification register (BMR) 12. The RAM 10 is a word-organised RAM in which data bits are written into and read from the RAM in parallel with a word width of, in this case, eight bits. The BMR 12 comprises eight bitmodification stages So to S7. An 8-bit wide read/write data bus 14 connects the RAM 10 to the BMR 12; in particular, each bit line Bo to B7 of the data bus 14 is connected to a corresponding one of the bit-modification stages So to S7 respectively.

The serial input data stream is supplied on an input line 16 and consists of a series of binary digits (bits). The input line 16 is connected in parallel to each of the bitmodification stages So to S7, so that each serial bit arriving at the BMR 12 is simultaneously present at each bitmodification stage.

IE 980021 A bit counter 18 counts bit clock signals input on line 20.

The bit clock signals are timing signals derived from the input serial data bits in known manner. Thus each consecutive bit clock signal received by bit counter 18 indicates the arrival on the input line 16 of the next consecutive bit at the bit-modification stages So to S7. The bit counter 18 is a 3-bit counter which repeatedly cycles '1 through states 000 to 111 as the bit clock signals are received. The current state of the bit counter 18 is supplied in parallel to all the bit-modification stages So to S7 via a 3-bit wide clock bus 22.

The system also includes an address counter 32 which derives, from the bit clock signals on line 20, the address in the RAM 10 of a word to be read out from and written back into the RAM each time a bit is received on the input line 16, as will be described.

Referring to Fig. 2, each bit-modification stage Sn (0n of the data bus 14.

The input selector 26 connects either the bit line Bn or the serial data input line 16 to the input D of the bit store 24, IE 980021 as determined by the select logic 28. The latter decodes the signals on the clock bus 22 such that when the 3-bit combination representing the state of the bit counter 18 is equal to n, the select logic 28 outputs a signal to the input selector 26 to cause the latter to connect the input line 16 to the input D of the bit store 24, as seen in dashed lines in Fig. 2. When the 3-bit combination on the clock bus 22 is not equal to n, no 'output is provided by the select logic 28 and the input selector 26 connects the bit line Bn to the input D, as seen in solid line in Fig. 2.

The system works as follows. As consecutive serial input bits on input line 16 arrive at the BMR 12, the bit counter 18 changes state and repeatedly cycles through the values 000 to 111. This defines an 8-bit cycle period. Each set of eight consecutive input bits received serially on the input line 16 in each cycle period will be called bits b0 to b7.

In each cycle period, upon receipt of serial input bit b0 the select logic 28 in bit-modification stage So will output a signal to the input selector 26 of that stage, so that in bit-modification stage So the input line 16 is connected to the D input of the bit store 24. However, in all the other bit-modification stages Sx to S7 the respective bit line Bx to B7 is connected to the D input of the bit store 24.

Next, upon receipt by the RAM 10 of a read signal (not shown) derived from the bit clock signal 20, an 8-bit word is read in parallel from the RAM 10, from an address defined by the address counter 32, and its individual bits placed on the bit lines Bo to B7 respectively. Now, a storage clock signal 30 is supplied in parallel to all the bit stores 24, the storage IE 980021 clock signal also being derived from the bit clock signal 20. In response to the storage clock signal 30 the bit store 24 in the bit-modification stage So assumes the state of serial input bit b0, while the bit stores 24 in the bit-modification stages Sx to S7 assume the states of bits 1 to 7 respectively of the word read out of the RAM.

I Finally, upon receipt by the RAM 10 of a write signal (not shown) also derived from the bit clock signal 20, the 8-bit word stored in the bit stores 24 is written in parallel back into the RAM 10, via the bit lines Bo to B7, at the same address from which it was read. Thus, the word written back into the RAM 10 has as its first bit, bit 0, the same value as bit b0 of the input data in the current cycle period.

Essentially the same sequence of events occurs in respect of each subsequent serial input bit b0 to b7 in the cycle period, with the same 8-bit word being read to and from the same address in RAM 10 each time, except that a different select logic 28 is activated each time so that each consecutive serial input bit on line 16 within the cycle period substitutes for a different bit of the word read out of the RAM.

Thus, in general during the cycle period, upon receipt of serial input bit bn (0n will output a signal to the input selector 26 of that stage, so that in bit-modification stage Sn the input line 16 is connected to the D input of the bit store 24. In all the other bit-modification stages So to S(n.

IE 980021 X) and S(n+1) to $7 the respective bit line Bo to Β(η.υ and B{n+1, to B7 is connected to the D input of the bit store 24.

As before, the 8-bit word is then read in parallel from the RAM 10, from the address defined by the address counter 32, and a storage clock signal 30 is supplied in parallel to all the bit stores 24.- In response to the storage clock signal » the bit store 24 in the bit-modification stage Sn assumes the state of serial input bit bn, while the bit stores 24 in the bit-modification stages So to S(n.1) and S(n+1) to S7 assume the states of bits 1 to (n-1) and (n+1) to 7 respectively of the word read out of the RAM.

Finally, the 8-bit word stored in the bit stores 24 is written in parallel back into the RAM 10, via the bit lines Bo to B7, at the same address from which it was read. Thus, the word written back into the RAM 10 has as its nth bit, bit n, the same value as bit bn of the serial input data in the current cycle period.

Accordingly, the 8-bit data word repeatedly read from and written to the RAM 10 during the cycle period will have been progressively modified, a bit at a time, so that after it has been read from and written back into the RAM 10 eight times, i.e. at the end of the cycle period, it corresponds to the 8 consecutive bits b0 to b7 of the serial input data stream received at the BMR 12 during that cycle period.

The above sequence now repeats for each successive 8-bit cycle period of the serial input data on input line 16, so that each series of 8 consecutive bits is converted to a respective parallel 8-bit word in the RAM io. Although IE 980021 during any given cycle period the 8-bit word is repeatedly read from and written back into the RAM at the same address, during different cycle periods the word is preferably read from and written into different addresses in the RAM. This will enable a plurality of 8-bit parallel words to be built up in the RAM corresponding to successive 8-bit cycle periods of the serial input data.

Since all key timing signals for the system, e.g. RAM read and write signals, clock bus signals 22, RAM address signals and storage clock signals 30, are derived from the bit clock signals 20, proper synchronism of the operation of the system with the serial input bits on line 16 is ensured.

The parallel converted data may be read out of the RAM using read cycles interleaved with the serial to parallel process write cycles described above. Alternatively, a dual port RAM could be used, where one port is used for serial to parallel accesses as described above and the other is used to access the completed parallel words.

In the foregoing embodiment, each bit-modification stage includes an input selector 26 at the input of each bit store 24 for selecting, for storage in the bit store, either a respective bit of the word read out from the RAM or, where such bit is to be substituted by a bit from the input data stream, the bit from the input data stream. Thus, although eight bits are read out of the RAM, only seven are stored in the bit stores, and the eighth is substituted in the relevant bit store by the current input bit on line 16.

IE 980021 However, it is clearly alternatively possible for each bitmodification stage to have the selector means 26 located at the output of each bit store 24 with one input connecetd to the Q output of the bit store and the other input connected to the bit line Bn. According to the output of the selector logic 28, the selector means 26 would select for storage in the RAM either the .bit stored in the bit store 24 or, where such bit is to be substituted by a bit from the input data stream, the bit from the input data stream. In this case all eight bits of the data word would be read out of the RAM and stored in the bit stores 24 each time, but only seven would be written back into the RAM with the eighth being directly substituted by the relevant bit of the input the data stream.

Fig. 3 is a logic diagram of a practical implementation of the bit-modification register BMR 12 of Fig. 1. In Fig. 3 only the first two bit-modification stages So and Sx, and the last bit-modification stage S7, are shown. However, all eight bit-modification stages Sx to S7 are the same, except for the connections at the inputs to the AND-gates 40, as will be described.

Each stage Sx to S7 includes a respective 3-input AND-gate 40, and the three bit lines of the clock bus 22 are connected respectively to the three inputs of this AND-gate. Each ANDgate 40 has a different combination of inverting and noninverting inputs, such that for any combination of the bit values 000 to 111 on the clock bus 22 one and only one of the AND-gates 40 will have a logic high output. For example, all three inputs of the AND-gate 40 in stage S7 are inverted, so the output of this AND-gate will go high when the clock bus bit combination is 000. On the other hand, only two of the IE 980021 three inputs of the AND-gate 40 in stage S2 are inverted, so the output of this AND-gate will go high when the clock bus bit combination is 001.

In general, the output of the AND-gate 40 of stage Sn will go high when the decimal equivalent of the combination of bit values on the clock bus 22 is n. Thus, the AND-gates 40 implement the select logic 28 of Fig. 2.

Each stage Sx to S7 further includes two 2-input AND-gates 42, 44 and a 2-input OR-gate 46. The AND-gate 42 has a noninverting input connected to the bit line Bn and an inverting input connected to the output of the AND-gate 40. The ANDgate 44 has a non-inverting input connected to the serial input line 16 and a non-inverting input connected to the output of the AND-gate 40. The inputs of the OR-gate 46 are connected respectively to the outputs of the AND-gates 42 and 44, while the output of the OR-gate is connected to the D input of the bit store 24.

It will be evident that when the output of the AND-gate 40 in any given stage Sn is high, the AND-gate 44 connects the serial input line 16 to the D input of the corresponding bit store 24 via the OR-gate 46. Correspondingly, when the output of the AND-gate 40 in the stage Sn is low, the ANDgate 44 connects the bit line Bn to the D input of the bit store 24 via the OR-gate 46. Thus in each stage Sx to S7 the two 2-input AND-gates 42, 44 and the 2-input OR-gate 46 collectively implement the input selector 26 of Fig. 2.

Each stage Sx to S7 further includes an output amplifier 48 at the Q output of the bit store 24. An output enable signal is IE 980021 provided on line 50 shortly after the storage clock signal on line 30, to ensure that the contents of the bit stores are stabilised before their contents are read.

Fig. 4 is a block diagram of an embodiment of the invention for the serial-to-parallel conversion of a plurality of, in this embodiment, eight input serial binary data streams ί received on input lines 160 to 167 respectively. The main difference from Figs. 1 and 2 is the addition of an input selector 60 to which the eight input lines 160 to 167 are connected in parallel. In this embodiment it is assumed that the input data streams are synchronised, i.e. consecutive bits arrive at the input selector 60 at the same time on each of the input lines 160 to 167.

Essentially what happens is that during each input bit period, i.e. the period of time, Fig. 5(a), during which respective bits on each of the input lines 160 to 167 are simultaneously present at the respective inputs of the input selector 60, the latter passes each input bit in turn to the BMR 12 on line 62, as shown in Fig. 5(b). Like line 16 in Fig. 1, the line 62 is connected in parallel to all the bitmodification stages So to S7 of BMR 12.

Each time an input bit is received by the BMR 12 a word is read from the RAM 10, modified as described previously, and then written back into the RAM, as shown in Fig. 5(c) . However, a different word is read out and written back in respect of each different input line 160 to 167.

Consider a cycle of eight input bit periods during which eight consecutive serial input bits b0 to b7 are received in IE 980021 synchronism on each line 160 to 167. During the first input bit period, eight input bits b0 are simultaneously present at the input selector 60, and the latter passes these in turn to the BMR 12. The input selector 60 is driven by a 3-bit input counter 64 which cycles through the values 000 to 111 to select each line 160 to 167 in turn for connection to the BMR 12, the input selector 60 having decoders similar to the ANDgates 40 of Fig. 3 'to determine which input line is to be connected at any given time. The input counter 64 is driven by clock pulses which are derived from, but have eight times the frequency of, the bit clock signals 20.

When the input bit b0 from line 160 is received by the BMR 12, a given word Wo is read out of the RAM 10 from an address defined by the address counter 32, the input bit b0 is substituted for bit 0 of word Wo in the manner previously described, and the word Wo is written back into the RAM at the same address from which it was read.

Next, when the input bit b0 from line 16x is received by the BMR 12, a different word Wx is read out of the RAM 10 from a different address defined by the address counter 32, the input bit b0 is substituted for bit 0 of word Wx, and the word W-l is written back into the RAM at the same address from which it was read.

This continues until all eight input bits b0 have been processed in turn, after which there will be eight words Wo to W7 in the RAM 10 in each of which the first bit, bit 0, will correspond to bit b0 of a respective input line 160 to · IE 980021 During the next input bit period, eight input bits bx are simultaneously present at the input selector 60, and the latter passes these in turn to the BMR 12. When the input bit bx from line 160 is received by the BMR 12, the word Wo is again read out of the RAM 10, the input bit bx is substituted for bit 1 of word Wo, and the word Wo is written back into the RAM at the same address from which it was read. ί Next, when the input bit bx from line 16! is received by the BMR 12, the word Wx is read out of the RAM 10, the input bit bx is substituted for bit 1 of word WL, and the word Wx is written back into the RAM at the same address from which it was read.

This continues until all eight input bits bx have been processed in turn, after which the eight words Wo to W7 in the RAM 10 will have their first bit, bit 0, corresponding to bit b0 of a respective input line 160 to 167 and their second bit, bit 1, corresponding to bit bx of a respective input line 160 to 167.

The same process occurs successively in respect of input bits b2 to b7 on each input line 160 to 167, so that at the end of the cycle of eight input bit periods each of the eight words Wo to W7 has its bits 0 to 7 corresponding to bits bQ to b7 of the respective input data stream on input lines 160 to 167. Thus, at the end of the cycle of eight input bit periods, eight consecutive serial input bits b0 to b7 of each of the input data streams on lines 160 to 167 have been converted to respective parallel words Wo to W7.

IE 980021 Finally, the entire process described above repeats for successive cycles of eight input bit periods.

The operation of Fig. 4, as described above, has assumed that the input streams on lines 160 to 167 will be synchronous.

If they are not, however, it is relatively straightforward to pre-process the inputs so that they are essentially synchronous as described above. The important point is that all the inputs must have the same, or substantially similar, bit cycle times.

The versatility of the present invention is demonstrated in the case of the S-DIF serial digital audio interface which transmits a 32-bit word approximately every 20uS, giving a bit period of 62SnS. Using SRAM with a read/write cycle time of 50nS, up to 12 S-DIF inputs could be handled. Because SDIF interfaces carry a single channel of audio per data stream, multi-channel audio equipment, such as multi-track tape recorders, will have a number of S-DIF links. The ability to implement several of these links with a single, compact block of circuitry is a distinct advantage.

As well as providing multiple interfaces, the present invention also allows for arbitrary word lengths in the serial input data stream. As mentioned above, the capacity of memory devices is very large, so long serial words which exceed the parallel word size of the memory are catered for by using multiple memory addresses to store the complete word.

For example, in the S-DIF example above, the 32-bit words from each of the twelve interfaces could be stored as 4 IE 980021 addresses each of 8 bits. The total storage requirement would be 4x12=48 bytes (8 bit words), which is a small fraction of available SRAM capacity.

The bit-modification register can be implemented using low density programmable logic devices which are fast and costeffective. The register can be readily configured to accomodate serial interfaces which are sent least-significant bit first or most-significant bit first. Also, individual bits which are not required can be discarded very simply, making preamble removal trivial.

A variation of the bit-modification register described can perform the bit-selection operation for parallel-to serial conversion. These two operations can be performed using a single memory, so the 12 interfaces mentioned above could be implemented as 6 receive links and 6 transmit links.

In most audio applications, one deals with some device which has 8, say, serial output streams which need to be processed appropriately. The results of this processing will then need to be passed on as a further 8 serial output streams. One can therefore use a system as described above with 16 ports on the input bus, 8 used for input and 8 used for output. A single BMR can be used to provide serial-to-parallel and parallel-to-serial conversions. The bit clock on the input bus can be set to ensure an output follows an input or all the outputs are done after all the inputs. Using such a setup clearly has an advantage in terms of density, and also ensures synchronous output.

IE 980021 The bit stores need not necessarily consist of logic devices,a bank of capacitors could be used to retain the data values read from RAM. In this case, the selection mechanism would overwrite the stored charge by charging or discharging the selected capacitance. The resutling charge values could then be written back to RAM.

Since only one of e'ight bits of the 8-bit word read from the RAM 10 is substituted each time, and the other seven bits are written back to the RAM unaltered, an alternative embodiment (not shown) is possible in which the BMR 12 has only seven bit modification stages. Each time the word is read out of the RAM these seven stages store the seven bits of the word which are to be unaltered, and the eighth bit of the word, i.e. the bit to be substituted, is taken directly from the serial input line when the word is read back to the RAM. In such embodiment there will need to be a switching network between the bit-modification stages of the BMR 12 and the bit lines Bo to B7, to ensure that each time the substitute bit is placed on the correct bit line.

Also, of course, the invention is not limited to a RAM organised on an 8-bit word basis. In general, if the RAM 10 has a word width of N bits, the BMR 12 will have N bitmodification stages, or (N-1) bit-modification stages in the case of the alternative embodiment referred to in the preceding paragraph.

Claims (5)

1. A system for the serial-to-parallel conversion of an input serial binary data stream, the system comprising a word-organised random access memory (RAM) with a word width of N bits, and a bit-modification means for the serial-toparallel conversion of each N consecutive serial input bits of the data stream, the bit-modification means including means for repeatedly reading an N-bit data word from, and each time writing the word back to, the RAM in synchronism with the serial input bits, and means for substituting the then current serial input bit for a different one of the bits of the word each time the word is read out and before it is written back, whereby after N read/write operations the N-bit word written back to the RAM corresponds to the N consecutive bits of the input data stream.

2. A system as claimed in claim 1, wherein the bitmodification means has at least (N-l) bit stores for storing respective data bits of an N-bit word received in parallel from the RAM and for providing respective data bits stored therein in parallel to the RAM, the bit modification means preferably having N bit stores.

3. A system as claimed in claim 2, wherein the bitmodification means includes: (i) selection means at the input of each bit store for selecting for storage in the bit store either a respective bit of the word read out from the RAM or, where such bit is to be substituted by a bit from the input data stream, the bit from the input data stream; or (ii) selection means at the output of each bit store for selecting for storage in the RAM either the bit stored in IE 980021 i 1 the bit store or, where such bit is to be substituted by a bit from the input data stream, the bit from the input data stream.

4. A system as claimed in any preceding claim for the serial-to-parallel conversion of a plurality M of serial binary data streams, wherein M different data words, each corresponding to a different input data stream, are cyclically read out of and written into the RAM, and each time a word is read out and before it is written back, a respective bit of the word is substituted by a respective bit of the corresponding data stream.

5. A method for the serial-to-parallel conversion of an input serial binary data stream, the method comprising providing a word-organised random access memory (RAM) with a word width of N bits, and serial-to-parallel converting each N consecutive serial input bits of the data stream by repeatedly reading an N-bit data word from, and each time writing the word back to, the RAM in synchronism with the serial input bits, and sustituting the then current serial input bit for a different one of the bits of the word each time the word is read out and before it is written back, whereby after N read/write operations the N-bit word written back to the RAM corresponds to the N consecutive bits of the input data stream.