JPH0561827B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a serial data transmitting device that converts parallel data of a predetermined number of bits into serial data and transmits the serial data.

[Prior art and its problems]

FIG. 1 is a block diagram showing a conventional data transmitting device, and FIG. 2 is a timing waveform diagram for explaining the operation of FIG. 1. In FIG. 1, 1 is an oscillation circuit, 2 is a frequency dividing circuit, 3 is a counter, 4 is a data processing section, 5 is a buffer register, 6 is a shift register, and 7 is a buffer amplifier.

The clock pulse from the oscillation circuit 1 is used as a system clock signal for the data processing section 4, and is divided by the frequency dividing circuit 2 to the processing frequency.
Used as a transmission clock for transmitting data. Note that this transmission clock is shown, for example, as shown in FIG. 2A. On the other hand, as shown in FIG. 2B, parallel data to be transmitted is written to the buffer register 5 from the data processing section 4 together with the signal WT. The contents of this buffer register 5 are further given to the shift register 6, so the shift register 6 shifts this data one bit at a time using the transmission clock, converts it into serial data as shown in Figure 2C, and sends it out. do. The transmission clock signal obtained from the frequency dividing circuit 2 is counted by, for example, an octal counter 3, so when eight transmission clocks are counted, the counter 3 outputs a carry signal. This signal is applied to the data processing unit 4 as a transfer completion signal BFE (see FIG. 2D) indicating that 8-bit serial data has been sent out, and is subjected to interrupt processing. That is, when this interrupt is raised, the data processing section 4 writes the next transmission data into the buffer register 5, thereby maintaining the continuity of the serial data. Note that the data processing section performs operations such as creating a synchronization pattern for data to be transmitted or editing a transmission word. Also,
Since a microprocessor can be used for the data processing section, the data structure is 8 as shown in Figure 1.
It is preferable to transmit in units of bits or 16 bits, but the number is not necessarily limited to this.

However, if such a device handles data for n multiple lines (stations, channels), buffer registers and shift registers or frequency divider circuits for n lines will be required, and accordingly, the port address of the buffer register will also be for n lines. The disadvantage is that the hardware is complicated and bulky. Furthermore, since the interrupt signal notifying the completion of transfer will also rise by the amount of n lines, the occupancy rate of the data processing section will increase, resulting in a drawback that the processing capacity will decrease by that amount.

[Purpose of the invention]

This invention was made in view of these points,
Serial data that can be handled at high speed with the same hardware, even if multiple lines, synchronization methods (start-stop synchronization, frame synchronization, etc.), transmission formats, or transmission speeds are different. The purpose of this invention is to provide a transmitting device.

[Key points of the invention]

The key point is that a transmission file is provided corresponding to each of multiple channels and stores a predetermined number of transmission data, bit by bit, corresponding to its address, and the data from each file is stored bit by bit in parallel, and the system data processing means for reading each bit successively by the maximum transmission speed of the channel divided by the transmission speed of the corresponding channel, and editing the bits or creating a synchronization pattern; First-in/first-out memory (FIFO) stores data bit by bit in parallel and outputs it in that order.
(memory), and the contents of the FIFO memory are read out using a signal corresponding to the maximum transmission speed.

[Embodiments of the invention]

FIG. 3 is a configuration diagram showing an embodiment of this invention, and FIG.
The figure is a timing waveform diagram for explaining the operation of FIG. 3. In FIG. 3, 11 to 18 are random access memories (RAM) for editing and storing transmission data for each channel CH1 to CH8 in the data processing section 4, and 19 is a first-in, first-out type memory (first-in, first-out type memory). It is a first-out memory (FIFO memory) and is otherwise the same as that shown in FIG.

Memories 11 to 18 contain each channel CH1 to
As shown in the figure, the data to be sent out through CH8 is in one vertical column, and in memory 11 it is in bit position "7" and in memory 18 it is in bit position "0".
They are stored with different bit positions, such as , and "0" is written in unused bit positions in each memory.
Therefore, when the same address in each memory 11 to 18 is specified sequentially, the addresses shown in FIG.
The data is read out one bit at a time according to the number of channels, such as a channel, and it can be said that each data has already been serially converted in the order of its address. Furthermore, in this case, since the transmission speeds of each channel are different from each other, the data reading mode is made to differ accordingly. For example, if the transmission speed of the channel corresponding to memory 11 is twice that of memory 12, data at a different address is read each time from memory 11, whereas data from one address is read from memory 12. It will be read twice. Therefore, in this system, the highest transmission rate (for example, 1200 baud) is used as a reference, and the highest transmission rate is referred to once per address, and the 1/n is referred to per address n times. By doing so, this difference in transmission speed can be dealt with. By doing this, the data processing section 4 simply specifies the addresses of each of the memories 11 to 18 in sequence, and data corresponding to the speed is read out via the internal OR gate.
Along with the write signal WT, the FIFO is
It can be written to memory 19. Data of each channel is retrieved from the FIFO memory 19 in the order in which it was written by applying a transmission clock (adjusted to the maximum transmission speed of the system) obtained via the frequency dividing circuit 2. , each channel CH1~CH via buffer amplifier 7
It can be divided into 8 parts. At this time, when eight transmission clocks are counted, the transfer completion signal BFE is output from the frequency divider circuit or counter 3 (see Figure 4B), so the data processing unit 4 waits for a predetermined period of time as shown in Figure 4C. After executing interrupt processing,
By repeating the operation of reading data from each memory 11 to 18 as described above, predetermined data is sent out for each channel. In other words, this example:
By using FIFO memory to synchronize the system clock of the data processing section (see Figure 4 A) and the transmission clock (see Figure 2 A), data for 8 lines can be processed with the same hardware. It can be said that it has been made possible. Furthermore, if the data processing unit rewrites the memories 11 to 18 for each interrupt, the transmission speed will be the highest (for example, 1200 baud), and if it is rewritten every 2 or 6 times, the transmission speed will be half that (for example, 1200 baud). 600 baud) and 1/6 (200 baud), which has the advantage that the transmission speed of each line can be set to a desired value. Note that _t1 in Fig. 4 is the interrupt processing time of the data processing section, and _t2 is the time required to write data on each line one bit at a time.Therefore, in order to write 8-bit data, The required time T is T=t ₁ +8t ₂ .

In addition, the system clock of the data processing section is set to 3M.
Hz, and the maximum transmission speed is 1200 baud, the length of 1 bit at 1200 baud is 1/1200 = 0.833 mS, and with 8 bit length, it is 0.833 x 6 = 6.67 mS, so the data is sent to the data processing unit every 6.67 baud. Since the interrupt will be raised, if the time for the data processing section to write the next 8 bits of data is 100 μS, the occupancy rate in this case will be 100 (μS) ÷ 6.67 (mS) ≒ 1.5%. , the time required for data processing is of little concern.

〔Effect of the invention〕

According to this invention, by using FIFO memory to synchronize the system clock of the data processing section and the transmission clock, not only can multiple lines be processed with the same hardware, but also By using it in combination with a data processing section, it has the advantage of being able to handle differences in transmission methods.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional serial data transmitter, FIG. 2 is a timing waveform diagram for explaining the operation of FIG. 1, FIG. 3 is a configuration diagram showing an embodiment of the present invention, and FIG. 4 3 is a timing waveform diagram for explaining the operation of FIG. 3. FIG. Explanation of symbols, 1... Oscillation circuit, 2... Frequency dividing circuit,
3... Counter, 4... Data processing section, 5... Buffer register, 6... Shift register, 7...
Buffer amplifier, 11-18...Transmission file (memory), 19...First-in/first-out memory (FIFO memory).

Claims (1)

[Claims] 1 A transmission file that is provided corresponding to each of multiple channels and stores a predetermined number of transmission data bit by bit in correspondence with its address, and a transmission file that stores data from each file one bit at a time in parallel and at the highest transmission rate of the system. A data processing means for successively reading out each bit by the number of bits divided by the transmission speed of the corresponding channel and editing or creating a synchronization pattern, and data corresponding to each channel provided through the processing means. It is equipped with a first-in/first-out memory (FIFO memory) that stores bits in parallel and outputs them in order.By reading the contents of the FIFO memory with a signal corresponding to the maximum transmission speed, each A serial data transmitting device characterized by serially transmitting transmission data for each channel.