JPH046138B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a reception buffer circuit provided in one station that receives burst data transmitted by N stations using different carrier waves in parallel in a one-to-N communication system. In particular, the present invention relates to a reception buffer circuit having a function of inputting in parallel burst data transmitted by N stations with a cyclic check code added in burst units and determining whether the burst data is correct or incorrect.

(Prior art) For example, in a time division multiple access satellite communication system, one station (master station) to many stations (slave stations) communicate via a satellite.
When performing communication between carriers, there is a limit to the number of lines that can be handled by one carrier wave, so if the number of lines is large, multiple carrier waves will be used. That is, the master station receives multiple carrier waves in parallel at once.

In addition, in this type of satellite communication system, the slave station on the transmitting side adds a cycle check code to the burst data and transmits it, and the master station that receives the burst data at once determines whether the burst data is correct or incorrect. This determination of authenticity is performed by a reception buffer circuit.

As such a receiving buffer circuit, for example, the one shown in FIG. 4 is known. This reception buffer circuit consists of N cyclic check circuits 4
, a parallel-to-serial conversion circuit 1 , a memory circuit 2 , and an address generation circuit 9 .

The N cyclic check circuits 4 are provided in one-to-one correspondence with the carrier waves (N series) to be received. The burst data of each carrier wave is input to the parallel-to-serial conversion circuit 1 while undergoing a cyclic check in the corresponding cyclic check circuit 4.

The parallel-to-serial conversion circuit 1 time-series multiplexes N series of burst data inputted in parallel in bit units.
It is sent to the memory circuit 2.

The memory circuit 2 receives address signals of the write address and the read address from the address generation circuit 9, stores the output of the parallel-to-serial conversion circuit 1, and sends it out as output data.

The address generation circuit 9 initializes the write address to the memory circuit 2 in response to a burst start signal generated in synchronization with the input of the N series of burst data, and updates and outputs the write address in response to a write clock signal. Then, the output signal of the parallel-to-serial conversion circuit 1 is sequentially stored in a predetermined storage area of the storage circuit 2. Next, the storage circuit 2 which is a receiving buffer
The read address is updated and outputted to the memory circuit 2 in response to a read clock signal inputted to read the burst data stored in the memory circuit 2.

(Problems to be Solved by the Invention) In the conventional receiving buffer circuit described above, the number of cyclic check circuits equal to the number of carrier waves is required. As the number of carrier waves increases and the number of carrier waves increases, the circuit scale increases, which poses the problem of hindering miniaturization and power reduction of the device.

The present invention was developed in view of these conventional problems, and can easily cope with an increase in parallel inputs without increasing the circuit scale, thereby reducing the size of the device.
The purpose of the present invention is to provide a reception buffer circuit that can contribute to lower power consumption.

(Means for Solving the Problems) In order to achieve the above object, the reception buffer circuit of the present invention has the following configuration.

That is, the reception buffer circuit of the present invention comprises: a parallel-to-serial conversion circuit that time-series multiplexes burst data consisting of a predetermined number of bits of a plurality of series input in parallel; a storage circuit; and an output of the parallel-to-serial conversion circuit. an address generation circuit that generates a write address for storing a signal in the storage circuit and a read address for reading out the base data from the storage circuit in time series; a cyclic check for the output signal of the storage circuit; The present invention is characterized by comprising a cyclic check circuit that performs;

(Operation) Next, the operation of the reception buffer circuit of the present invention configured as described above will be explained.

Multiple series of burst data input in parallel are
A parallel-to-serial conversion circuit multiplexes the data bit by bit in time series and inputs it to the storage circuit. The storage circuit receives the write address from the address generation circuit and stores the output of the parallel-to-serial conversion circuit, and also receives the read address and converts the stored multiplexed data by time-series multiplexing in units of bits into the burst data format. output in chronological order. As a result, the cyclic check circuit can perform the required cyclic check on each burst data input sequentially.

As explained above, according to the receive buffer circuit of the present invention, even if the number of parallel inputs increases, one cyclic check circuit can perform cyclic checks on all inputs, so the circuit size does not increase. It can be easily applied without any problems, and has the effect of contributing to the miniaturization of equipment and lower power consumption.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a configuration block diagram of a receiving buffer circuit according to an embodiment of the present invention, and FIG. 2 is an operation timing diagram of each part.

This reception buffer circuit consists of a parallel-to-serial conversion circuit 1
, a memory circuit 2 , an address generation circuit 3 , and a cycle check circuit 4 .

The parallel-to-serial conversion circuit 1 time-series multiplexes burst data consisting of a predetermined number of bits of a plurality of series input in parallel in units of bits based on a high-speed clock signal, and outputs the multiplexed data to a storage circuit 2.

In this example, in order to simplify the explanation, the number of carrier waves input in parallel is assumed to be 2, and the burst data carried by carrier wave 1 is composed of 4 bits A0 to A3 (Fig. 2 a1). The burst data carried by carrier wave 2 has a 4-bit structure of B0 to B3 (FIG. 2 a2). Therefore, this parallel-to-serial conversion circuit 1
will send serial data b of "A0, B0, A1, B1, A2, B2, A3, B3" to the storage circuit 2 (FIG. 2b).

The address generation circuit 3 is configured, for example, as shown in FIG. 3 (details will be described later), and stores the serial data b in the storage circuit 2 upon receiving a burst start signal (FIG. 2c) and a high-speed clock signal. In response to the address signal (write address) for reading and the read clock signal, each address signal f of the read address for reading burst data from the memory circuit 2 in time series (FIG. 2 d) is generated and stored. Send to circuit 2.

The cyclic check circuit 4 receives the output signal d (FIG. 2 d) from the memory circuit 2 and sequentially performs a cyclic check on the sequentially input burst data "A0 to A3" and "B0 to B3". It is output as output data e (Fig. 2 e).

Next, a specific example of the address generation circuit 3 will be explained with reference to FIG.

The address generation circuit 3 includes two selection circuits 11,
12, two counter circuits 13, 14,
It is composed of an R-S flip-flop circuit 15.

The first counter circuit 13 is a counter circuit that counts two from "0" to "1" and outputs the upper bit of the address signal f, and performs counting based on the output signal from the first selection circuit 11.

The second counter circuit 14 is a counter circuit that counts four times from "0" to "3" and outputs the lower bit of the address signal f, and performs counting based on the output signal from the second selection circuit 12. Both counter circuits are flywheel type counter circuits in which a carry signal is output when a full count is reached, and the count value returns to "0".

When the output signal of the R-S flip-flop circuit 15 is "1", the first selection circuit 11 directly outputs a high-speed clock signal with twice the frequency synchronized with the received burst data, and when the output signal is "0", the A carry signal of the second counter circuit 14 is output.

The second selection circuit 12 outputs a carry signal of the first counter circuit 13 when the output signal of the R-S flip-flop circuit 15 is "1", and outputs a read clock signal when it is "0". .

The R-S flip-flop circuit 15 outputs "1" when a burst start signal indicating the head position of the received burst data is input, and outputs "0" when a carry signal from the second counter circuit 14 is input.

First of all, for each circuit that operates as described above, see Figure 2c.
When the burst start signal shown in is input, the first and second counter circuits 13 and 14 output "0", that is, the address signal f is initialized and the R-S
The output of each flip-flop circuit 15 is set to "1". As a result, the first selection circuit 11
outputs a high-speed clock signal to the first counter circuit 13, and the second selection circuit 12 outputs the carry signal of the second counter circuit 13 to the second counter circuit 14. The first counter circuit 13 receives the high-speed clock signal and counts from "0" to "1" while counting the high-order bit "0" of the address signal f.
Output “1” sequentially. Every time the count ends, a carry signal is output to the second counter circuit 14 via the second selection circuit 12 and returns to "0". Each time, the second counter circuit 14 counts up by one, and the lower bit of the address signal f is output.

When the second counter circuit 14 counts four to "3", it changes the count value to "0" and outputs a carry signal. Then, this carry signal causes the R-S flip-flop circuit 15 to output "0", so the first selection circuit 11 stops outputting the high-speed clock signal. In other words, the write address signal ends. At this time, the first and second counter circuits 13 and 14 set their count values to "0".

The write address signal formed in this way is as shown in FIG.
Bit B0 goes to address 0, bit A1 goes to address 01,
Bit B1 goes to address 11, Bit A2 goes to address 02, Bit B2 goes to address 12, Bit A3 goes to address 13, Bit B3 goes to address 13.
will be stored respectively.

In this state, the R-S flip-flop circuit 1
5 sets the output to "0", the first selection circuit 11 outputs the output of the second counter circuit 14 (i.e.,
carry signal), and the second selection circuit 12 selects the read clock signal. Therefore, when the read clock signal is input after the serial data b is stored in the memory circuit 2, the second counter circuit 1
4 operates before the first counter circuit 13,
When it counts from "0" to "3", it outputs a carry signal and returns to "0". As a result, memory circuit 2
As shown in Figure 2f, 00,01,02,
Each address of 03 is accessed in turn, A0,
Each bit of A1, A2, and A3 will be output in sequence. That is, burst data of carrier wave 1 is output.

Next, when the second counter circuit 14 outputs a carry signal, the first counter circuit 13 counts up by one, so in that state, the second counter circuit 14 counts up four from "0" to "3". I do. As a result, in the memory circuit 2, addresses 10, 11, 12, and 13 are sequentially accessed as shown in FIG. 2f, and each bit of B0, B1, B2, and B3 is sequentially output.

That is, burst data of carrier wave 2 is output.

When the second counter circuit 14 counts up, it returns to "0" and outputs a carry signal to the first counter circuit 13, so the first counter circuit 13 counts up and returns to "0".

In other words, the read address signal ends.

In this embodiment, the case where the number N of parallel inputs is "2" has been described, but it goes without saying that the same idea can be applied even when N becomes larger.

(Effects of the Invention) As explained above, according to the receiving buffer circuit of the present invention, even if the number of parallel inputs increases, a single cyclic check circuit can perform a cyclic check on all inputs. This can be easily handled without increasing the circuit scale, and has the effect of contributing to device miniaturization and lower power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of a receiving buffer circuit according to an embodiment of the present invention, FIG. 2 is an operation timing diagram of each part, FIG. 3 is a block diagram of a specific example of the configuration of an address generation circuit, and FIG. 1 is a configuration block diagram of a conventional reception buffer circuit. 1...Parallel-serial conversion circuit, 2...Storage circuit, 3,
9... Address generation circuit, 4... Cyclic check circuit, 11, 12... Selection circuit, 13, 1
4... Counter circuit, 15... R-S flip-flop circuit.

Claims (1)

[Claims] 1. A parallel-to-serial conversion circuit for time-series multiplexing of burst data consisting of a predetermined number of bits of multiple series input in parallel in bit units; and a storage circuit; for storing the output signal of the parallel-to-serial conversion circuit in the storage circuit. an address generation circuit that generates a write address of the memory circuit and a read address for reading the base data from the memory circuit in time series; a cyclic check circuit that performs a cycle check of the output signal of the memory circuit; A reception buffer circuit characterized by comprising: