JPS6242698A - Circuit setting circuit - Google Patents

Abstract

PURPOSE:To halve the number of data memory chips and to simplify peripheral circuits by setting the capacity of a data memory to one frame. CONSTITUTION:Input data in one period is set to four bits. The time width of each bit comprising the input data is bisected. The first half of the divided width is used for writing data in the data memory, while the latter half is used for reading data out of the data memory. At this time addresses of data writing and data reading are inverted by one period. The capacity of the data memory is set to eight bits, and during some one period data is written and read out in the first half bits and the latter half bits of the data memory, respectively. during the next one period, conversely, data is read out and written in the first half bits and the latter half bits, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a line setting method for a digital circuit network, and particularly to a line setting method that reduces the circuit scale by approximately half and contributes to miniaturization and economicalization of equipment. It is.

(Prior art) Instead of the spatial line setting at the distribution rack, which was carried out in the conventional analog network, in the digital synchronous network, the circuit setting is carried out temporally by exchanging time slots at the synchronous multiplexing level. The technology that shows the circuit setting method in such a digital network is Facility, 33C11] (1980-11-15).
) Telecommunications Association, Nakahama, Sasahira 2 Kunieda P, 95-1
06, Research practical application report, (113 (1980-11-
22) B-Telegraph and Telephone Public Corporation Musashino Telecommunications Research Institute, Kashiwara,
There was one described in Yojima, P., 194.7-1968.

The line setting circuit that performs the above line setting is the central part of the synchronous multiplex converter. The synchronous multiplex converter will be explained below.

The synchronous multiplex converter terminates a 1.544 Mbit/a or 6.312 Mbit/s digital transmission line, and
Channel line setting group (Handling Group)
:HG) and terminate the line in the same unit, 2.048Mbit/s or 8.192Mbj
It is connected to the digital exchange through a t/s intra-office interface.

Line settings are made using TSI (Time SlotIn), which swaps the time and space occupied positions of time slots in data strings.
terchanger), and a semi-fixed time switch is realized as a configuration in which the order of changing time slots can be controlled from the outside.

The interface conditions between the synchronous multiplex converter and the digital transmission path and the interface conditions between the synchronous multiplex converter and the exchange are as follows.

The digital transmission line accommodated by the synchronous multiplex converter is 1.54
4 Mbit/s primary group transmission line and 6.312 Mb
It is an i t/S secondary group transmission line, and the channel capacity of each transmission line interface is 24 channels and 96 channels, respectively, in terms of 64 kbit/3 telephone channels. On the other hand, the interface with the exchange is 2.048Mbi.
t/,.

The channel capacity of each intra-office interface is 30 channels and 120 channels, respectively.

In the synchronous multiplex converter, the transmission line termination function, two line setting functions, and the two line termination functions described earlier are used.

In addition to the intra-office interface function, a multiplex conversion function is required to convert the signal speed and channel capacity of each interface depending on the transmission path and intra-office interface conditions.

Next, a conventional method of configuring a circuit for realizing line setting and multiplex conversion in a synchronous multiplex converter will be described. In the following explanation, in order to avoid complicating the explanation, the transmission line interface is assumed to be 6.312 Mbit.
732nd order group interface, internal office interface 8.
Although the present invention is limited to a 192 Mbit/s intra-office interface, it is also possible to accommodate other transmission line interfaces and intra-office interfaces.

FIG. 2 is a block diagram showing an example of the configuration of a line setting circuit of a synchronous multiplex converter and a multiplex converter, and shows the line setting circuit in the direction from the transmission path to the inside of the station (R direction). lN1(
t=1~40) are 6,312 Mbtt/s, respectively.
Received from secondary group transmission line interface, 8.19
This is a 96-channel multiplex signal whose speed has been converted to 2 Mbit/a. Five 96-channel multiplex signals are multiplex conversion circuit 1
The signal is converted into four 120-channel multiplexed signals. Hereinafter, this multiplex conversion circuit 1 will be referred to as a 5/4 conversion circuit. 2 to 8 are similar 5/4 conversion circuits, and with these 8 total 5/4 conversion circuits, 40 96-channel multiplexed signals sent from the transmission line are converted to 120-channel multiplexed signals 32. Multiple conversion into books. 9 is the line setting circuit, and 12 is converted by the 5/4 conversion circuit of 1 to 8.
32 0-channel multiplexed signals are set up by exchanging time slots for each line editing group HG (in units of 6 channels), and a 120-channel multiplexed signal is sent out. 0UTt
(i = 1 to 32) are each signal speed 8.192
A 120-channel multiplexed signal of Mbit/s is sent to the intra-office interface.

In the above explanation, the multiplex conversion and line settings in the direction from the transmission line to the inside of the station (R direction) were described, but for the direction from the inside of the station to the transmission line (S direction), the configuration is completely symmetrical to the R direction, i.e. 415 conversion circuit and line setting circuit are required.

Since the line setting circuit 9 has a function of rearranging the temporal order of input data and outputting the same, it requires some kind of memory function. The principle is shown in Figure 3.

In the figure, 10 is a data memory, 11 is a data memory 10
12 is an address counter, 13 is a write address, 14 is an address control memory, 15 is a read address, and 16 is an output of the data memory 10.

The data DIN that has arrived at the input 11 of the data memory 10 is sequentially sent to the data memory 10 according to the write address 13 that is the output of the address counter 12 (5equ
ntial). Write address 13
is an address control memo! JIJK is also given at the same time, and the address control memory 14 gives the data memory 10 a read address 15 that has been written in advance in correspondence with the given address 13. The data memory 10 outputs 1 according to this address 15.
6, the data is read out and output as DOUT. That is, since the time slot conversion information between the input and output of the data memory is stored in the address control memory 14, the order of reading data in the delta memo I)1 is in accordance with this time slot conversion information.

In devices with such a channel switching function,
For any given channel, all bits in the same frame must be treated as one, and the order with bit strings in other frames must be maintained. TSS this
I (Time 5lot SequenceInte
Grity). In order to guarantee TSSI, the above line setting circuit employs a double buffer format. This is a method that writes and reads data every cycle to a memory that has a capacity for two cycles of data.
A block diagram showing the principle is shown in FIG. 17 is the input of the line setting circuit, 18 is the switch, 19 is the data memory, 2
0 is the input of the data memory 19, 21 is the address counter, 22 is the write address, 23 is the switch, 24 is the write address of the data memory 19, 25 is the address control memory, 26 is the read address, 27 is the switch, 28 is the data memory , 29 is the data memory 28
read address, 30 is the output of the data memory 28,
31 is a switch, 32 is the output of the line setting circuit, 33 is the input of the data memory 28, 34 is the write address of the data memory 28, 35 is the read address of the data memory 19, and 36 is the output of the data memory 19. The switches 18, 23, 27, and 31 are connected to the solid line side in the first period, and are connected to the broken line side in the second period, and thereafter, the switches 911. ? Can be replaced.

In the first period, input 17 of the line setting circuit is connected to input 20 of data memory 19 by switch 18Vc. Also, the write address 22 which is the output of the address counter 21 is transferred to the data memory 1 by the switch 23.
It is connected to the write address 24 of 9. As a result, all data in the first cycle is written to the data memory 19.

Ru. On the other hand, the read address 26 which is the output of the address control memory 25 is connected to the read address 29 of the data memory 28 by the switch 22. Further, an output 30 of the data memory 28 is connected by a switch 31 to an output 32 of the line setting circuit. by this,
In the first period, the contents of the data memory 28 are read out as output. In the second period, switches 18, 23
The connections at 27.31 are reversed, input 17 is written to data memory 28, and the contents of data memory 19 are written to output 32.
becomes. A time chart of the above operation is shown in FIG.

Here, a case is shown in which data for one cycle is 4 bits, writing is performed in the order of 1.2.3.4, and reading is performed in the order of 2, 4, 3.1. For each memory, W indicates writing and R indicates reading. Further, the address counter is reset every two cycles. As is clear from this, since all data is read out with a delay of one cycle, TSSI is guaranteed. This method is called a parallel double buffer format because it uses two memories having a capacity for one period of data (4 bits in FIG. 5) in parallel.

In the actual line setting circuit, the data input/output is 8.192.
According to the intra-office frame format of Mbit/s, line setting is performed after serial-parallel conversion of 8-bit data for 120 channels (20 HG), so one cycle is 160 bits when line setting is performed in HG units. This value is approximately 1/6 frame. Regarding data memory, an LSI with a built-in address counter has been developed.

(Problems to be Solved by the Invention) However, the above line setting method requires two data memories and a large number of changeover switches.
The problem is that the address counter is reset every 173 frames, and as the hardware becomes larger, the control circuit becomes more complex.

(Means for Solving the Problems) The present invention provides a line setting method for a synchronous multiplex converter by writing input data into a data memory having a capacity equivalent to the number of data bits for one frame, and setting the line. The data is read out with a delay of one cycle, and the address counter is reset once per frame cycle.

(Function) Input data is written from the beginning of the frame to a data memory with a capacity equivalent to the number of data bits for one frame, and the line setting cycle is 1 from the time the beginning of the frame is written.
Since the data is read with a delay of a period, all bits in the same frame are treated as one, and the order with bit strings in other frames is maintained, ensuring TSSI.

Further, the address counter is reset once per frame period.

(Embodiment) FIG. 6 shows a simplified time chart of the serial type double buffer format, which is the principle of the present invention, by reducing the number of data in one cycle. Input data within one cycle is 4
Bit. The time width of each bit of the input r-data is divided into two equal parts, the r-time is written into the data memory in the first half of the divided time, and the data is read from the data memory in the second half. At this time, the addresses for writing and reading data are periodically reversed. Note that the capacity of the data memory is 8 bits, and within a certain cycle, f-2 is written in the first half bits of the data memory, and data is read from the second half 4 bits. In the next cycle, data is read from the first 4 bits of the data memory.

Write data to the latter 4 bits. Therefore, as shown in FIG. 4, instead of using two data memories, one data memory with the capacity of two data memories is used, and the write/read cycle is performed at twice the speed of the input data. A double-buffer format is realized in a time-division manner. In this case, the basic block diagram will be the same as in FIG.

In the time chart of FIG. 6, the addresses for writing and reading data are exchanged every cycle. However, the double buffer format can also be realized by writing input data sequentially from the first address into a data memory having a capacity corresponding to one frame's worth of data, for example, and starting readout after one cycle. Therefore, in the line setting circuit, the capacity of the data memory is set to 1024 bits (8,
Biy in one frame of 192Mbit/s intra-office frame
A cedar pull buffer format can be realized by setting the input data to 160 bits corresponding to one period (approximately 1/6 frame) and reading the data according to the contents of the address control memory.

FIG. 1 is a block diagram of a circuit setting circuit for 3840 channels implemented using the present invention. In the figure, 37 is a data memory section, 38 to 4 are data memories having a capacity for one frame of input data, 42 to 45 are data inputs of data memories 38 to 41, respectively, 46 is an address counter, and 47 is a write address. , 48 is an address control memory, 49 is a read address, 50 to 53 are outputs of the data memories 38 to 41, respectively, and 54 is a selector which uses the outputs 50 to 53 of the data memory as data inputs and the read address 49 as a control input. .

The input 3840 CH is 640 HG in line editing unit, and 8,192 Mbit7' after serial/parallel conversion! Since the intra-office frame of l is 160 HG, it is 3840CI.
(In order to set up a serial double-buffer format line for input data using one data memory, the operating frequency of the data memory is 8.192MHzX2X640HG/160HG = 6
The frequency is 5.536 MHz. Since such high-speed memory does not currently exist, four data memories are used in parallel,
Each data memory is 8.192 Mbit/
Configure the line for one intra-office frame (160HG) for s. At that time, the operating frequency for writing and reading is 16.3
84 Ml (becomes z.

In FIG. 1, numeral 37 is a data memory unit corresponding to 960CH (1,60HG), which is composed of four data memories 38 to 41. These four data memory sections realize a line setting circuit compatible with 3840CH (640HG). That is, each input 42 to 45 of the data memory is
It is common to the input of the corresponding data memory in other data memory sections, and according to the write address 47 which is the output of the at/counter 46, DINi (i=1 to 4) 640 HG worth of data is sequentially written. On the other hand, according to the read address 49 which is the output of the address control memory 48,
Each data memory section is 160HG(7)f out of 640HG
-Read data. These 160 HG data are selected by the selector 54 from outputs 50 to 53 of each data memory in the data memory section, and are output as DOUT.

The same applies to DOUTi (i”2 to 4).Selector 5
4, the output of the address control memory 48,
19.

This type of line setup is called a parallel 71-stage configuration.
In this case, if a parallel double-buffer format is adopted, a large number of data memory chips are required, and it is also necessary to install a cap/lid around the periphery corresponding to each memory bare. On the other hand, if the serial double buffer format is adopted, the number of data memory chips will be reduced to 1/2, and the number of selectors will also be reduced. In this case, the random read address of the data memory given externally, that is, the contents of the address control memory, is the line setting information, and in the parallel type, the HG unit is 1.
The total of 8 bits for 60HG and 2 bits for selector control is 10 bits, whereas in the [-1 series type, it is expanded to channel scale and has 10 bits for 1024 bits and 2 bits for selector control. In this case, the data is converted into 12 bits, which is Δ-I, and used as data in the address control memory. For this reason, the hardware size increases slightly, but it is small compared to the decrease in the number of data memory chips.

1 and 2. In the present invention, the address counter may be reset every frame, and is performed approximately 1/6 of the time from the time when the beginning of the frame is written into the data memory. Therefore, reset control is also simplified, and the scale of the hardware is correspondingly smaller and simpler.

(Effects of the Invention) As described above in detail, according to the present invention, the capacity of the data memory is reduced to one frame, so the number of data memory chips can be reduced to 1/2, and the peripheral circuitry can also be reduced. It has become simpler and the scale of the hardware has been reduced overall.

Furthermore, even if some information is inserted into empty bits that do not contain data in an intra-office frame and transmitted within the device, this can be handled simply by changing the contents of the address control memory.

Furthermore, since it is only necessary to reset the address counter in units of one frame, there is an advantage that the control circuit can be made small and simple.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a line setting circuit with a parallel 71-stage configuration showing a preferred embodiment of the present invention, FIG. 2 is a block diagram of a line setting circuit and its surroundings in a synchronous multiplex converter, and FIG. 3 is a block diagram of a line setting circuit in a synchronous multiplex converter. A block diagram of the setting circuit, Figure 4 is a block diagram of the line setting circuit of the parallel type double-two-way type,
FIG. 5 is a time chart of the line setting circuit shown in FIG. 4, and FIG. 6 is a time chart of the serial double buffer type line setting circuit. In the figure, 1 to 8 are 5/4 conversion circuits, 19 is a line setting circuit,
10 is the data memory, 1 is the input of the data memory 10,
12 is an address counter, 13 is a write address, 14
is the address control memory, 15 is the read address, 16 is the output of the data memory 10, 17 is the input of the line setting circuit, 18 is the switch, 19 is the data memory, 20
is the input of the data memory 19, 21 is the address counter,
22 is a write address, 23 is a switch, 24 is r-
25 is an address control memory, 26 is a read address, 27 is a switch, 28 is a data memory, 2! Kawamabuta Memory 2
8 is the read address, 3θ is the output of the data memory 28, and 31 is the swing. 32 is the output of the line setting circuit, 33 is the input of the data memory 28, 34 is the write address of the data memory 28, 3
5 is a read address of the data memory 19, 36 is an output of the data memory 19, 37 is a data memory section, 38 to 4
1 is a data memory having a capacity for one frame of input data, 42 to 45 are data inputs of data memories 38 to 41, respectively, 46 is an address counter, 47 is a write address, 48 is an address control memory 1), 491
d. Read addresses 50-53 are outputs of data memories 38-4I, respectively, 54 are outputs 50-5 of data memory
3 as a data input and read address 49 as a control input. Patent applicant Oki Electric Industry Co., Ltd. Nippon Telegraph and Telephone Corporation No. 4 Leap. The line setting circuit is the same as the one shown in Figure 5. Turning information, ro 1
Written amendment to the procedure shown in Figure 6 of each cut button Buddha (spontaneous) 1 Indication of the case 1985 Patent Application No. 181103 2 Name of the invention Line setting circuit 3 Person making the amendment Relationship with the case Patent application Office (
105) 1-7-12-4 Toranomon, Minato-ku, Tokyo.
Agent (1 other person) Address (〒105)
No. 7-12 Egome, Toranomon, Minato-ku, Tokyo 5. Subject of amendment: ``Detailed description of the invention'' column, ``Brief explanation of the drawings'' column and drawing ``Figure 1'' 6. Contents of amendment ( 1) In the 19th line of page 15 of the specification, the phrase "driving again" should be corrected to ", driving still." (2) In the same book, page 18, line 8, "19" is corrected to "9". (3) Amend the drawing, “Figure 1” as shown in the attached sheet. that's all

Claims (2)

[Claims] (1) In a line setting circuit that temporarily stores input data and performs time slot conversion in units of 6 channels to obtain a signal arrangement different from the input signal, data for 6 channels is stored for all line setting units of 6 channels. the first one at a different address in data memory.
means for sequentially writing data from the first channel to the sixth channel; means for randomly reading from the data memory from the first channel according to the contents of the address control memory after the writing of the first channel is completed; and random data sent from the outside in units of six channels. 1. A line setting circuit comprising means for writing a read address into a random read address control memory for each channel. (2) The line setting circuit according to claim 1, characterized in that the means for writing to the data memory, the means for reading from the data memory, and the means for writing to the address control have a parallel T1 stage configuration. .