JPS5789358A - Line control system - Google Patents

Line control system

Info

Publication number
JPS5789358A
JPS5789358A JP55164846A JP16484680A JPS5789358A JP S5789358 A JPS5789358 A JP S5789358A JP 55164846 A JP55164846 A JP 55164846A JP 16484680 A JP16484680 A JP 16484680A JP S5789358 A JPS5789358 A JP S5789358A
Authority
JP
Japan
Prior art keywords
data
fifo queue
transmission
timing
receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55164846A
Other languages
Japanese (ja)
Other versions
JPH0235500B2 (en
Inventor
Zenichi Yashiro
Mineo Nishiwaki
Shuhei Arima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP55164846A priority Critical patent/JPS5789358A/en
Publication of JPS5789358A publication Critical patent/JPS5789358A/en
Publication of JPH0235500B2 publication Critical patent/JPH0235500B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To prevent the overrun and the underrun of data, by providing a transmission first in first out (FIFO) quenue controlled to fill with data and a receiving FIFO queue controlled to be empty of data. CONSTITUTION:Data is transferred between a transmission FIFO queue 240 and a receiving FIFO queue 250 and a data transmitting and receiving circuit 220 synchronously with timing signals ST' and RT' generated by a timging generating circuit. The transmission FIFO queue has a function which detects whether it is filled up with transmission queuing data or not, and the detection signal is applied to the timing generating circuit to stop the generation of the timing signal ST'. The receiving FIFO queue has a function which detects whether stored contents are zero or not, and the detection signal is applied to the timing generating circuit to stop the generation of the timing signal RT'.
JP55164846A 1980-11-22 1980-11-22 Line control system Granted JPS5789358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55164846A JPS5789358A (en) 1980-11-22 1980-11-22 Line control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55164846A JPS5789358A (en) 1980-11-22 1980-11-22 Line control system

Publications (2)

Publication Number Publication Date
JPS5789358A true JPS5789358A (en) 1982-06-03
JPH0235500B2 JPH0235500B2 (en) 1990-08-10

Family

ID=15801026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55164846A Granted JPS5789358A (en) 1980-11-22 1980-11-22 Line control system

Country Status (1)

Country Link
JP (1) JPS5789358A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6014555A (en) * 1983-07-06 1985-01-25 Fuji Facom Corp Serial data receiver
US5247616A (en) * 1989-10-23 1993-09-21 International Business Machines Corporation Computer system having different communications facilities and data transfer processes between different computers

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6014555A (en) * 1983-07-06 1985-01-25 Fuji Facom Corp Serial data receiver
JPH0561827B2 (en) * 1983-07-06 1993-09-07 Fuji Facom Corp
US5247616A (en) * 1989-10-23 1993-09-21 International Business Machines Corporation Computer system having different communications facilities and data transfer processes between different computers

Also Published As

Publication number Publication date
JPH0235500B2 (en) 1990-08-10

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