JPS5794824A - Data processing system having bus converter - Google Patents
Data processing system having bus converterInfo
- Publication number
- JPS5794824A JPS5794824A JP16947380A JP16947380A JPS5794824A JP S5794824 A JPS5794824 A JP S5794824A JP 16947380 A JP16947380 A JP 16947380A JP 16947380 A JP16947380 A JP 16947380A JP S5794824 A JPS5794824 A JP S5794824A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- bus
- speed
- occupation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To prevent the occurrence of an undesired overrun for a high-speed input/output device, etc., by releasing once the occupation of a high-speed bus through a bus converter. CONSTITUTION:Both signals IOP and DTSD are received at a mode timing circuit 14, and the address information ADR is latched to an address latching circuit 10. An open signal OPEN is raised up, and at the same time the circuit 14 transmits a service-out signal SVOI to the side of a low-speed bus to carry out the control so as to transmit the contents of the circuit 10. When receiving a service in signal SVI of a low-speed input/output device, the circuit 14 lowers the signal OPEN to give an occupation request for the high-speed bus. Then the data is sent to the side of the high-speed bus via a data driver 13 when a bus occupation permission signal OPENAV is received. And a data confirmation signal DTAK is transmitted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16947380A JPS5794824A (en) | 1980-12-03 | 1980-12-03 | Data processing system having bus converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16947380A JPS5794824A (en) | 1980-12-03 | 1980-12-03 | Data processing system having bus converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5794824A true JPS5794824A (en) | 1982-06-12 |
Family
ID=15887202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16947380A Pending JPS5794824A (en) | 1980-12-03 | 1980-12-03 | Data processing system having bus converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5794824A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60189053A (en) * | 1984-03-07 | 1985-09-26 | Seiko Epson Corp | Data transfer controller |
JPS61110250A (en) * | 1984-11-02 | 1986-05-28 | Hitachi Ltd | Data processing system provided with plural bus |
JPS61216074A (en) * | 1985-02-14 | 1986-09-25 | Fujitsu Ltd | Direct memory access system |
JP2006113689A (en) * | 2004-10-12 | 2006-04-27 | Fujitsu Ltd | Bus bridge device and data transfer method |
-
1980
- 1980-12-03 JP JP16947380A patent/JPS5794824A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60189053A (en) * | 1984-03-07 | 1985-09-26 | Seiko Epson Corp | Data transfer controller |
JPS61110250A (en) * | 1984-11-02 | 1986-05-28 | Hitachi Ltd | Data processing system provided with plural bus |
JPS61216074A (en) * | 1985-02-14 | 1986-09-25 | Fujitsu Ltd | Direct memory access system |
JP2006113689A (en) * | 2004-10-12 | 2006-04-27 | Fujitsu Ltd | Bus bridge device and data transfer method |
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