JPH04270521A - Multiplex channel receiver - Google Patents

Abstract

PURPOSE:To reduce the hardware and the cost by using a serial/parallel converter for multiple channels in common. CONSTITUTION:A serial/parallel converter SP is provided with a reception shift register RXS and a reception counter RXT. Then a prescribed transmission/reception clock is externally applied to the serial parallel converter SP for the operation at a prescribed channel to implement transmission reception for a serial data by a prescribed bit in the usual operation. Then a data storing the state of each function block at present is once saved to an external storage RM for the operation of other channel. After the saved data of the preceding relevant channel is read from the RM being a save RAM for the operation of another channel, the transmission/reception clock is supplied externally to implement the transmission/reception for some bits and the operation is transited for the other channel operation.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex channel device for data transmission over a plurality of lines or for data transmission in which a plurality of channels are multiplexed over one line. For example, in the ISDN primary group interface, 24 or 30 channels are multiplexed in one line, and these channels operate simultaneously to process data.

[0002] In this case, the amount of hardware required is enormous in order to handle simultaneous processing.

0003

2. Description of the Related Art FIG. 7 is a diagram showing the configuration of a conventional system. The plurality of lines L are connected to the receiver/driver RD via respective modems M, and in response to the reception clock RXC, the reception data RXD is connected to the corresponding serial-to-parallel converter SP.
be taken in. And serial-parallel converter S
The data stored in P is sent to serial-to-parallel converter SP
The data is converted into parallel data and sent to the microprocessor MPU, memory RAM, ROM, etc. As shown in the figure, in the conventional configuration, a serial-to-parallel converter SP is provided for each RD. As described above, a serial-to-parallel converter is required as a multiplexed channel receiving device, and conventionally, a device called a "line control LSI" has been frequently used as this serial-to-parallel converter. In this line control LSI, a signal from a line interface is supplied to serial-to-parallel converters #0 to #n for each channel by a receiver/driver RD.

0004

[Problems to be Solved by the Invention] Conventionally, when controlling the simultaneous operation of multiple lines or multiple channels in one line using this line control LSI, it is necessary to Requires serial-to-parallel converter. Therefore, such a configuration causes an increase in the amount of hardware, resulting in an increase in cost.

[0005] An object of the present invention is to reduce hardware by sharing a single multi-channel serial-to-parallel converter, thereby reducing costs.

[0006]

[Means for Solving the Problems] FIG. 1 is a system configuration diagram to which the present invention is applied. As shown in the figure, the present invention has a configuration in which one serial-to-parallel converter is shared by each channel. In this way, in order to share the serial-to-parallel converter between multiple channels, the multiplex channel receiving device of the present invention includes a control means for controlling its operation from the outside, and a control means for saving and restoring its internal information from the outside. and a memory for saving saved/restored data.

[0007]

[Operation] When receiving data, the serial-to-parallel converter SP normally converts input serial data into parallel data in response to a predetermined external clock. A serial-to-parallel converter usually consists of a shift register, and the internal information of this shift register (i.e., the data in the shift register and the number of bits of that data)
It is only necessary that the data can be temporarily saved/restored to/from external memory according to instructions from the outside.

If such data saving/restoring is temporarily executed, the original data in the shift register constituting the converter can be saved as a step for sharing the serial-to-parallel converter with multiple channels. SAVE INSIDE INFORMATION
→Load new internal information →Receive operation (normal serial-to-parallel converter processing, i.e. perform serial → parallel conversion, and if assembly to parallel data is completed, send the data to the receive buffer) By performing the following operations: → SAVE internal information → repeat the following steps, multiple channels can be operated simultaneously even if only one serial-to-parallel converter is used.

[0009]

Embodiment FIG. 2 is a block diagram of one embodiment of the present invention. RX
-FIFO #0, #1, #2 are reception FI for each channel
FO (first in, first out buffer), RG is a data presence/absence display register, RP is a read pulse generation circuit, S is a serial-to-parallel converter of the present invention, and RM is a RAM for saving. The serial-to-parallel converter SP includes a reception shift register RXS and a reception counter RXT.

[0010] Normally, line control LSIs are used for transmitting/receiving (Tx
/Rx), each register for transmission/reception,
It also includes functional blocks such as a transmitting and receiving CRC generator/checker. In the present invention, each of these functional blocks included in the line control LSI is operated intermittently. In the basic operation of the present invention, as an operation for a predetermined channel, a predetermined transmission/reception clock is supplied to the serial-to-parallel converter from the outside, and serial data is transmitted and received for a predetermined bit amount in normal operation. In order to perform another channel operation, data holding the current state of each functional block is temporarily saved to external storage.

FIG. 3 is a signal timing chart of the present invention.
FIG. 4 is a basic flowchart of the present invention using FIFO #0 as an example. As shown in Figures 3 and 4, the serial data for each channel is transferred by a clock for serial data, and the FIFO is sent by a write pulse RX pulse to the FIFO.
Incorporated into FO. Then, the read pulse RP is sent from the read pulse generation circuit to the FIFO to perform reading from the FIFO.

[0012] Such an operation will be specifically explained below. For each FIFO for transmitting/receiving (Tx/Rx), the value of a pointer indicating how far data is stored in multiple FIFOs and the RAM for saving data in the FIFO are stored.
evacuate to. For each shift register for transmission/reception, the value of the pointer indicating up to which bit of each shift register contains data and the data in the shift register are saved to the save RAM. The CRC generator checker also saves the CRC value calculated so far to the save RAM.

Next, for the operation of another channel, the previously saved data of the other channel is restored from the save RAM, and then a transmit/receive clock is supplied from the outside to perform the transmit/receive clock.
After performing the receiving operation for several bits, the process moves to another channel operation. Here, there is a discrepancy between the actual transmission and reception speed of the line and the transmission/reception speed of the serial-to-parallel converter according to the present invention, but a serial data storage section is placed between the two to compensate for the difference in speed between the two. I'm trying to adjust it. That is, data received from the line is sampled and then held in a serial data storage (FIFO) at the same speed as the communication speed, and the serial-to-parallel converter of the present invention transfers data from the serial data storage at a speed faster than the communication speed. Performs the extraction serial-to-parallel conversion operation.

An embodiment of an interface in which a plurality of channels are multiplexed on one line as seen in ISDN will now be described. In ISDN, multiple channels are physically time-divided and transmitted over one transmission path. How to separate the data into each channel from here depends on the interface convention (frame format), but
For example, after the repetition of one or several frame synchronization bits is done by matching a predetermined pattern,
The data can be counted based on each frame synchronization bit and extracted as data for each channel.

The serial data separated as described above is stored in a FIFO for each channel. Note that this is done at the timing shown in FIG. 3 so as not to conflict with data reading from the FIFO from the serial-to-parallel converter. That is, FIFO reads/writes do not occur simultaneously, writes occur at the same rate as the bit rate of the channel, and reads occur several times faster. Note that reading is performed only when there is data remaining in the FIFO.

Next, the operation of the serial-to-parallel converter will be explained. In FIG. 2, this configuration can also be configured with a microprocessor (MPU), for example. The microprocessor is able to know in which FIFO data exists by using the data presence/absence display register RG of each transmission FIFO. Here, the FIFO
Some devices have a function that notifies you of the amount of data remaining in addition to the presence or absence of data. The microprocessor gives a read pulse (which can be read out faster than the write pulse mentioned above) to the FIFO where data remains, reads out the serial data, and the data is given as data to the serial-to-parallel converter, and the read pulse is Give it as a serial clock.

Inside the serial-to-parallel converter, data is sampled using the clock and assembled into parallel data using a shift register. Here, if it is assembled as 8-bit parallel data, it becomes a received character, and if the number of FIFO read pulses is insufficient to assemble 8-bit parallel data and the end is completed, the number of effective bits remaining in the shift register is 3 bits. This can be known from the counter.

[0018] The microprocessor saves the contents of the shift register and the contents of the 3-bit counter to the RAM for saving for the next channel operation, and restores the previously saved data of the next channel to the shift register and the 3-bit counter. , reads several bits of data from the FIFO and performs serial-to-parallel conversion. In the present invention, these operations are repeated.

[0019] For the sake of simplicity, only the shift register section has been described above, but the same applies to other parts, such as the CRC calculation register and the synchronization pattern detection circuit for synchronizing the SYN flag. Evacuation/
It is possible to operate by returning. FIG. 5 is a detailed diagram of the data presence/absence display register shown in FIG. 2. A register is provided for each FIFO input, and a register is selected and output by a register selection pulse.

FIG. 6 is a detailed diagram of the read pulse generating circuit shown in FIG. 2. It has a register for each FIFO, inputs the output from the pulse generation counter to AND gates #0 to #2, and generates a read pulse when it matches the output of the register.

[0021]

[Effects of the Invention] As explained above, according to the present invention,
In data processing of multiplexed channels, data can be saved/restored by sharing a serial-to-parallel converter for each channel, thereby reducing hardware and cost.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram to which the present invention is applied.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a signal timing chart of the present invention.

FIG. 4 is a flowchart of an embodiment of the present invention.

FIG. 5 is a detailed diagram of the display register of FIG. 2;

FIG. 6 is a detailed diagram of the read pulse generation circuit of FIG. 2;

FIG. 7 is a conventional system configuration diagram.

[Explanation of symbols]

SP…Serial-to-parallel converter RD…Receiver driver FIFO...First-in, first-out buffer RG...display register RP…Read pulse creation circuit RM...Evacuation memory L...Line RXC…Reception clock RXD…Receive data

Claims (2)

[Claims] Claim 1: In a multiplex channel device for data transmission over multiple lines or data transmission in which multiple channels are multiplexed over one line, serial data storage means for temporarily storing data from the lines; A single serial-to-parallel conversion means for receiving serial data and converting it into parallel data, and a saving means for temporarily saving the serial data being received by the serial-to-parallel conversion means. 1. A multiplex channel receiving device characterized in that, when converting to data, serial data is saved in the saving means and serial-to-parallel conversion of the next storing means is performed by time division. 2. A device for converting multiplexed received data using a single serial-to-parallel conversion means, comprising:
A multiplexed channel receiving device comprising counting means for counting the effective bit length in a shift register of a predetermined data length.