JPH0313147A - Frame converting circuit for asynchronous/synchronous interface - Google Patents

Abstract

PURPOSE:To improve transmission efficiency in packet communication, etc., by counting the number fo effective data and applying the number as an additional bit. CONSTITUTION:A sampling circuit 2 restores an asynchronizing signal, excludes a start bit or stop bit which are redundant bits, sends only the effective data to a FIFO memory 5 and applies 1 signal, which shows the position of the effective data, to the FIFO memory 5 or an asynchronous side counter circuit 3. The asynchronous counter circuit 3 counts the number of the signals and presets the number of the effective data to a synchronous side counter circuit 6. Next, data to be limited to the number of the effective data, which is preset to the synchronous side counter circuit 6, are read from the FIFO memory 5 and gathered as a packet signal. Then, a result counted by the synchronous side counter circuit 6 is multiplexed to a main signal by a multiplexing circuit 8. Thus, redundant data are removed and the transmission efficiency can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interface between an asynchronous communication device and a synchronous backbone line in digital communication, and in particular to frame conversion used when bundling data from an asynchronous communication device into packets. Regarding circuits.

[Conventional technology]

FIG. 4 shows the configuration of a conventional interface section between this type of asynchronous communication device and a synchronous backbone line.

In the figure, 11 is an asynchronous communication terminal, 12 is a sampling circuit that samples the signal from this asynchronous communication terminal 11 at a speed several times the transmission speed and restores the data, and 13 generates timing in accordance with the asynchronous system. an asynchronous timing signal generation circuit; 14 is a synchronous timing signal generation circuit that generates timing along a synchronous relay line; 15 is a time adjustment between the asynchronous timing signal generation circuit 13 and the synchronous timing signal generation circuit 14; First In Fi: First In Fi
rst 0ut) memory.

First, when a line is established and data is sent from the asynchronous communication terminal 11 to the sampling circuit 12, the sampling circuit 12 constantly samples at a speed several times that of the received data, so the asynchronous data as shown in FIG. frame formats can be detected. Then, at the timing according to the asynchronous timing signal generation circuit 13, the FIFO
Writing is performed in the memory 15.

Thereafter, the written data is read out from the FIFO memory 15 at a timing consistent with the synchronous timing signal generation circuit 14 and multiplexed onto the synchronous relay line.

[Problems to be Solved by the Invention] In the frame conversion at the interface between the conventional asynchronous communication terminal and the synchronous backbone line described above, after detecting data from the asynchronous communication terminal, the data is transferred as it is to the FIFO.
Since the time is adjusted using the mesh and sent to the synchronous backbone line, the start bit and stop bit used to determine asynchronous data are also sent together. In addition, in the case of an asynchronous frame structure as shown in FIG. 5, 3.5 bits of redundant data are added to 8 bits of valid data, which is wasteful in terms of transmission efficiency.

An object of the present invention is to provide a frame conversion circuit that improves transmission efficiency by removing such redundant data.

[Means for Solving the Problems] A frame conversion circuit of the present invention includes a circuit that samples a signal from an asynchronous communication device at a higher speed than the data to be transmitted, restores the signal, and removes redundant bits, and the asynchronous side A circuit that counts the number of data during a certain period of
It includes a circuit that reads out data on the synchronous side from the FO memory, and a circuit that multiplexes the counting results of the counting circuit into the data.

[Effect]

In this configuration, in the asynchronous system, data with redundant bits removed is written to the FIFO memory and the number of data is counted at the same time, and in the synchronous system, data is read from the FIFO memory based on this counted value, and the counted value is added to this data. It is multiplexed, sent out to the backbone line, and bundled as a packet signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, 1 is an asynchronous communication terminal, 2 is a sampling circuit that samples the signal from the asynchronous communication terminal 1 at a speed several times the transmission speed, restores the signal, and removes redundant bits, and 3 is a sampling circuit 2 4 is an asynchronous timing signal generation circuit for writing asynchronous side data to the FIFO memory 5; 5 is a FIFO memory for adjusting the time between asynchronous synchronous periods; 6 is a synchronous side counting circuit that counts the number of data output from the FIFO memory 5 using information from the asynchronous side counting circuit 3, regulates the output, and indicates the number; 7 is an output of the PIFO 5 from the synchronous side timing. A synchronous timing signal generation circuit 8 generates timing, and 8 indicates a multiplexing circuit that multiplexes the count result of the synchronous side count circuit 7 onto the main signal from the FIFO memory 5.

In this circuit configuration, first, when an asynchronous signal is input from the asynchronous communication terminal 1 to the sampling circuit 2, it is sampled at several times the data transmission speed, and the signal is restored as shown in FIG. , and redundant bits such as start bits and stop bits are removed. Then, only valid data is sent to the FIFO memory 5. The sampling circuit 2 also supplies a signal indicating the position of valid data to the FIFO memory 5 and the asynchronous count circuit 3.

The asynchronous count circuit 3 counts that one signal,
The number of valid data is determined from this counting result and is preset in the synchronous side counting circuit 6.

The FIFO memory write operation up to this point is controlled by the timing signal output from the asynchronous timing signal generation circuit 4.

Next, when data is read from the FIFO memory 5, it is controlled by a timing signal outputted from a synchronous timing signal generation circuit 7, which is similar to or similar to the timing of a relay line.

At this time, data is not uniformly read out according to this timing signal, but data limited to the number of valid data pieces preset in the synchronization side count circuit 6 is read out and bundled as a packet signal. Further, the result counted by the synchronous side counting circuit 6 is multiplexed with the main signal by the multiplexing circuit 8.

The signal format in that case is shown in FIG.

As a result, only data and counting results from which redundant signals have been removed are sent out as packet signals. Therefore, compared to the conventional data area, there will be a vacant area. Note that a data area exists in the form of a packet at regular intervals on the line, but since the number of valid data in the data area is undefined at the interface with the asynchronous communication terminal 1, the number of valid data is added as an additional bit. You can know the valid data by checking the data.

In addition, on the side that is relayed through the transmission line and then sent to the asynchronous terminal, the number of data attached to the front of the data is read, only valid data is written to the FrFO memory, and the data is sent to the asynchronous terminal at the timing of the asynchronous side.

As described above, this circuit can easily realize frame exchange at the interface between the asynchronous communication terminal and the synchronous backbone line.

〔Effect of the invention〕

As described above, the present invention counts the number of pieces of data and adds them as additional bits in order to send only valid data on the transmission path, so it is possible to easily improve the transmission efficiency in packet communications and the like.

Furthermore, since a free space is created in the data area, multiplexing of other data into that area can be easily achieved by simply considering the timing on the synchronization side.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of an embodiment of the present invention, FIG. 2 is a time chart explaining the operation of the sampling circuit in FIG. 1, FIG. 3 is a data format diagram sent to the backbone line, and FIG. FIG. 5 is a block diagram of a conventional asynchronous synchronous interface, and FIG. 5 is an asynchronous frame format diagram. l...Asynchronous communication terminal, 2...Sampling circuit,
3...Asynchronous side count circuit, 4...Asynchronous timing signal generation circuit, 5...FIFO memory, 6...
Synchronous side count circuit, 7... Synchronous timing signal generation circuit, 8... Multiplex circuit, 11... Asynchronous communication terminal,
I2... Sampling circuit, 13... Asynchronous timing signal generation circuit, 14... Synchronous timing signal generation circuit, 15... FIFO memory. Figure 1 Figure 2 Figure 3 Theaenoa

Claims (1)

[Claims] 1. At the interface between the asynchronous communication device and the synchronous backbone line in data transmission, a circuit that samples the signal from the asynchronous communication device at a higher speed than the data to be transmitted, restores the signal, and removes redundant bits, and the asynchronous A circuit that counts the number of data during a certain period on the side, a circuit that writes this data to the first-in first-out memory at the timing of the asynchronous side, and a circuit that reads the data on the synchronous side from the first-in first-out memory based on the result of counting the number of data on the asynchronous side. 1. A frame conversion circuit for an asynchronous synchronous interface, comprising: a circuit; and a circuit for multiplexing the counting results of the counting circuit into data.