SU1379785A1 - Device for generating test sequences - Google Patents

Abstract

The invention relates to automation and computing, in particular to devices for generating test effects. The purpose of the invention is to expand the functionality. The device contains the initial test setting unit 1, the shift register 2, the feedback switch 3, the communication switch 4, the shift switch 5, the mode switch 6, the control unit 7. The inputs of the shift register 2 are the outputs of the device, the outputs of the initial test task unit 1 are connected to the inputs of the feedback switch 3, the communication switch 4, the shift switch 5, the shift register inputs 6. The second group of inputs of the shift register 2 is connected to the outputs of the switch 5 shift and switch 6 mode. The inputs-outputs of the shift register 2 are connected to the inputs-outputs of the commutator 3 feedback and the commutator 4 communications. The outputs of the control unit are connected to the control inputs of the switches 3-6 and the unit 1 of the initial test task. Expansion of functionality is achieved by introducing switches 3–6 feedback, links, shift, mode, and unit 1 to set initial tests, which allows changing the configuration of the shift register and its mode of operation, thereby forming test sequences with different properties. . 1 hp , 8 il. W (L with co 00 SP

Description

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The invention relates to automation and computing, and to devices for generating test effects.

The purpose of the invention is to expand the functionality by forming test sequences with various properties.

FIG. 1 is a diagram of the device; Fig. 2 is a block diagram of a task for initial tests; FIG. 3 is a control block diagram; Fig. 4 is a diagram of a feedback switch; FIG. 3 is a diagram of a communication switch; 6 is a diagram of a shear switch; 7 is a diagram of a mode switch; on Fig diagram of the shift register.

The device for generating test actions includes an "initial test setting unit 1, a shift register 2, a feedback switch 3, a communication switch 4, a shift switch 5, a mode switch 6, a control unit 7, an initial setup input 8, a device start input 9, in addition, a controlled object is depicted 10.

Unit 1 assigning initial tests (Fig. 2) contains switches 11-16, a counter 17, a switch 18, a delay element 19, a decoder 20.

The control unit 7 (Fig. 3) contains decoders 21 and 22, delay elements 23-28, a counter of 29 cycles, a clock generator 30, frequency dividers 31-33, an OR element 34.

The feedback switch 3 (FIG. 4) contains base cells 35-38, each of which contains AND 39.1-39.5 elements and adders 40.1-40.5 modulo two, and register 41.

The communication switch 4 (FIG. 3) contains elements AND 42.1-42.31, elements “with OR 43.1-43.11 and register 44.

The switch 5 shift (6) contains a register 45 and the elements 2I-4ILI 46.1-46.4.

The switch 6 of the mode (Fig.7) contains the register 47, the elements And 48.1-48.4 and the element AND NOT 49.

The shift register 2 (Fig. 8) contains the basic shift registers 50.1-50.4.

The device works as follows.

The operation of the device begins with the recording of the switching test KT1 in

13797852 4 communications switch. The start signal of the device passes to the control unit 7 and through the OR element 34 and the delay element 23 provides for issuing the read signals (THU) and the write CT1 (CTIT1). These signals are used to read the initial tests from unit 1 and write 4 KT1 links to the switch.

Upon termination of writing KT1 to the 4-link switch, unit 1 generates the code of the KT1 end tag (KKTI). This tag is read into control unit 7, where decoder 22 generates a CCT1 signal that passes through the OR 34 element and a delay element 26 and reads and writes the CT2 to the shift switch 5 via the CT signals and the DCT2 signals.

After reading the CCT2 tag, the decoder 22 generates the CCT2 serial passing through the OR 34 element and the delay and 24 element 24 causes the KTZ to read and write to the mode switch 6 using the CT and TTC signals.

After reading the KKTZ tag, deoshfrater 22 generates a KKTZ signal passing through the OR element 34 and the delay element 28 and reading and writing the KT4 to the switch 3 feedbacks using the CT signals and the PLCT signals 4.

After reading the CCT4 mark, the decoder 22 generates a CCT4 signal passing through the OR element 34 and the delay element 25 and causing reading and writing to the parts of the shift register 2 selected by the CTP of the initial state of the SRP using the CT signals and the CCPS.

Reading the end-of-record mark of the initial state of the SRTP (LELV) causes the output of the SPIDP signal, which, having passed through the OR 34 element, provides the reading of the number of cycles from block 1. After a time determined by the delay element 27, the counter has 29 cycles A signal is issued to enable the recording of information of the PDMS in the counter of 29 cycles, which records the number of cycles in the counter of 29 cycles and sets the time interval of the device operation. This completes the setting of the device operation mode.

From the setting unit of block 1, the code of the end of the write number of cycles (КЧ11) label is read, the decoder 22 generates

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CCT signal, which starts the generator 30 clock pulses. Clock pulses from the generator 30 are supplied to the dividers 31-33 frequency. From the output of the generator 30 and from the outputs of the dividers 31-33 frequencies to the switch 5 shift come the frequencies f, fr / 2, fp / 4, respectively. The test kits formed by the shift register 2 are fed to the controlled object 10.

If the contents of the counter 29 cycles is not zero, then the generator 30 continues its work. If the contents of the counter 29 cycles is zero, then a generator 30 stop signal appears at the output of the decoder 21. Otherwise, the content of the counter of the cycles 29 cycles is reduced. The clock pulses from the generator 30 are fed to a counter of 29 cycles, which operates in the subtraction mode.

The feedback switch 3 operates as follows.

According to the write test enable signal of the PLC4 test, received from the control unit 7 via the control input of the feedback switch 3, the switching test test KT4 is recorded in the register 41 from the unit 1 through the first input group of the feedback switch 3. The further operation of the feedback switch 3 will be considered using the base cell 35 as an example. From the input-output group of the feedback switch 3, the signals 1.1-1.5 that carry information about the state of the register 50.1 of the shift register 2 come to the inputs of the elements 39.1-39.5. the other inputs of the AND 39.1-39.5 elements receive control signals from the register 41. If the signal, for example, 1.4 participates in the feedback signal, then from the register 41 to the input of the And 39.2 element comes one, otherwise zero.

The signals from the outputs of the elements And 39.1-39.5 arrive at the inputs of the adder 40.1-40.5 modulo two. The second inputs of the adders 40.2-40.5 receive signals from the outputs of the adders 40.1-40.4, respectively, and the second input of the adder 40.1 receives the BxKI signal from the switch 4 of the links through the input / output group of the switch 3 feedback. Sequence10

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Really connected adders 40.1-40.5 produce a feedback signal EQ, which through a group of inputs-outputs of the switch 3 of the operational links goes to the switch 4 of the links. Base cells 36-38 are made according to the scheme of base cell 35 and work in the same way.

The recording of the CT1 in the communication switch 7 is carried out as follows. On the write enable signal of the Switching Test DCBT1, coming from the control unit 7 via the control input, the switching test KT1 is written to the register 44 from block 1 through the first group of inputs.

The write CT2 to the shift switch 5 is performed as follows. According to the write test enable signal of the PLCT test 2, coming from the control unit 7 via the second group of inputs, the switching text KT2 is written to the register 45 of the block I via the first group of inputs. The recording of the KTZ in the mode switch 6 is carried out as follows. According to the write enable signal of the test test of the DCTT, coming from the control unit 7 via the second group of inputs of the mode switch 6, the switching test test KT is recorded in the register 47 of the block 1 through the first group of inputs of the mode switch 6.

Block I of the initial tests works as follows. With the arrival of the initial setup signal, the counter 1 is set to the zero state. Then, the control input of block 1 from the control block 7 receives a read signal (THU), which transfers the counter 17 to the first state and after a time sufficient for switching the counter I7 and determined by the delay element 19 enters the switch 18 and allows the contents to pass counter 17 to control block 17 as a KKTI tag code. The first state of the counter 17 is fed to the decoder 20, at the output of which a single signal appears, which is fed to the input of the switch 16 of the communication code. From the output of the switch 16 of the communication code, the code KT1 arrives at the output of block 1. Then the operation of block 1 is repeated on the next signal THU from block 7 of control. On the following four signals, THB is vyraba513

KTZ, KT4, code of the number of cycles and initial states of the memory bandwidth.

Shift register 2 works as follows.

In accordance with KTI, the switch 4 communications provides the connection of the basic shift registers 50.1-50.4. In accordance with CT2, the shift switch 5 sets the shift direction and operating frequency for each base register 50.1-50.4 shift. In accordance with the KTZ mode switch 6 selects the basic registers 50.1-50.4 shift

mode, the initial test task block includes six switches, a decoder, a counter, a switch and a delay element, the counter installation input is the first input of the initial test task block and through a delay element connected to the control input of the switch, a group of information inputs of which are integrated with the decoder input group and connected to the group of information outputs of the counter, the reset input of the counter connect to the second

ga in which will be recorded at the input of the initial test task block.

the initial states of the memory bandwidth. In accordance with KT4, the feedback switch 3 sets the law of formation of the SRP in each basic shift register 50.1-50.4. The recording resolution signals ZP1-ZP4, coming from the mode switch 6 through the second group of inputs to the base shift registers 50.1-50.4, record the initial states of the memory bandwidth from block J through the first group of inputs to the shift registers 50.1-50.4 selected by KTZ. Then, using readout signals СЧ1-СЧ4, coming from the mode switch 6 through the second group of inputs to the basic shift registers 50.1-50.4, test influences are read from the registers 50.1-50.4, which through the output group arrive at the monitored object 10. According to the information shift signals SI1-SI4, Coming from the shift switch 5 through the second group of inputs and the basic shift registers 50.1-50.4, shifts the information in the registers 50.1-50.4 with the frequency specified by КТ2.

Claims (2)

Invention Formula I. A device for generating test actions, containing a control unit and a shift register, the output shift register group being connected to the control object input group, characterized in that, in order to expand the functionality of the device due to the formation of test sequences with different properties, initial tests job unit, feedback switch, communication switch, shift switch and switch 20 25 thirty 35 40 45 50 55 the outputs of the decoder are connected to the inputs of the respective switches, the outputs of the first, second, third and fourth switches are connected to the information inputs of the feedback switch, the communication switch, shift switch and mode switch, respectively, the outputs of the fifth and sixth switches are connected to the information input of the shift register and the first input of the control unit, respectively, the switch output of the initial test task unit is connected to the second input of the control unit, the first output of which is Connected to the first input of the initial test task unit, the second input of which is the input of the initial installation of the device, the second input of the control unit is connected to the control inputs of feedback switches, shear and mode connections, information inputs and outputs of feedback switches and links combined and connected to the shift register input / output, the shift and mode switch outputs are connected to the enabled shift register shift input, the third input of the control unit is the device start input. 2. The device according to claim 1, of which is that the control unit comprises first and second decoders, six delay elements, an OR element, a cycle counter, a clock pulse generator, and three frequency dividers, with the outputs of the first, second , the third, fourth, and - fifth delay elements; the first, second, third frequency dividers and the clock generator form the second output of the block, the first and second inputs of which are connected respectively to the input of the first decrypt five 0 five 0 five 0 five the outputs of the decoder are connected to the inputs of the respective switches, the outputs of the first, second, third and fourth switches are connected to the information inputs of the feedback switch, the communication switch, shift switch and mode switch, respectively, the outputs of the fifth and sixth switches are connected to the information input of the shift register and the first input of the control unit, respectively, the switch output of the initial test task unit is connected to the second input of the control unit, the first output of which is Connected to the first input of the initial test task unit, the second input of which is the input of the initial installation of the device, the second input of the control unit is connected to the control inputs of feedback switches, shear and mode connections, information inputs and outputs of feedback switches and links combined and connected to the shift register input / output, the shift and mode switch outputs are connected to the enabled shift register shift input, the third input of the control unit is the device start input. 2. The device according to claim 1, of which is that the control unit comprises first and second decoders, six delay elements, an OR element, a cycle counter, a clock pulse generator, and three frequency dividers, with the outputs of the first, second , third, fourth and fifth delay elements, first, second, third frequency dividers and a clock generator form the second output of the block, the first and second inputs of which are connected respectively to the input of the first decoder and the information input of the cycle counter, the first input the column is connected to the input of the first delay element and the first input of the OR element, the second input of which is connected to the third input of the block and to the input of the second delay element, the second output of the first decoder is connected to the input of the third delay element and the third input of the OR element, the fourth input of which is connected with the input of the fourth delay element and with the third output of the first decoder, the fourth output of which is connected to the fifth input of the OR element and to the input of the sixth delay element whose output is connected to the input and KKTJ From if l Khtf P G7 fOWi NP 1 "U OmSti write counter, the output of which is connected to the input of the second decoder, the output of which is connected to the start input of the clock generator, the stop input of which is connected to the fifth output of the first decoder, the sixth output of which is connected to the input of the fifth delay element and the sixth input of the OR element, the output of which is the first output of the block, the output of the clock generator is connected to the subtractive input of the cycle counter and to the input of the first frequency divider, the output of which is connected to the input of the second divider part Ota, the output of which is connected to the input of the third frequency divider. ,, S, B KSiil Xvl1 mx L5.7 Mffi zlnas zigzag ztt fin KM xfn J i // IS TO/ Hits CM c vS I i GU n6l2 7 NOL.2 t and 5l 10  from 5 l. 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