JPS5577095A - Ccd memory unit - Google Patents

Ccd memory unit

Info

Publication number
JPS5577095A
JPS5577095A JP14994178A JP14994178A JPS5577095A JP S5577095 A JPS5577095 A JP S5577095A JP 14994178 A JP14994178 A JP 14994178A JP 14994178 A JP14994178 A JP 14994178A JP S5577095 A JPS5577095 A JP S5577095A
Authority
JP
Japan
Prior art keywords
clocks
φce
clock signal
generating circuit
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14994178A
Other languages
Japanese (ja)
Other versions
JPS6043593B2 (en
Inventor
Fumiaki Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53149941A priority Critical patent/JPS6043593B2/en
Publication of JPS5577095A publication Critical patent/JPS5577095A/en
Publication of JPS6043593B2 publication Critical patent/JPS6043593B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the number of clocks of a CCD memory by internally forming a chip enable signal of one transfer clock.
CONSTITUTION: On receiving input signals from prior states, generating circuits 1W 4 generate signals (ϕC1), (-ϕC1), (ϕCE1), and (-ϕCE1). By receiving the output of circuit 1, generating circuit 5 outputs clock signal (ϕ1) whose level becomes high for a certain time from its rise, and similarly generating circuit 6 outputs clock signal (ϕ2). This two-phase signal is used as a transfer clock signal. Output (ϕCE1) of generating circuit 3 exercises control over address-taking-in, data reading and writing operations. In this way, CCD transfer clocks and CE clocks and CE clocks can be reduced to only one in all, and the designing of package can therefore be simplified.
COPYRIGHT: (C)1980,JPO&Japio
JP53149941A 1978-12-06 1978-12-06 memory device Expired JPS6043593B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53149941A JPS6043593B2 (en) 1978-12-06 1978-12-06 memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53149941A JPS6043593B2 (en) 1978-12-06 1978-12-06 memory device

Publications (2)

Publication Number Publication Date
JPS5577095A true JPS5577095A (en) 1980-06-10
JPS6043593B2 JPS6043593B2 (en) 1985-09-28

Family

ID=15485907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53149941A Expired JPS6043593B2 (en) 1978-12-06 1978-12-06 memory device

Country Status (1)

Country Link
JP (1) JPS6043593B2 (en)

Also Published As

Publication number Publication date
JPS6043593B2 (en) 1985-09-28

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