JPS5793434A - Serial port system - Google Patents

Serial port system

Info

Publication number
JPS5793434A
JPS5793434A JP55169272A JP16927280A JPS5793434A JP S5793434 A JPS5793434 A JP S5793434A JP 55169272 A JP55169272 A JP 55169272A JP 16927280 A JP16927280 A JP 16927280A JP S5793434 A JPS5793434 A JP S5793434A
Authority
JP
Japan
Prior art keywords
circuit
data
clock
serial
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55169272A
Other languages
Japanese (ja)
Other versions
JPS6017139B2 (en
Inventor
Masaharu Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55169272A priority Critical patent/JPS6017139B2/en
Publication of JPS5793434A publication Critical patent/JPS5793434A/en
Publication of JPS6017139B2 publication Critical patent/JPS6017139B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To make input and output surely without error between the external circuits and the circuit using a serial port system of dynamic type which makes input and output of serial data between said circuit and the external circuit and provides shift registers of a plurality of bits and transfers data with a shift clock. CONSTITUTION:A serial input latch circuit ILA which fetches data at the leading edge of a serial data clock SC given from external circuits and a serial output latch circuit OLA which fetches and transmits the trailing data are connected among n-bit shift registers SR1-SRn, an input terminal Si and an output terminal. SC, and the data of an FF1 of bit SRn in which the trailing edge of the clock SC is given to the output latch circuit OLA via an inverter INV at time t1 is fetched to the circuit OLA, and the data of the external circuit OLA given to an input latch circuit ILA at the leading of the clock SC at the next tme t2 is received via the input terminal Si and latched to the circuit ILA. A shift clock generating section 500 generates shift clocks S1, S2 with the clock SC.
JP55169272A 1980-12-01 1980-12-01 Serial port method Expired JPS6017139B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55169272A JPS6017139B2 (en) 1980-12-01 1980-12-01 Serial port method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55169272A JPS6017139B2 (en) 1980-12-01 1980-12-01 Serial port method

Publications (2)

Publication Number Publication Date
JPS5793434A true JPS5793434A (en) 1982-06-10
JPS6017139B2 JPS6017139B2 (en) 1985-05-01

Family

ID=15883425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55169272A Expired JPS6017139B2 (en) 1980-12-01 1980-12-01 Serial port method

Country Status (1)

Country Link
JP (1) JPS6017139B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019272A (en) * 1983-07-12 1985-01-31 Seiko Epson Corp Data input circuit of microprocessor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019272A (en) * 1983-07-12 1985-01-31 Seiko Epson Corp Data input circuit of microprocessor

Also Published As

Publication number Publication date
JPS6017139B2 (en) 1985-05-01

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