SU1596320A1 - N-input adder - Google Patents

Abstract

The invention relates to computing and is intended for use in multi-pipeline digital signal processing systems. The purpose of the invention is to expand the functionality of the device by summing the groups of operands. Conveyor N-input adder contains inputs 1 1, ..., 1 N, summing cells 2, outputs 3, outputs 4 cells, bus 5 synchronization and bus 6 installation in "O". Cell 2 contains an alarm combination combiner and trigger. 2 ill., 1 tab.

Description

SP

with

I.

ate yu

0s 00 N5 O

The invention relates to computing and is intended for use in multi-pipeline digital signal processing systems.

The purpose of the invention is to expand the functionality of the device by implementing the summation of groups of operands.

FIG. 1 shows a p-input adder circuit; in fig. 2 is a diagram of a summing cell.

p-Input adder contains inputs 1i - In, summing cells 2, additional outputs 3, first outputs 4 cells, synchronization bus 5 and installation bus 6 in O,

Cell 2 (Fig. 2) is formed by a three-input combination adder 7 and triggers 8 and 9.

In the static state, after the 1st clock cycle, the (1 + 1) th bits of the added numbers are at the inputs 1–1, the outputs of 3 flip-flops 9 cells 2 — i.e., the bits of the corresponding amounts, at the inputs of the flip-flops 8 - the values of hyphens in The (1 + 1) th bits of the corresponding amounts.

p-input adder works as follows.

First, a pulse is fed through the bus 6 of the installation to O. At the inputs 1i-In, the younger bits advance the numbers, and the change of each bit occurs along the leading edge of the clock pulse, which is fed through the synchronization bus 5, is written to the corresponding triggers 8 and 9 information from the outputs of the combinational adder 7. After the pulse is transmitted through the bus 6 of the installation to the O, all the triggers are set to the zero state. After the first sync pulse, the first (lower) bit values of the corresponding amounts appearing at their outputs 3 are written into triggers 9, and the corresponding transfer values are written into the triggers 8, and after the second sync pulse at the outputs 4, the corresponding values of the second bit appear etc. Maximum number of pulses required to obtain all bits

sums of n numbers: T m + 1od2P + 1, where m is the digit length of numbers.

If it is required to determine only the sums of pairs of numbers, then t + 2 clock cycles will suffice, then the process proceeds in a similar way.

Consider the example of the work of the n-input adder. Suppose you want to add the numbers 0101, 1011, 0111, 1010 (). The sequence of states of the inputs of the triggers 8 and the outputs 3 after each clock cycle in the process of summation will be represented in the form of a table.

Claims (1)

Claims p-Input adder containing p-1 summing cells forming logan lines, each summing cell comprises trehvhodovy combinational adder and transfer the storage flip-flop, whose input is connected to the transfer output, and an output - a transfer input trehvhodovogo Raman adder of the same adder cell data inputs trehvhodovogo Raman adder are connected to inputs, and output sums - with the first output of the corresponding summing cell, the inputs of the summing cells of the first line are connected to the inputs of the p-input adder, taken in pairs, the inputs of the summing cells of each the rulers, starting with the second, are connected to the first outputs of the summing cells of the previous line, taken in pairs, the first output of the summing cell of the last line is connected to the output of the n-input adder, characterized in that, in order to expand functionality by implementing the summation of a group of operands, a trigger is entered into each sum cell; which is connected to the output of the sum of the three-input combinational adder, and the output to the second output of the corresponding summing cell, the second outputs of all summing cells are additional outputs of the p-input adder. 4- J FIG. 2