JPS648723A - Logic device - Google Patents

Logic device

Info

Publication number
JPS648723A
JPS648723A JP16433387A JP16433387A JPS648723A JP S648723 A JPS648723 A JP S648723A JP 16433387 A JP16433387 A JP 16433387A JP 16433387 A JP16433387 A JP 16433387A JP S648723 A JPS648723 A JP S648723A
Authority
JP
Japan
Prior art keywords
array
signal
level
pla
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16433387A
Other languages
Japanese (ja)
Inventor
Shunichi Iwata
Masahito Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16433387A priority Critical patent/JPS648723A/en
Publication of JPS648723A publication Critical patent/JPS648723A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To simplify the circuit to select a circuit means by providing a selecting means to make only the output signal of the circuit means effective between two groups of logic circuit means. CONSTITUTION:In selecting a programmable logic array PLA of the side A, the level of a select signal A is at logical 1 and a signal B is at logical 0. In giving the input signal A to an AND array A1 in the PLA at the side A, since the level of the signal A is logical; 1, a clock phi2 goes to 1 and transmission gates Ga1-GaL are opened, then the level of bit lines Ba1-BaL is inputted to word lines Wa1-WaL of an OR array C3 as it is. In giving the input signal B to an AND array B2 at the PLA of the side B, since the signal B is 0, bit lines Bb1-BbM are all discharged at the leading of the clock phi2 and the level is 0. Thus, the logic is generated by the input only from the array A1 in the array C3 and outputted from output lines O1-ON.
JP16433387A 1987-06-30 1987-06-30 Logic device Pending JPS648723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16433387A JPS648723A (en) 1987-06-30 1987-06-30 Logic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16433387A JPS648723A (en) 1987-06-30 1987-06-30 Logic device

Publications (1)

Publication Number Publication Date
JPS648723A true JPS648723A (en) 1989-01-12

Family

ID=15791179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16433387A Pending JPS648723A (en) 1987-06-30 1987-06-30 Logic device

Country Status (1)

Country Link
JP (1) JPS648723A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0379071A2 (en) * 1989-01-19 1990-07-25 National Semiconductor Corporation Multiple page programmable logic architecture
JPH0788057A (en) * 1993-09-24 1995-04-04 Dia Gomme Kk Cooking two-layer gloves

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60229424A (en) * 1984-04-26 1985-11-14 Nec Corp Field programmable logic array
JPS60229425A (en) * 1984-04-26 1985-11-14 Nec Corp Programmable logic array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60229424A (en) * 1984-04-26 1985-11-14 Nec Corp Field programmable logic array
JPS60229425A (en) * 1984-04-26 1985-11-14 Nec Corp Programmable logic array

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0379071A2 (en) * 1989-01-19 1990-07-25 National Semiconductor Corporation Multiple page programmable logic architecture
EP0379071A3 (en) * 1989-01-19 1990-10-31 National Semiconductor Corporation Multiple page programmable logic architecture
JPH0788057A (en) * 1993-09-24 1995-04-04 Dia Gomme Kk Cooking two-layer gloves

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