JPS60229424A - Field programmable logic array - Google Patents

Field programmable logic array

Info

Publication number
JPS60229424A
JPS60229424A JP59084426A JP8442684A JPS60229424A JP S60229424 A JPS60229424 A JP S60229424A JP 59084426 A JP59084426 A JP 59084426A JP 8442684 A JP8442684 A JP 8442684A JP S60229424 A JPS60229424 A JP S60229424A
Authority
JP
Japan
Prior art keywords
area
logical circuit
product term
programmed
field programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59084426A
Other languages
Japanese (ja)
Inventor
Yutaka Takahashi
裕 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59084426A priority Critical patent/JPS60229424A/en
Publication of JPS60229424A publication Critical patent/JPS60229424A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To attain programming of another independent logical circuit to an area not in use when a logical circuit having a low gate operating rate is programmed by dividing an area of a product term line into plural numbers. CONSTITUTION:In dividing an area of a field programmable logic array (FPLA) into two, the product term 4 is divided into areas (a), (b) and the product term line of each area is connected to collectors of area selecting transistors (TRs) (c), (c)... and (d), (d).... Emitter of the TRs (c), (d) are grounded and bases are connected to area selection signals (e), (f). If a desired logical circuit is not realized by the area (a) only, the area selection signals (e), (f) are brought into logical ''1'' so as to use the area a, b selectively. When the desired logical circuit is realized by the area (a) only, only the area (a) is programmed. Another logical circuit is programmed to the area (b) not in use and the area (a) or (b) is used selectively by the area selection signals (e), (f). In using the areas (a), (b) dividedly, the signals (e), (f) are clamped into logical ''0'' or ''1'' so as to realize the logical circuit having the other function.

Description

【発明の詳細な説明】 〔発明の属する技術分野の説明〕 本発明は領域分割可能なフィールド・プログラマブル・
ロジック・アレイ（以下ＦＰＬＡという）に関する。[Detailed description of the invention] [Description of the technical field to which the invention pertains] The present invention provides a field programmable
It relates to logic arrays (hereinafter referred to as FPLA).

〔従来技術の説明〕[Description of prior art]

第１図に示すようにＦＰＬＡはプログラム可能な閥アレ
イ１，１・・及びＯＲアレイ２，２・・から構成され、
未プログラムの状態ではＮのアレイ入力線３．３　と積
項線４，４・との交点及び積項線４．４・とＯＲアレイ
出力線５，５・・・との交点は開放状態であり、プログ
ラムにより必要な交点を通常ダイオードＤで短絡状態に
して所望の論理回路を短時間に実現するものである、６
は電源に接続する電力線である。As shown in FIG. 1, the FPLA is composed of programmable group arrays 1, 1,... and OR arrays 2, 2,...
In the unprogrammed state, the intersections between the N array input line 3.3 and the product term lines 4, 4, and the intersections between the product term line 4.4 and the OR array output lines 5, 5, etc. are open. Yes, the desired logic circuit can be realized in a short time by short-circuiting the necessary intersection points with a diode D according to the program.6
is the power line that connects to the power source.

このようにＦＰＬＡはアレイサイズ、すなわち入力線数
、出力線数及び積項線数があらかじめ定まっており、ゲ
ートアレイのように入力端子数及び出力端子数も任意に
できるような自由度がない。As described above, in the FPLA, the array size, that is, the number of input lines, the number of output lines, and the number of product term lines are determined in advance, and unlike a gate array, there is no degree of freedom in which the number of input terminals and the number of output terminals can be arbitrarily determined.

このため、論理回路の種類によっては、ゲートすなわち
交点の使用率が低くなるという欠点を有する。また、ア
レイサイズが大きくなる程、ゲート使用率は低くなると
いう傾向がある。Therefore, depending on the type of logic circuit, there is a drawback that the usage rate of gates, that is, intersections is low. Furthermore, there is a tendency that the larger the array size, the lower the gate usage rate.

〔発明の詳細な説明〕[Detailed description of the invention]

本発明の目的は、積項線の領域を複数に分割できるよう
にすることにより、ゲート使用率の低い論理回路をプロ
グラムした場合に未使用の領域に独立した別の論理回路
をプログラムできるＦＰＬＡを提供することにある。An object of the present invention is to create an FPLA in which an independent logic circuit can be programmed into an unused area when a logic circuit with a low gate usage rate is programmed by making it possible to divide the area of the product term line into multiple areas. It is about providing.

〔発明の構成〕[Structure of the invention]

本発明は、農大力線、積項線及びＯＲ出方線よりなるＦ
ＰＬＡにおいて、積項線の領域を複数に分割し、各領域
を領域選択信号により選択させるゲート手段を有するこ
とを特徴とするフィールド・プログラマブル・ロジック
・アレイである。The present invention is based on the F
This is a field programmable logic array in a PLA, which is characterized by having gate means that divides a region of a product term line into a plurality of regions and selects each region by a region selection signal.

〔実施例の説明〕[Explanation of Examples]

次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

第２図はＦＰＬＡの領域を２分割した場合の本発明の実
施例を示すものであり、積項線４は領域ａ及び領域すに
分割され、各領域の積項線は領域選択トランジスタＣ，
Ｃ・・・及びｄ、ｄ・・・のコレクタに接続されている
。各トランジスタＣ及びｄのエミッタは接地され、また
ベースは領域選択信号ｅ及びｆＫ接続される。FIG. 2 shows an embodiment of the present invention in which the region of the FPLA is divided into two, where the product term line 4 is divided into region a and region A, and the product term line of each region is divided into region selection transistors C,
It is connected to the collectors of C... and d, d.... The emitters of each transistor C and d are grounded, and the bases are connected to area selection signals e and fK.

次に本実施例の動作について説明する、所望の論理回路
が領域αだけで実現できない場合は領域選択信号ｅ及び
ｆを論理ゝ１“にして２つの領域α及びｂを選択して使
用する。Next, the operation of this embodiment will be explained. If a desired logic circuit cannot be realized only in area α, area selection signals e and f are set to logic "1" to select and use two areas α and b.

また、所望の論理回路が領域αだけで実現できる場合は
、その領域αのみにプログラムする。未使用領域すは別
の論理回路をプログラムしておき、領域選択信号ｅ及び
ｆにより領域α又はｂを選択して使用する。Furthermore, if a desired logic circuit can be realized only in area α, programming is performed only in that area α. A separate logic circuit is programmed for the unused area, and area α or b is selected and used by area selection signals e and f.

次に本実施例の効果について説明する。Next, the effects of this embodiment will be explained.

領域α及びｂを分割して使用した場合は信号ｅ。When areas α and b are divided and used, signal e is obtained.

ｆを論理ｖＸＯＩ又はゝ１“にクランプすることによっ
て別の機能を持った論理回路を実現できる。また信号ｅ
、ｆにダイナツクな信号を与えて領域α又はｂを時分割
して使用することもできる。By clamping f to the logic vXOI or "1", a logic circuit with another function can be realized.Also, the signal e
, f can be given dynamic signals to use the area α or b in a time-division manner.

さらに、一方の領域すにはプログラムせず、領域αのプ
ログラムを誤った場合や使用中に交点が不良になった場
合（未プログラム交点の短絡、プログラム交点の開放）
、領域αの論理回路を変更する場合にプログラムできる
領域としてとっておくこともできる。Furthermore, if one area is not programmed and the programming of area α is incorrect, or if the intersection becomes defective during use (short circuit of unprogrammed intersection, open of programmed intersection)
, it can also be set aside as a programmable area when changing the logic circuit in area α.

〔発明の詳細な説明〕[Detailed description of the invention]

本発明は、以上説明したように、ＦＰＬＡの領域を分割
できるよう構成すること、によシ、ゲート使用率の低い
複数の論理回路を単一のＦＰＬＡで実現できるという効
果がある。As explained above, the present invention is advantageous in that it is possible to realize a plurality of logic circuits with a low gate usage rate in a single FPLA by configuring the FPLA so that its area can be divided.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のＦＰＬＡの構成を示す回路図、第２図は
本発明の実施例を示す回路図である。 １・・・翫アレイ、２・・・ＯＲアレイ、３・・・に０
アレイ入力線、４・・・積項線、５・・・ＯＲアレイ出
力線、α、ｂ・・・分割された領域、ｃ、ｄ・・・領域
選択トランジスタ、ｅ、ｆ・・・領域選択信号 特許出願人　日本電気株式会社FIG. 1 is a circuit diagram showing the configuration of a conventional FPLA, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1...Kan array, 2...OR array, 3...0 to
Array input line, 4... Product term line, 5... OR array output line, α, b... Divided area, c, d... Area selection transistor, e, f... Area selection Signal patent applicant NEC Corporation

Claims (1)

【特許請求の範囲】[Claims] （１）ＡＮＤ入力線、積項線及びＯＲ出力線よりなるフ
ィールド・プログラマブル・ロジック・アレイにおいて
、前記積項線の領域を複数に分割し、各領域を領域選択
信号により選択させるゲート手段を有することを特徴と
するフィールド・プログラマブル・ロジック・アレイ。(1) A field programmable logic array consisting of an AND input line, a product term line, and an OR output line, including gate means that divides the area of the product term line into a plurality of areas and selects each area by an area selection signal. A field programmable logic array characterized by:
JP59084426A 1984-04-26 1984-04-26 Field programmable logic array Pending JPS60229424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59084426A JPS60229424A (en) 1984-04-26 1984-04-26 Field programmable logic array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59084426A JPS60229424A (en) 1984-04-26 1984-04-26 Field programmable logic array

Publications (1)

Publication Number Publication Date
JPS60229424A true JPS60229424A (en) 1985-11-14

Family

ID=13830254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59084426A Pending JPS60229424A (en) 1984-04-26 1984-04-26 Field programmable logic array

Country Status (1)

Country Link
JP (1) JPS60229424A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS648723A (en) * 1987-06-30 1989-01-12 Mitsubishi Electric Corp Logic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS648723A (en) * 1987-06-30 1989-01-12 Mitsubishi Electric Corp Logic device

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