JPS5778213A - Timing generating circuit - Google Patents

Timing generating circuit

Info

Publication number
JPS5778213A
JPS5778213A JP55153104A JP15310480A JPS5778213A JP S5778213 A JPS5778213 A JP S5778213A JP 55153104 A JP55153104 A JP 55153104A JP 15310480 A JP15310480 A JP 15310480A JP S5778213 A JPS5778213 A JP S5778213A
Authority
JP
Japan
Prior art keywords
circuit
clocks
generated
start signal
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55153104A
Other languages
Japanese (ja)
Inventor
Koichi Aida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55153104A priority Critical patent/JPS5778213A/en
Publication of JPS5778213A publication Critical patent/JPS5778213A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain a circuit adapted to an LSI which is used in both modes, by constituting the delay circuit by logical gates and by operating this circuit by either of an internal clock generated by a start signal and an external clock having a time relation to the start signal. CONSTITUTION:Internal clocks CSET1 and CTMF1 are selected when a signal line CLSEL is 0, and an external clock MCLK is selected when the CLSEL is 1. An internal clock CSET0 is generated by a start signal, and the clock outputted from an AND circuit 40 is transmitted while being delayed by inverters 20-25, and delay clocks having a prescribed time relation are generated from outut taps CTM0- CTM7. An FF44 is set by the CSET0, and FFs 45-48 are operated to generate timing gate signals CET0-CET4. A timing signal of a desired delay time is obtained by AND of desired combinations between clocks CTM0-CTM7 and signals CET0- CET4.
JP55153104A 1980-10-31 1980-10-31 Timing generating circuit Pending JPS5778213A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55153104A JPS5778213A (en) 1980-10-31 1980-10-31 Timing generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55153104A JPS5778213A (en) 1980-10-31 1980-10-31 Timing generating circuit

Publications (1)

Publication Number Publication Date
JPS5778213A true JPS5778213A (en) 1982-05-15

Family

ID=15555054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55153104A Pending JPS5778213A (en) 1980-10-31 1980-10-31 Timing generating circuit

Country Status (1)

Country Link
JP (1) JPS5778213A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5159365A (en) * 1974-11-19 1976-05-24 Ibm Fet fukageetohoshosochi
JPS51149761A (en) * 1975-06-07 1976-12-22 Nec Corp Delay pulse generating circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5159365A (en) * 1974-11-19 1976-05-24 Ibm Fet fukageetohoshosochi
JPS51149761A (en) * 1975-06-07 1976-12-22 Nec Corp Delay pulse generating circuit

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