JPS6437114A - D flip flop circuit with set/reset function - Google Patents

D flip flop circuit with set/reset function

Info

Publication number
JPS6437114A
JPS6437114A JP62193948A JP19394887A JPS6437114A JP S6437114 A JPS6437114 A JP S6437114A JP 62193948 A JP62193948 A JP 62193948A JP 19394887 A JP19394887 A JP 19394887A JP S6437114 A JPS6437114 A JP S6437114A
Authority
JP
Japan
Prior art keywords
pull
trs
reset
inverters
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62193948A
Other languages
Japanese (ja)
Other versions
JPH0666659B2 (en
Inventor
Eiji Ikuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62193948A priority Critical patent/JPH0666659B2/en
Publication of JPS6437114A publication Critical patent/JPS6437114A/en
Publication of JPH0666659B2 publication Critical patent/JPH0666659B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Dram (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To increase the operation speed by combining clock inverters and pull-up and pull-down transistors TRs to provide a feedback inverter. CONSTITUTION:Clock inverters C11 and C12 are turned off at the time of set/ reset, and pull-up TRs P1 and P2 and pull-down TRs N1 and N2 are provided and a master part and a slave part are forcibly set or reset to transmit the input to the output. By the use of an edge triggered FF, a high-speed clock is used to transfer the input to the output. The master-slave system is adopted to eliminate the noise superposed on the input signal. Thus, the operation is quickly performed though set/reset functions are added, and the operation is quickly performed even in the set/reset state because it is sufficient if the input signal is delayed by one stage of TRs and one stage of inverters.
JP62193948A 1987-08-03 1987-08-03 D flip-flop circuit with set / reset Expired - Lifetime JPH0666659B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62193948A JPH0666659B2 (en) 1987-08-03 1987-08-03 D flip-flop circuit with set / reset

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62193948A JPH0666659B2 (en) 1987-08-03 1987-08-03 D flip-flop circuit with set / reset

Publications (2)

Publication Number Publication Date
JPS6437114A true JPS6437114A (en) 1989-02-07
JPH0666659B2 JPH0666659B2 (en) 1994-08-24

Family

ID=16316421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62193948A Expired - Lifetime JPH0666659B2 (en) 1987-08-03 1987-08-03 D flip-flop circuit with set / reset

Country Status (1)

Country Link
JP (1) JPH0666659B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5905393A (en) * 1997-10-06 1999-05-18 Motorola, Inc. Unbuffered latch resistant to back-writing and method of operation therefor
WO2000031871A1 (en) * 1998-11-25 2000-06-02 Nanopower, Inc. Improved flip-flops and other logic circuits and techniques for improving layouts of integrated circuits

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61290814A (en) * 1985-06-18 1986-12-20 Sharp Corp D-type flip-flop
JPS62117410A (en) * 1985-11-16 1987-05-28 Sharp Corp Flip flop

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61290814A (en) * 1985-06-18 1986-12-20 Sharp Corp D-type flip-flop
JPS62117410A (en) * 1985-11-16 1987-05-28 Sharp Corp Flip flop

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5905393A (en) * 1997-10-06 1999-05-18 Motorola, Inc. Unbuffered latch resistant to back-writing and method of operation therefor
WO2000031871A1 (en) * 1998-11-25 2000-06-02 Nanopower, Inc. Improved flip-flops and other logic circuits and techniques for improving layouts of integrated circuits
US6198324B1 (en) * 1998-11-25 2001-03-06 Nanopower Technologies, Inc. Flip flops
US6252448B1 (en) 1998-11-25 2001-06-26 Nanopower Technologies, Inc. Coincident complementary clock generator for logic circuits
US6297668B1 (en) 1998-11-25 2001-10-02 Manopower Technologies, Inc. Serial device compaction for improving integrated circuit layouts
US6333656B1 (en) 1998-11-25 2001-12-25 Nanopower Technologies, Inc. Flip-flops

Also Published As

Publication number Publication date
JPH0666659B2 (en) 1994-08-24

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term