JPS57210412A - Muting system of pcm recording and reproducing apparatus - Google Patents
Muting system of pcm recording and reproducing apparatusInfo
- Publication number
- JPS57210412A JPS57210412A JP9403181A JP9403181A JPS57210412A JP S57210412 A JPS57210412 A JP S57210412A JP 9403181 A JP9403181 A JP 9403181A JP 9403181 A JP9403181 A JP 9403181A JP S57210412 A JPS57210412 A JP S57210412A
- Authority
- JP
- Japan
- Prior art keywords
- supplied
- muting
- gates
- gate
- pcm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/22—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing distortions
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Noise Elimination (AREA)
Abstract
PURPOSE:To simplify constitution and to reduce cost, by using the change point of a polarity bit as a trigger for muting. CONSTITUTION:A PCM signal processing circuit 20 supplies a PCM data signal and a latch signal to a latch circuit 21. An EX-OR gate 25 exclusively ORs data on a polarity bit having tow-clock delay with original polarity bit data. The output pulse of the gate 25 is supplied to AND gates 26 and 27. The AND gates 26 and 27 are supplied with an LIR switching pulse from a PCM signal processing circuit 20. The outputs of the AND gates 26 and 27 are supplied as clock input signals to L and R channel muting flip-flops 29 and 210, whose outputs are supplied as a clear signal to the latch circuit 21 through an NOR gate 211. The instruction for muting is permitted by closing a switch 212.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9403181A JPS57210412A (en) | 1981-06-19 | 1981-06-19 | Muting system of pcm recording and reproducing apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9403181A JPS57210412A (en) | 1981-06-19 | 1981-06-19 | Muting system of pcm recording and reproducing apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57210412A true JPS57210412A (en) | 1982-12-24 |
JPS6367267B2 JPS6367267B2 (en) | 1988-12-23 |
Family
ID=14099186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9403181A Granted JPS57210412A (en) | 1981-06-19 | 1981-06-19 | Muting system of pcm recording and reproducing apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57210412A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6066365A (en) * | 1983-09-21 | 1985-04-16 | Sony Corp | Muting circuit |
-
1981
- 1981-06-19 JP JP9403181A patent/JPS57210412A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6066365A (en) * | 1983-09-21 | 1985-04-16 | Sony Corp | Muting circuit |
JPH057789B2 (en) * | 1983-09-21 | 1993-01-29 | Sony Corp |
Also Published As
Publication number | Publication date |
---|---|
JPS6367267B2 (en) | 1988-12-23 |
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