JPH0588578B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a clock regeneration method for synchronizing digital signals.

[Background of the invention]

Conventional data synchronization circuits, as described in Japanese Unexamined Patent Publication No. 58-56212, synchronize at edges when the edges of a digital signal are at predetermined intervals.

There is no problem when detecting a falling edge 4 of a digital signal 3 obtained by slicing an ideal signal 1 at a slice level 2 as shown in FIG.

However, in the digital signal 7 obtained by slicing the noise-containing signal 5 at the slice level 6 as shown in FIG. 3, a short pulse appears near where the signal 5 crosses the slice level 6. If a digital signal containing such short pulses is input to a conventional data synchronization circuit, the number of edges detected by the edge detection circuit will increase compared to when the ideal signal shown in Figure 2 is input. It's obvious. If edge intervals are counted while including edges of pulses caused by such noise, edges at a predetermined interval may become difficult to detect, resulting in longer data synchronization intervals, or edges caused by noise may become more difficult to detect than edges at a predetermined interval. There was a problem with false detection.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art by eliminating short pulses that are noise in the input signal, thereby achieving synchronization only with edges at intervals allowed by the format, and achieving data synchronization. The goal is to eliminate disturbances and reproduce a stable clock.

[Summary of the invention]

In order to achieve the above object, the present invention detects the edges of an input digital signal, counts the length of the interval between edges, removes short pulses, and synchronizes data with the removed signal. It is.

In other words, when considering the noise level of a signal before converting it to a digital signal, its C/N is usually 30 dB to 40 dB, so as shown in Figure 3, the noise level near where the signal crosses the slice level is Noise appears in digital signals as short pulses.

In the present invention, in order to eliminate the influence of this short pulse, by detecting the edges of the input digital signal and counting the length of the interval between edges,
Remove short pulses and synchronize data to the removed signal.

[Embodiments of the invention]

The present invention will be explained in detail using a specific example. FIG. 1 shows the configuration of a data synchronization circuit including the present invention.

The first edge detection circuit 12 detects the digital signal 1
1 as input, edge signal 13 and edge signal 1
If the signal 3 is a rising edge, a discrimination signal 14 is output, which is "H", and if it is a falling edge, it is "L". The first counting circuit 16 is reset by the edge signal 13, counts the signal 15 except during this reset period, and outputs the signal 17 after a certain period of time has elapsed after being reset. AND
The gate 22 outputs the set signal 23 by ANDing the discrimination signal 14 and the signal 17, and the AND gate 20 outputs the set signal 23 as follows.
A reset signal 21 is generated by a signal 19 obtained by inverting the discrimination signal 14 by an inverter 18 and a signal 17, respectively. The flip-flop 24 is set to "H" by the reset signal 21, set to "L" by the reset signal 23, and outputs a signal 25.

The second edge detection circuit 26 detects the rising edge of the output signal 25 of the flip-flop 24 and outputs an edge signal 27. Second counting circuit 29
is reset by the edge signal 27, counts the signal 28 except during this reset period, and outputs a predetermined count value signal 30 after being reset. AND gate 3
1 outputs an AND signal 32 of the edge signal 27 and the count signal 30. Start-stop data synchronization circuit 3
4 is reset by the signal 32, the signal 33 is counted until the next reset, and a unique count value signal 35 is output.

Next, a more detailed explanation will be given with reference to the time chart shown in FIG.

In this example, the time 39 of the input digital signal 11,
“L” level pulse in time 40 interval and
The "H" level pulse in the time 43 and time 44 intervals, and the "H" level pulse in the time 49 and time 50 intervals are the pulses that should be removed, respectively, and the signal 11 originally had a length of 1 bit. Let T be a 2T repetitive signal.
Furthermore, in this example, signal 15, signal 28, signal 33
is a signal whose period is one-eighth of the length T of one bit of the signal 11.

A signal obtained by delaying the signal 11 by, for example, time 36 from the edge signal 13 detected at time 37 is set as the discrimination signal 14. Further, the count value of the first counting circuit 16 is selected so that the signal 17 is output when a time period 36 has elapsed after the first counting circuit 16 is reset by the edge signal 13. The length of this time 36 determines the length of the pulse that is removed. Further, in this example, the time 36 is set to 2/8 of the length T of one bit of the signal 11.

At time 38, the discrimination signal 14 is "H" and the signal 17 is being output, so the set signal 23 is output and the output 25 of the flip-flop circuit 24 is set to "H". Next, the first counting circuit 16 is reset by the edge signal 13 detected at time 39, but before the length of time 36 has elapsed, the edge signal 13 is further detected at time 40. The signal 17 is output at time 41 when the length of time 36 has elapsed from time 40. At this time,
Since the discrimination signal 14 is at the "H" level with a delay of the signal 11 by the same length of time 36 from time 40, the set signal 23 is output and the output 25 of the flip-flop 24 at time 41 is set to "H". It remains as it is. Therefore, the "L" level at times 39 and 40 does not appear in the signal 25.

Similarly, flip-flop circuit 24 is reset by signal 21 at time 42 and reset at time 45 as a result of the edge signal detected at time 44, but the edge signal detected at time 43 is output to output 25 of flip-flop 24. is not reflected.

Therefore, at the output 25 of the flip-flop 24,
Short width pulses of the input signal 11 are not output.

Next, the second edge detection circuit 26 detects the rising edge signal 27 of the signal 25. The second counting circuit 29 receives the rising edge signal 2 at time 37.
In this example, it is reset at time 46 and time 4.
7. Output the count value signal 30 at time 48. At time 47, since the edge signal 27 is output, the AND signal 32 of the AND gate 22 is output. Since the third counting circuit 34 is reset by the AND signal 32, the count value signal 35 of the asynchronous data synchronization circuit 34 becomes short at time 47 in this example, and after time 47, the signal 33 in this example is shortened. The signal frequency-divided by 8 is output as the count value signal 35, and the signal 1
1 synchronous clock.

In this example, the lengths of the signals 15, 28, and 33 are set to 1/8 of the length T of 1 bit of the input signal 11, but the lengths can be arbitrarily selected. In that case, the frequency division ratios of the second counting circuit and the start-stop data synchronization circuit may be changed.

In addition, in this example, the length of time 36 is set to the length of input signal 11.
The length of 1 bit is set to 2/8 of T, but this length can also be arbitrarily selected.

Further, the edge signal 27 detected by the second edge detection circuit 26 may be one obtained by detecting a falling edge.

FIG. 5 shows a more detailed embodiment of the first edge detection circuit 12, first counting circuit 16, and flip-flop circuit 24.

The input signal 11 is input to the first stage D-FF51, the same output 53 is input to the second stage D-FF52, and the same output 1 is inputted to the second stage D-FF52.
Get 4. Both outputs 53 and 14 are input to an E-OR circuit 54 to obtain an edge signal 13. Here, the width of the edge output 13 is equal to the period of the clock pulse 55 of the D-FFs 51 and 52.

The edge signal 13 resets the first counting circuit 16. The first counting circuit has a D-
It is composed of FF57, but the output 5 of D-FF57
6 is the D input of the D-FF 57, the signal 17 is in the reset period, that is, the edge signal 13.
The output is obtained by dividing the clock pulse signal 15 of the D-FF 57 by two, except for the period in which it is output.

The flip-flop circuit 24 consists of D-FFs 58 and 59 for removing hazards appearing in the outputs of the AND gate circuits 21 and 23, and an R-SFF to which the outputs of the NAND gate circuits 63 and 64 are fed back.

The clock signal 55 of the edge detection circuit 12, the first
A signal 25 is obtained by making the clock signal 15 of the counting circuit 16 and the clock signal 62 of the flip-flop circuit 24 the same signal.

The time chart of FIG. 5 is shown in FIG. 6.

FIG. 7 shows a more detailed embodiment of the second edge detection circuit 26, second counting circuit 29, and start-stop data synchronization circuit 34.

In the second edge detection circuit 26, the signal 25 is
-Input to FF66 and output 67 to next stage D-FF
69 and obtain the same output 70. D-FF66,
65 performs the same operation at the same time with the clock signal 65, and D-
Output 68 of FF66 and Q output 70 of D-FF69
is input to the AND gate circuit 71 to obtain the rising edge signal 27.

The second counting circuit 29 includes D-FF72, J-KFF74, J-KFF75, and J-KFF7 for timing matching.
6, an 8 frequency divider counter clocked by the clock signal 28 consisting of an AND gate circuit 77 and an AND gate circuit 77 which decodes a predetermined count value signal 30;
The gate 81 is configured with a gate 81. Edge signal 27 to D
-Input to FF72, output 73 to J-KFF7
4.Reset 75 and 76. The count signal 30 is output every eight clock signals 28. Further, the count value signal 30 may be selected so as to coincide with the time when the edge signal 27 should be outputted next after the edge signal 27 is outputted once.

An edge signal 27 and a count signal 30 are input to an AND gate 31, and a signal 32 is output only when both inputs match.

Next, the asynchronous data synchronization circuit 34 will be explained.
The D-FF 82 which receives the output signal 32 of the AND gate circuit 31 is used for timing adjustment. J-KFF84, 86, 89
Together with the AND gate 88, a divide-by-8 circuit using the clock signal 33 as a clock is configured. AND gate 91 is a decoder for generating a clock simultaneously with input signal 25, and the decode value can be arbitrarily selected. D-FF93, D-FF97 and OR gate 95 widen the pulse width of AND gate 91 and output signal 35. Signal 35 is input signal 2
The clock is synchronized to 5.

FIG. 8 shows a timing chart showing the operation of FIG. 7.

In this example, when the length of one bit of the input signal 25 is T, the period of the clock pulse of each circuit is T/8, but the period of the clock pulse may be arbitrary. Furthermore, the edge detected by the second edge detection circuit 26 may be a falling edge circuit.

〔Effect of the invention〕

According to the present invention, it is possible to reproduce a clock that is synchronized with the signal after noise in the input digital signal has been removed.
This has the effect of reducing the error rate in determining "H".

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment including the present invention, and FIG.
The figure is an explanatory diagram of an ideal signal and its falling edge detection output, Figure 3 is an explanatory diagram of the falling edge detection output of a signal mixed with noise, and Figure 4 is an explanatory diagram of the falling edge detection output of a signal mixed with noise.
FIG. 5 is a diagram showing a detailed embodiment of the first edge detection circuit, first counting circuit, and flip-flop circuit including the present invention, and FIG. 6 is a timing chart showing the operation. 7 is a diagram showing a detailed embodiment of the second edge detection circuit, second counting circuit, and start-stop data synchronization circuit including the present invention, and FIG. 8 is an operation time chart thereof. be. 12...First edge detection circuit, 16...First counting circuit, 24...Flip-flop circuit, 26...Second edge detection circuit, 29...Second counting circuit, 3
4... Start-stop data synchronization circuit.

Claims (1)

[Claims] 1. In an asynchronous data synchronization circuit that receives a digital signal as input, a first edge detection circuit detects a rising edge of the digital signal, a first edge detection circuit detects a rising edge of the digital signal, and a first edge detection circuit detects a rising edge of the digital signal. a first counting circuit that detects that a certain period of time has elapsed after being reset at the edge;
Only when the second edge detected next to the first edge detected by the edge detection circuit is detected after the certain time period detected by the first counting circuit, the second edge is detected by the first edge detection circuit. A flip-flop circuit whose state changes according to the fall and rise of
A second edge detection circuit detects edges of the output of the flip-flop circuit, and a second counting circuit counts intervals between edges detected by the second edge detection circuit and outputs a specific count value. A data synchronization circuit characterized in that synchronization is achieved by a coincidence output between the count value output and the second edge detection circuit output.