JPH07326963A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To reduce the jitter of an output clock signal by frequency-dividing a reference clock signal supplied from outside by a frequency dividing circuit, frequency- dividing a standard clock signal by an output clock frequency dividing circuit, and supplying both of the obtained frequency dividing signals to a phase comparison circuit through a window generation circuit for comparing phases. CONSTITUTION:This digital PLL circuit is provided with a frequency dividing counter 17 for preparing the output clock signal, a reference clock frequency dividing circuit 11 for frequency-dividing the reference clock signal and the output clock frequency dividing circuit 12 for frequency-dividing the output clock signal so as to detect the phase difference between the output signals of the circuits 11 and 12 by way of the window generation circuit 13 for comparing phases by the phase comparing circuit 14. When setting a frequency dividing value by a frequency dividing value setting circuit 16, one of a stationary value, a value obtained by subtracting a fixed minute quantity from the stationary value and a value obtained by adding a fixed minute quantity to the stationary value is selectively set counter 17. A frequency dividing value changing period for changing the value by the counter 17 to the minute quantity subtracted value or the minute quantity added value is generated by a frequency dividing value changing period generation circuit 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL circuit incorporated in a transmission device, for example.

[0002]

2. Description of the Related Art FIG. 5 shows a block diagram of a conventional digital PLL circuit. In FIG. 5, reference numeral 17 is a frequency dividing counter for generating an output clock signal by dividing the reference clock signal. Reference numeral 11 is a reference clock frequency dividing circuit for dividing a reference clock signal supplied from the outside. Reference numeral 12 is an output clock frequency dividing circuit for dividing the output clock signal. Reference numeral 14 is a phase comparison circuit that detects a phase difference between the output signal of the reference clock frequency dividing circuit 11 and the output signal of the output clock frequency dividing circuit 12. Reference numeral 13 is a phase comparison window generation circuit for generating a window for performing phase comparison in the phase comparison circuit. Reference numeral 16 'is a frequency division value setting circuit that sets a frequency division value to the frequency division counter 17 based on the phase comparison result of the phase comparison circuit 14 as a steady value or a value that differs from the steady value by a phase difference.

When the phase of the output signal of the output clock frequency dividing circuit 12 is substantially the same as the phase of the output signal of the reference clock frequency dividing circuit 11, the frequency dividing value setting circuit 16 'has a steady frequency dividing value. Set the value. Further, when the phase of the output signal of the output clock frequency dividing circuit 12 is delayed with respect to the phase of the output signal of the reference clock frequency dividing circuit 11,
The frequency division value of the frequency division counter 17 is set to a value that is smaller than the steady value by the phase difference. Furthermore, the output clock divider circuit 1
When the phase of the output signal 2 is ahead of the phase of the output signal of the reference clock frequency dividing circuit 11, the frequency division value of the frequency division counter 17 is set to a value that is increased by a phase difference from the steady value.

In this digital PLL circuit, a frequency dividing counter 17 divides a standard clock to create an output clock signal, and a reference clock signal supplied from the outside is frequency-divided by a reference clock frequency dividing circuit 11 to generate a standard clock. The output clock signal generated by the frequency dividing counter 17 is frequency-divided by the output clock frequency dividing circuit 12. Then, both frequency-divided signals respectively output from the reference clock frequency dividing circuit 11 and the output clock frequency dividing circuit 12 are supplied to the phase comparison circuit 14 through the phase comparison window generation circuit 13 to detect the phase difference between them. That is, the phase difference is detected by comparing it with the phase comparison window previously obtained.

In the frequency dividing value setting circuit 16 ', if the phase of the output signal of the output clock frequency dividing circuit 12 substantially matches the phase of the output signal of the reference clock frequency dividing circuit 11, the frequency dividing value is continuously maintained. As a steady value, keep the phase of the output clock signal unchanged. Also, the output clock divider circuit 1
When the phase of the output signal of 2 is delayed with respect to the phase of the output signal of the reference clock frequency dividing circuit 11, the frequency division value of the frequency dividing counter 17 is decreased by a phase difference from the steady value to thereby output the cycle of the output clock signal. Is made shorter than the steady cycle to reduce the phase delay of the output signal of the output clock frequency dividing circuit 12. On the contrary, when the phase of the output signal of the output clock frequency dividing circuit 12 leads the phase of the output signal of the reference clock frequency dividing circuit 11, the frequency dividing value of the frequency dividing counter 17 is increased by a phase difference from the steady value. By doing so, the cycle of the output clock signal is made longer than the steady cycle, and the output clock frequency dividing circuit 12
The phase lead of the output signal of is reduced. As a result, phase synchronization between the reference clock signal and the output clock signal is achieved. Further, the change width of the frequency division value of the frequency division counter 17 from the steady value is set to be large when the phase difference is large, and is set to be small when the phase difference is small so that the phase of the output clock signal is the phase of the reference clock signal. Quickly sync to.

[0006]

In the above conventional example, in order to quickly synchronize the phase of the output clock signal with the phase of the reference clock signal, the phase of the output signal of the output clock frequency dividing circuit 12 is changed to the reference clock frequency. When the phase of the output signal of the circuit 11 is deviated, the cycle of the output clock signal is temporarily changed according to the phase difference between the output signal of the output clock frequency dividing circuit 12 and the output signal of the reference clock frequency dividing circuit 11. Therefore, when the above phase difference is large, the cycle of the output clock signal will also change greatly, and the jitter of the output clock signal will increase, causing the transmission device to lose data synchronization and be transmitted. There is a risk of adverse effects such as the inability to accurately capture data.

Therefore, an object of the present invention is to provide a digital PLL circuit which can reduce the jitter of the output clock signal and reduce the adverse effects on the equipment using the clock signal such as the transmission device.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, in which the width of changing the cycle of the output clock signal is set to a fixed amount, and the cycle of the output clock signal is set to a fixed value from the steady cycle. A circuit that changes a cycle for changing a small amount (a cycle for changing a dividing value) according to the magnitude of a phase difference is incorporated. That is, when the phase difference is large, the cycle for changing the cycle is shortened, and when the phase difference is small, the cycle for changing the cycle is lengthened. That is, the width of changing the cycle of the output clock signal is constant, and the interval for changing the cycle is changed according to the magnitude of the phase difference, so that the cycle of the output clock signal does not change even when the phase difference is large. It can be suppressed and the jitter is reduced. Even if the phase difference is large, phase synchronization can be done quickly.

Hereinafter, description will be given in accordance with the content of the claims. The digital PLL circuit of the present invention is provided with a frequency dividing counter that divides a reference clock signal to generate an output clock signal, and is provided with a reference clock frequency dividing circuit that divides a reference clock signal supplied from the outside. An output clock divider circuit that divides the signal is provided, and a phase comparator circuit that detects the phase difference between the output signal of the reference clock divider circuit and the output signal of the output clock divider circuit is provided. A window generation circuit for phase comparison that generates a window to be performed is provided, and the frequency division counter is selectively set to either a steady value, a value that is reduced by a fixed small amount from the steady value, or a value that is increased by a fixed small amount from the steady value. A frequency division value setting circuit that sets the frequency division value is provided, and the frequency division value set by the frequency division value setting circuit in the frequency division counter is a value that is a constant value minus a steady amount It is provided a frequency division value changing period generating circuit for generating a frequency division value change period to change any of the values increased by a certain small amount than the steady value.

The frequency dividing value setting circuit divides the phase of the output signal of the output clock frequency dividing circuit when the phase of the output signal of the output clock frequency dividing circuit substantially matches the phase of the output signal of the reference clock frequency dividing circuit based on the phase comparison result of the phase comparing circuit. The frequency division value of the frequency division counter is continuously set to a steady value, and the frequency division value of the frequency division counter is output when the phase of the output signal of the output clock frequency divider circuit is behind the phase of the output signal of the reference clock frequency divider circuit. Is changed from a steady value to a value that is slightly smaller than the steady value at a predetermined frequency division value changing cycle, and the phase of the output signal of the output clock frequency divider leads the phase of the output signal of the reference clock frequency divider. If so, the frequency division value of the frequency division counter is changed from a steady value to a value that is increased by a constant small amount from the steady value at a predetermined frequency division value changing cycle.

The frequency division value change period generation circuit is based on the phase comparison result of the phase comparison circuit when the absolute value of the phase difference between the output signal of the output clock frequency division circuit and the output signal of the reference clock frequency division circuit is large. The frequency division value changing period is shortened, and the frequency division value changing period is lengthened when the absolute value of the phase difference between the output signal of the output clock frequency dividing circuit and the output signal of the reference clock frequency dividing circuit is small.

[0012]

According to the structure of the present invention, the reference clock signal supplied from the outside is divided by the reference clock frequency dividing circuit, and the output clock signal generated by the frequency dividing counter for dividing the reference clock signal is output clock. Divide by the divider circuit. Then, both frequency-divided signals respectively output from the reference clock frequency dividing circuit and the output clock frequency dividing circuit are supplied to the phase comparison circuit through the phase comparison window generation circuit to detect the phase difference between them.

When the phase of the output signal of the output clock frequency divider circuit is substantially the same as the phase of the output signal of the reference clock frequency divider circuit, the frequency divider value setting circuit continuously sets the frequency division value of the frequency divider counter. By setting it to a steady value, the cycle of the output clock signal is maintained at a steady cycle so that the phase does not change. Also, if the phase of the output signal of the output clock divider circuit is delayed with respect to the phase of the output signal of the reference clock divider circuit,
The frequency of the output clock signal is intermittently shortened from the steady cycle by changing the frequency division value of the frequency division counter from the steady value to a value that is a certain small amount less than the steady value at the predetermined frequency change cycle. The phase delay of the output signal of the frequency divider is reduced. On the contrary, if the phase of the output signal of the output clock frequency divider circuit is ahead of the phase of the output signal of the reference clock frequency divider circuit, the frequency division value of the frequency division counter is changed to a steady value at a predetermined frequency division value changing cycle. From the steady value to a value slightly larger than the steady value, the cycle of the output clock signal is intermittently made longer than the steady cycle to reduce the advance of the phase of the output signal of the output clock frequency dividing circuit.

When the absolute value of the phase difference between the output signal of the output clock frequency dividing circuit and the output signal of the reference clock frequency dividing circuit is large, the frequency dividing value changing period generation circuit shortens the frequency dividing value changing period and outputs the signal. The speed at which the phase of the output signal of the clock divider circuit approaches the phase of the output signal of the reference clock divider circuit is increased. Also, if the absolute value of the phase difference between the output signal of the output clock frequency divider circuit and the output signal of the reference clock frequency divider circuit is small, the frequency division value change cycle is lengthened and the phase of the output signal of the output clock frequency divider circuit becomes The speed of approaching the phase of the output signal of the reference clock frequency dividing circuit is reduced.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a digital PL according to an embodiment of the present invention.
The block diagram of L circuit is shown. In FIG. 1, reference numeral 17 is a frequency dividing counter that divides the reference clock signal to generate an output clock signal. Reference numeral 11 is a reference clock frequency dividing circuit for dividing a reference clock signal supplied from the outside. 12
Is an output clock divider circuit for dividing the output clock signal. Reference numeral 14 is a phase comparison circuit that detects a phase difference between the output signal of the reference clock frequency dividing circuit 11 and the output signal of the output clock frequency dividing circuit 12. Reference numeral 13 is a phase comparison window generation circuit for generating a window for causing the phase comparison circuit 14 to perform phase comparison. Reference numeral 16 denotes a frequency dividing value setting circuit for selectively setting, as a frequency dividing value, a constant value, a value which is decreased by a fixed small amount from the stationary value, or a value which is increased by a fixed small amount from the stationary value in the frequency dividing counter 17. Reference numeral 16 is a frequency division in which the frequency division value setting circuit 16 changes the frequency division value set in the frequency division counter 17 from a steady value to a value that is a certain small amount smaller than the steady value or a value that is a certain small amount is increased from the steady value. It is a frequency division value change period generation circuit that generates a value change period.

In the frequency division value setting circuit 16, the phase of the output signal of the output clock frequency dividing circuit 12 is substantially equal to the phase of the output signal of the reference clock frequency dividing circuit 11 based on the phase comparison result of the phase comparison circuit 14. Dividing counter 1 when doing
When the phase of the output signal of the output clock frequency dividing circuit 12 is delayed with respect to the phase of the output signal of the reference clock frequency dividing circuit 11, the frequency division value of 7 is continuously set to the steady value. The frequency value is changed from a steady value to a value obtained by decrementing the steady value by a constant small amount in a predetermined frequency division value changing cycle, and the phase of the output signal of the output clock frequency dividing circuit 12 is changed to the reference clock frequency dividing circuit 1.
When the phase of the output signal of 1 is advanced, the frequency division value of the frequency division counter 17 is changed from a steady value to a value slightly larger than the steady value by a predetermined frequency division value changing cycle. .

The frequency division value change period generation circuit 15 is based on the phase comparison result of the phase comparison circuit 14 and the absolute value of the phase difference between the output signal of the output clock frequency division circuit 12 and the output signal of the reference clock frequency division circuit 11. When the absolute value of the phase difference between the output signal of the output clock frequency dividing circuit 12 and the output signal of the reference clock frequency dividing circuit 11 is small, the frequency dividing value changing period is lengthened. I am trying to do it.

In this digital PLL circuit, the reference clock signal supplied from the outside is used as the reference clock frequency dividing circuit 11.
Frequency division counter 1 that divides by 1 to divide the reference clock signal
The output clock signal created in 7 is divided by the output clock divider circuit 12. Then, the reference clock frequency dividing circuit 11
And both frequency-divided signals output from the output clock frequency dividing circuit 12 are supplied to the phase comparison circuit 14 through the phase comparison window generation circuit 13 to detect the phase difference between them.

The frequency division value setting circuit 16 includes a frequency division counter 17
Is set to either a steady value, a value slightly smaller than the steady value or a value slightly larger than the steady value as the frequency dividing value, but the output is based on the phase comparison result of the phase comparison circuit 14. When the phase of the output signal of the clock frequency dividing circuit 12 substantially matches the phase of the output signal of the reference clock frequency dividing circuit 11, the frequency dividing value of the frequency dividing counter 17 is continuously set to a steady value to output. If the phase of the output signal of the output clock frequency dividing circuit 12 is delayed with respect to the phase of the output signal of the reference clock frequency dividing circuit 11 so that the phase of the clock signal is kept constant so as not to change the phase, the frequency division is performed. The frequency of the output clock signal is intermittently shortened from the steady cycle by changing the frequency division value of the counter 17 from the steady value to a value which is smaller than the steady value by a predetermined small amount in a predetermined frequency division value changing cycle. If the phase delay of the output signal of the frequency divider circuit 12 is reduced and, conversely, the phase of the output signal of the output clock frequency divider circuit 12 leads the phase of the output signal of the reference clock frequency divider circuit 11, the frequency division counter The frequency of the output clock signal is intermittently made longer than the steady cycle by changing the frequency division value of 17 from the steady value to a value which is increased by a constant small amount from the steady value in a predetermined frequency division value changing cycle. The phase advance of the output signal of the circuit 12 is reduced.

The frequency division value change period generation circuit 15 is a value obtained by dividing the frequency division value set in the frequency division counter 17 by the frequency division value setting circuit 16 from a steady value by a constant small amount from the steady value and by a constant small amount from the steady value. The frequency division value changing cycle for changing to any one of the increased values is generated, and the output signal of the output clock frequency dividing circuit 12 and the output signal of the reference clock frequency dividing circuit 11 are generated based on the phase comparison result of the phase comparison circuit 14. When the absolute value of the phase difference between the reference clock frequency dividing circuit 11 and the reference clock frequency dividing circuit 11 is short, the frequency division value changing cycle is shortened and the phase of the output signal of the output clock frequency dividing circuit 12 is changed.
Of the output signal of the output clock frequency dividing circuit 12 and the reference clock frequency dividing circuit 11 are increased.
When the absolute value of the phase difference from the output signal of the output clock signal is small, the frequency division value changing cycle is lengthened so that the phase of the output signal of the output clock frequency dividing circuit 12 approaches the phase of the output signal of the reference clock frequency dividing circuit 11. Make it smaller.

The digital PLL circuit of this embodiment will be described below in detail with reference to the concrete circuit diagram of FIG.
2, reference numeral 310 denotes a 45-divider circuit that divides the reference clock signal C-REF by 45, which corresponds to the reference clock divider circuit 11 in FIG. 320 is an output clock signal CB
It is a 67-divider circuit that divides AS by 67 and corresponds to the output clock divider circuit 12 in FIG. The 45 frequency divider circuit 310 and the 67 frequency divider circuit 320 use the reference clock signal C-RE.
When F and the output clock signal C-BAS are not the same frequency, one of them is divided by 45 and the other is divided by 67 in order to match the frequencies of the respective divided output signals. It should be noted that these frequency division values are appropriately set according to the frequencies of the reference clock signal C-REF and the output clock signal C-BAS.

Reference numeral 311 denotes a D flip-flop which receives the frequency-divided output signal of the 45-frequency-dividing circuit 310 as a data input and uses the control clock signal as a clock input, and controls rising and falling of the frequency-divided-output signal of the 45-frequency-dividing circuit 310. It has a function of synchronizing with the clock signal for use and generates a divided signal REF. It is sufficient that the control clock signal has a frequency about the same as or several times the frequency of the reference clock signal C-REF and the output clock signal C-BAS.

Reference numeral 330 denotes a D flip-flop 311 which receives the output signal of the D flip-flop 311 as a data input and the control clock signal as a clock input.
It has a function of shifting the output of 11 by one cycle of the control clock signal. An AND gate 331 takes the logical product of the output of the D flip-flop 311 and the inverted output of the D flip-flop 330, and its output signal REF-P is generated at the rising timing of the divided signal REF. That is, the D flip-flop 330 and the AND gate 331
Has a function of detecting the rising edge of the divided signal REF.

332 is a 5-bit binary counter,
While the frequency-divided signal REF is at the high level, it operates to count the control clock signal and outputs the window signals REF-Q3 and REF-Q4 corresponding to the count value. Reference numeral 321 is a D that receives the frequency-divided output signal of the 67-frequency-dividing circuit 320 as a data input and the control clock signal as a clock input.
The flip-flop has a function of synchronizing the rising and falling edges of the frequency-divided output signal of the 67-frequency-dividing circuit 320 with the control clock signal, and generates the frequency-divided signal BAS.

Reference numeral 335 is a D flip-flop which receives the output signal of the D flip-flop 321 as a data input and the control clock signal as a clock input.
It has a function of shifting the output of 21 by one cycle of the control clock signal. An AND gate 336 takes the logical product of the output of the D flip-flop 321 and the inverted output of the D flip-flop 335, and its output signal BAS-P is generated at the rising timing of the divided signal BAS. That is, the D flip-flop 335 and the AND gate 336.
Has a function of detecting the rising edge of the divided signal BAS.

337 is a 5-bit binary counter,
While the divided signal BAS is at the high level, it operates to count the control clock signal, and outputs the window signals BAS-Q3 and REF-Q4 corresponding to the count value. The above D flip-flops 311, 321, 33
0, 335, AND gates 331, 336, and binary counters 332, 337 configure the phase comparison window generation circuit 13 in FIG.

Reference numerals 340 and 341 denote latches, respectively, which indicate the rising timing of the divided signal BAS, that is, the signal BA.
In response to SP, window signals REF-Q3, REF
It has a function of holding the state of -Q4, and the latch 340 generates an output signal PA and the latch 341 generates an output signal PB. 342 and 343 are latches, respectively, which respond to the rising timing of the divided signal REF, that is, the signal REF-P, in response to the window signal BAS-Q
3, it has a function of holding the state of BAS-Q4, and an output signal P-C is generated from the latch 342 and an output signal P-D is generated from the latch 341. Each latch 340-34
The three output signals P-A, P-B, P-C, and P-D differ depending on whether the phase of the frequency-divided signal BAS is advanced or delayed with respect to the frequency-divided signal BAS, and the magnitude of the phase difference.

Reference numeral 344 denotes a phase difference decision decoding circuit, which is the output signals P-A, P-B, P-C of the latches 340-343.
P-D is converted into an output signal U-D indicating whether the phase difference is advanced or delayed, an output signal PS indicating whether to perform control, and an output signal W1 indicating the magnitude of the phase difference. The above latches 340-3
43 and the phase difference decision decoding circuit 344 constitute the phase comparison circuit 14 of FIG.

Reference numeral 350 denotes a 3-bit presettable counter, which constitutes the frequency division value change period generation circuit 16 of FIG. 1, and the output signal W1 of the phase difference determination decoding circuit 344 is "H" (or "1"). In this case, "100" is preset, and when the output signal W1 of the phase difference determination decoding circuit 344 is "L" (or "0"), "000" is preset. Therefore, when the output signal W1 is "H",
When the four output clock signals are counted, the output signal CTRL-P is generated. When the output signal W1 is "L", the output signal CTRL-P is generated when the eight output clock signals are counted. . That is, when the phase difference is large, a frequency division value changing cycle having four cycles of the output clock signal as one cycle is generated, and when the phase difference is small, the frequency division value having eight cycles of the output clock signal as one cycle. Generate a change cycle.

Reference numeral 360 is a latch, 361 to 363 are AND gates, 364 is an OR gate, and 365 is a 3-bit latch, which constitute the frequency division value setting circuit of FIG.
Output signals UD and PS of the phase difference determination decoding circuit 344
And the output signal CTRL- of the presettable counter 350.
Using P and P as input, the frequency division value is set to 15, 16, or 17.

In this case, when the output signal PS is "L" (or "0"), the frequency division value is always set to 16. When the output signal PS is "H" (or "1"), the output signal U-
When D is "H" (or "1"), output signal CTR
The division value is set to 16 when LP is "L", and the division value is set to 15 when the output signal CTRL-P is "H". When the output signal PS is "H" (or "1"),
When the output signal UD is "L" (or "0"), the division value is set to 16 when the output signal CTRL-P is "L", and the output signal CTRL-P is "H". Sometimes the division value is set to 17. In the output signal CTRL-P, when the output signal W1 is “H” (or “1”), it becomes “H” (or “1”) once every four cycles of the output clock signal C-BAS, The output signal W1 is "L" (or "0") every 1 cycle in 8 cycles of the output clock signal C-BAS.
It becomes "H" (or "1") at a rate of times.

Therefore, the output signal PS is "H" (or "1"), the output signal U-D is "H" (or "1"), and the output signal W1 is "H" (or "1"). In this case, the frequency division value changes from 16 to 15 once every four cycles of the output clock signal C-BAS. When the output signal PS is "H" (or "1"), the output signal UD is "H" (or "1"), and the output signal W1 is "L" (or "0") , The frequency division value changes from 16 to 15 at a rate of once every eight cycles of the output clock signal C-BAS.
Further, the output signal PS is "H" (or "1"), the output signal UD is "L" (or "0"), and the output signal W1 is
Is "H" (or "1"), the frequency division value is 16 to 1 at a rate of once every four cycles of the output clock signal C-BAS.
Change to 7. Further, the output signal PS is "H" (or "1") and the output signal UD is "L" (or "0").
When the output signal W1 is "L" (or "0"),
The frequency division value changes from 16 to 17 at a rate of once every eight cycles of the output clock signal C-BAS. Also, as mentioned above,
When the output signal PS is "L" (or "0"), the frequency division value is 16 over the entire period of the output clock signal C-BAS.
To maintain.

Reference numeral 370 denotes the frequency division value BAS-L set by the presettable counter 350 and the reference clock signal C0-.
The 5-bit presettable counter that divides the BAS to generate the output clock signal C-BAS constitutes the divider counter 17 in FIG. 371 is a signal BAS- synchronized with the carry output signal BAS-TC of the presettable counter 370 and the reference clock signal C0-BAS.
It is a D flip-flop that creates a PC.

The operation of the digital PLL circuit of FIG. 2 will be described with reference to the time charts of FIGS. 3 and 4. First, the generation of the phase comparison window and the phase comparison operation will be described with reference to the time chart of FIG.
A signal obtained by dividing the reference clock signal C-REF by 45 is passed through the D flip-flop 311 for synchronization and is used as a divided signal REF. Then, the signal passed through the flip-flop 330 and the divided signal REF are passed through the AND gate 331 to generate the signal REF-P indicating the rising edge of the divided signal REF (see arrow (a) in FIG. 3). ).

By advancing the binary counter 332 while the divided signal REF is "H", for example, Q3, Q
4, window signals REF-Q3 and REF-Q4 are generated (see arrow (b) in FIG. 3). Similarly, for the output clock signal C-BAS, the divided signal BAS,
Rising signal BAS-P, window signal BAS
-Q3 and BAS-Q4 are generated.

Further, in order to determine the phase difference between the divided signal BAS and the divided signal REF, a signal BAS- indicating a rising edge is generated.
Window signals REF-Q3 and RE when P is "H"
Similarly, the states of the window signals BAS-Q3 and BAS-Q4 when the signal REF-P indicating the rising edge is "H" are latched respectively.
Hold at 40-343.

In the time chart of FIG. 3, the divided signal BAS of the output clock signal C-BAS is the reference clock signal C.
-Because it shows a state of being delayed from the divided signal REF of -REF, the divided signal BA of the output clock signal C-BAS is shown.
When the signal BAS-P indicating the rising edge of S is "H", the divided signal RE of the reference clock signal C-REF is
The window signal REF-Q4 on the F side is "H", and the output signal P-B of the latch 341 is "H" (see arrow (c) in FIG. 3). The window signal REF-Q4 is "L", and the output signal P-A of the latch 340 remains "L".

Frequency division signal R of reference clock signal C-REF
When the signal REF-P indicating the rise of EF is "H", the divided signal B of the output clock signal C-BAS corresponding to
All the window signals BAS-Q3 and BASQ4 on the AS side remain "L". Therefore, the latch 342,
Both of the output signals P-C and P-D of 343 remain "L".

Output signals P- of these latches 340 to 343
By decoding and holding A, P-B, P-C, and P-D in the cycle of the divided signal, that is, in response to the signals REF-P and BAS-P, the phase difference between the divided signals BAS and REF is obtained. Can be detected. Table 1 shows a truth table of an example of the phase difference determination decoding circuit 344 of the digital PLL circuit of FIG.

[0040]

[Table 1]

By the decoding according to Table 1, the output signal of the phase difference determination decoding circuit 344 becomes (PS, U-
D, W1) = (H, H, H) or “111” is output from the phase difference determination decoding circuit 344 in synchronization with the timing of the signal REF-P indicating the rising edge of the divided signal REF (FIG. 3). Arrow (d)). If the phase delay of the frequency-divided signal BAS of the output clock signal C-BAS is smaller than that in FIG. 3, the window signal at the timing of the signal BAS-P indicating the rise on the output clock signal side is REF-Q3 = "H. ", And REF-Q4 =" L "
And the decoding result is (PS, UD, W1) =
(H, H, L).

Further, when the phase delay is reduced, (P
S, U-D, W1) = (L, L, L). On the contrary, when the phase of the output clock advances, the decoding result becomes (PS, U
-D, W1) = (L, L, L), (H, L, L),
It becomes like (H, L, H). Next, the operation of determining the output clock cycle will be described with reference to the time chart of FIG.

Prior to the description of the operation, the frequency division value change period generation circuit and the frequency division value setting circuit will be briefly described again. As an example of the frequency dividing counter 17 that determines the cycle of the output clock, a 5-bit presettable counter 370 is provided.
In this example, the presettable counter 370 is used to count any of 15, 16, and 17 reference clocks. As an example of a circuit that determines the frequency division value,
Latch 360, AND gates 361, 362, 363,
Decode circuit and latch circuit 3 consisting of OR gate 364
65 combinations are shown. As an example of a circuit that determines the cycle of frequency division value change, a frequency division value change cycle generation circuit 15 using a 3-bit presettable counter 350 is shown. The change cycle generation circuit 350 compares the signal BAS-PC generated in synchronization with the output clock with the previous phase comparison circuit (latch 3
40 to 343), the period is determined by counting according to the value determined by the output signal W1 indicating the magnitude of the phase difference detected. The periodic signal is output as the signal CTRL-P.

In this example, the phase difference determination decoding circuit 3
As the output of 44, an output signal W1 indicating the magnitude of the phase difference
Therefore, in FIG. 4, W1 = “H” is input. Therefore, "100" is input as the preset value of the presettable counter 350 for generating the frequency division value changing period (see arrow (e) in FIG. 4). Therefore, the signal CTRL-P is output at a cycle of counting the signal BAS-PC output from the latch 371 by 4 (see the arrow (f) in FIG. 4). The signal BAS-PC is the signal BAS-TC.
Is shifted by one reference clock C0-BAS.

As described above, when the phase difference becomes large, W1 = "H", and when the phase difference becomes small, W1 becomes "1".
= “L”. When W1 = “H”, the cycle of the CTRL-P signal is 4, and when W1 = “L”, the preset value of the presettable counter 350 is “000”.
Is inputted, the period of the signal CTRL-P becomes 8. The signal INT-Q indicates the count value of the presettable counter 350.

The latch 360 which is the frequency division value setting circuit 16,
AND gate 361, 362, 363, OR gate 36
The circuit of the combination of the decode circuit composed of 4 and the latch circuit 365 decodes from the signal CTRL-P and the output signals UD and PS of the phase difference determination decode circuit 344,
Determine the frequency division value (either 15, 16, or 17) (Fig. 4
Arrow (g)). The BAS-LD has a latch 36.
5 and BAS-L is a preset input of the presettable counter 370.

Then, "10001" is preset in the presettable counter 370 which determines the cycle of the output clock signal C-BAS only in the cycle after the signal CTRL-P becomes "H", and the cycle of the output clock signal C-BAS is preset. Will be "15", which is shorter than usual. As a result, the phase of the frequency-divided signal BAS of the output clock signal C-BAS is advanced, and the delay phase of the frequency-divided signal REF of the reference clock signal C-REF is reduced.

In the other cycles, that is, the signal CTRL-
When P is "L", "10000" is preset in the presettable counter 370, and the output clock signal C
-The BAS cycle becomes the normal "16" (see arrow (i) in FIG. 4). On the contrary, when the frequency-divided signal BAS of the output clock signal C-BAS is earlier than the frequency-divided signal REF of the reference clock signal C-REF, the output signal from the phase difference determination decoding circuit 344 is (PS, U- D, W1) =
(H, L, L) or (H, L, H), and the preset value to the presettable counter 370 is "0111.
1 ", and the cycle of the output clock signal C-BAS is" 1 ".
It will be as long as 7 ”. Note that the cycle "17" is once every four times or once every eight times, as in the above case.

When the phases of the divided signals BAS and REF are almost the same, the phase difference determination decoding circuit 344 is used.
The output signal from (PS, UD, W1) = (L,
L, L) and the preset value to the presettable counter 370 is always "10000", so the cycle of the output clock is constant at "16". From the above, when the phase difference is large, the timing of setting the output clock cycle to "15" or "17" is changed at a rate of once every four times, and once every eight times when the phase difference is small. Will be changed at the rate of.

The cycle fluctuation of the output clock signal C-BAS is small at only 15, 16 and 17, but when the phase difference is large, the cycle changing cycle is shortened to increase the rate of cycle changing. Can be faster.
According to this embodiment, when the phase of the output signal of the output clock frequency dividing circuit 12 substantially matches the phase of the output signal of the reference clock frequency dividing circuit 11, the frequency division value of the frequency dividing counter 17 is continuously maintained. By making it a steady value, the cycle of the output clock signal is kept at a steady cycle so that the phase does not change,
When the phase of the output signal of the output clock frequency divider circuit 12 is delayed with respect to the phase of the output signal of the reference clock frequency divider circuit 11, the frequency division value of the frequency division counter 17 is a steady value at a predetermined frequency division value changing cycle. From the steady value to a value slightly smaller than the steady value, the cycle of the output clock signal is intermittently shortened from the steady cycle to reduce the phase delay of the output signal of the output clock frequency dividing circuit 12, and vice versa. When the phase of the output signal of the output clock frequency dividing circuit 12 leads the phase of the output signal of the reference clock frequency dividing circuit 11, the frequency dividing counter 1
By changing the division value of 7 from the steady value to a value that is increased by a constant small amount from the steady value at a predetermined division value changing cycle, the cycle of the output clock signal is intermittently made longer than the steady cycle and the output clock is divided. When the phase advance of the output signal of the frequency dividing circuit 12 is reduced and the absolute value of the phase difference between the output signal of the output clock frequency dividing circuit 12 and the output signal of the reference clock frequency dividing circuit 11 is large, the frequency dividing value is changed. The period is shortened to increase the speed at which the phase of the output signal of the output clock frequency dividing circuit 12 approaches the phase of the output signal of the reference clock frequency dividing circuit 11, and the output signal of the output clock frequency dividing circuit 12 and the reference clock frequency dividing circuit are increased. When the absolute value of the phase difference from the output signal of 11 is small, the frequency division value changing cycle is lengthened so that the phase of the output signal of the output clock frequency dividing circuit 12 approaches the phase of the output signal of the reference clock frequency dividing circuit 11. To By fence, less the output clock signal is obtained jitter can be improved and synchronization performance of the transmission device.

In this embodiment, when the phase difference is large, the frequency division value is changed once every four times, and when the phase difference is small, the frequency division value is changed once every eight times. The changing cycle is not limited to the above. For example, when the phase difference is large, the frequency division value may be changed once every two times, and when the phase difference is small, the frequency division value may be changed once every four times, or when the phase difference is large, the full frequency division value may be changed. The frequency division value may be changed once every two times when the phase difference is small.

[0052]

According to the digital PLL circuit of the present invention, when the phase of the output signal of the output clock frequency dividing circuit substantially matches the phase of the output signal of the reference clock frequency dividing circuit, the frequency division of the frequency dividing counter is performed. By setting the value to a steady value continuously, the cycle of the output clock signal is maintained at a steady cycle so that the phase does not change, and the phase of the output signal of the output clock frequency divider circuit is the phase of the output signal of the reference clock frequency divider circuit. When the frequency is delayed with respect to the phase, the frequency division value of the frequency division counter is changed at a predetermined frequency division value change cycle from a steady value to a value that is a fixed small amount less than the steady value, so that the cycle of the output clock signal is intermittent. The output clock divider circuit output signal phase delay by shortening the output clock divider circuit output signal phase relative to the reference clock divider circuit output signal phase. The frequency of the output clock signal is intermittently changed from the steady cycle by changing the division value of the frequency division counter from the steady value to a value that is increased by a fixed small amount from the steady value at the predetermined frequency division value change cycle. If the absolute value of the phase difference between the output signal of the output clock frequency divider circuit and the output signal of the reference clock frequency divider circuit is large, increase The cycle of changing the frequency value is shortened to increase the speed at which the phase of the output signal of the output clock divider circuit approaches the phase of the output signal of the reference clock frequency divider circuit, and the output signal of the output clock frequency divider circuit and the reference clock frequency divider circuit are increased. When the absolute value of the phase difference with the output signal of is small, the frequency division value changing cycle is lengthened to reduce the speed at which the phase of the output signal of the output clock frequency divider approaches the phase of the output signal of the reference clock frequency divider. And the less the output clock signal is obtained jitter can be improved and synchronization performance of the transmission device.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a digital PLL circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration of the digital PLL circuit of FIG.

FIG. 3 is a time chart for explaining a phase comparison window generation and phase comparison operation in the digital PLL circuit of FIG.

FIG. 4 is a time chart showing how the output clock cycle is set in the digital PLL circuit of FIG.

FIG. 5 is a block diagram showing a configuration of an example of a conventional digital PLL circuit.

[Explanation of symbols]

 11 Reference Clock Frequency Divider 12 Output Clock Frequency Divider 13 Phase Comparison Window Generation Circuit 14 Phase Comparison Circuit 15 Frequency Division Value Change Cycle Generation Circuit 16 Frequency Division Value Setting Circuit 17 Frequency Division Counter 310 45 Frequency Division Circuit 311 D Flip-flop 320 67 Frequency divider 321 D flip-flop 330 D flip-flop 331 AND gate 332 Binary counter 335 D flip-flop 336 AND gate 337 Binary counter 340 Latch 341 Latch 342 Latch 343 Latch 344 Phase difference determination decoding circuit 350 Presettable counter 360 Latch 361 AND-gate 362 AND-gate 363 AND-gate 364 OR-gate 365 Latch 370 Presettable counter 371 Latch

Claims (1)

[Claims] 1. A frequency dividing counter for dividing a reference clock signal to generate an output clock signal, a reference clock frequency dividing circuit for dividing an externally supplied reference clock signal, and frequency dividing the output clock signal. An output clock frequency dividing circuit, a phase comparison circuit for detecting a phase difference between the output signal of the reference clock frequency dividing circuit and the output signal of the output clock frequency dividing circuit, and for causing the phase comparison circuit to perform the phase comparison. And a phase comparison window generation circuit for generating a window for selectively dividing a constant value into the steady state value, a value that is reduced by a fixed small amount from the steady value, or a value that is increased by a fixed small amount from the steady value. A frequency dividing value setting circuit for setting the frequency dividing value, and a value obtained by reducing the frequency dividing value set by the frequency dividing value setting circuit in the frequency dividing counter from the steady value by a certain small amount from the steady value. And a frequency division value change cycle generation circuit for generating a frequency division value change cycle for changing to a value that is increased by a constant small amount from the steady value, wherein the frequency division value setting circuit is the phase of the phase comparison circuit. On the basis of the comparison result, when the phase of the output signal of the output clock frequency dividing circuit substantially matches the phase of the output signal of the reference clock frequency dividing circuit, the frequency division value of the frequency dividing counter is continuously set to the steady state. When the phase of the output signal of the output clock frequency dividing circuit is delayed with respect to the phase of the output signal of the reference clock frequency dividing circuit, the frequency dividing value of the frequency dividing counter is changed to a predetermined frequency dividing value changing cycle. When the steady value is changed to a value that is slightly smaller than the steady value by a certain amount, and the phase of the output signal of the output clock frequency dividing circuit leads the phase of the output signal of the reference clock frequency dividing circuit, The dividing coun The frequency division value of the phase comparison circuit is changed from the steady value to a value which is increased by a constant small amount from the steady value in a predetermined frequency division value change cycle. Based on the comparison result, when the absolute value of the phase difference between the output signal of the output clock frequency dividing circuit and the output signal of the reference clock frequency dividing circuit is large, the frequency dividing value changing cycle is shortened,
The digital PLL circuit is characterized in that when the absolute value of the phase difference between the output signal of the output clock frequency dividing circuit and the output signal of the reference clock frequency dividing circuit is small, the frequency dividing value changing period is lengthened. .