JPH0421212A - Digital phase locked loop circuit - Google Patents

Abstract

PURPOSE:To suppress output jitter by discriminating the direction of a frequency offset of an input signal in an offset detection circuit and outputting a dead band control signal setting a dead band in opposite direction to the discriminated direction so as to set the dead band to a phase comparator. CONSTITUTION:A phase comparator 1 applies M-value quantization as to how many bits of inputted phase information are deviated from a clock signal in the lead or lag direction. When a set reset flip-flop(SR-FF) 9 is set, a least significant bit N1 among M-sets of delay phase information N1-NM subjected to multi-value quantization is inhibited by an AND gate 11a to set a dead band. On the other hand, when the SR-FF 9 is reset, a bit P1 is inhibited by an NAND gate 11b to set a dead band. Thus, a phase difference between an input signal and a clock signal inputted to the phase comparator is within the dead band, since no excess phase control is implemented, the output jitter is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital phase synchronization circuit that creates a clock that is phase synchronized with an input signal.

[Prior Art] Figure 4 shows, for example, a conventional digital phase shifter shown in "How to use rPLL-IC" written by Furuyo Hata (published by Sanpo Publishing Co., Ltd., November 20, 1987), page 147. FIG. 2 is a block diagram showing a synchronous circuit. In this figure, 16 is a phase comparison circuit that compares the phase information inputted from the input terminal 6 with the clock signal and outputs a binary quantized phase comparison result. Reference numeral 3 denotes a sequential loop filter (hereinafter abbreviated as SLF) including an up-down count and consisting of, for example, a random walk filter, which outputs a phase control signal from the input phase comparison result. 4 is a variable frequency divider circuit which changes the frequency division number of the high-speed clock from the oscillator 5 in response to the phase control signal input from the 5LF3, and synchronizes the phase with the phase information input from the input terminal 6. A signal is output from the output terminal 7.

Next, the operation will be explained.

Phase information is input as an input signal from the input terminal 6 to the phase comparator circuit 16, and the phase comparator circuit 16 compares the phase information with the clock signal from the variable frequency divider circuit 4 to determine if the phase information is "advanced". ” or “delay”, and outputs a binary quantized phase comparison result. Based on this phase comparison result, the 5LF3 outputs a phase control signal indicating the presence or absence of phase control and the direction of "advance" or "delay" if control is to be performed. For example, if a random walk filter is used for 5LF3, 5LF3 will be "10N" where N is a natural number.
It is equipped with an up/down counter that changes from "-N", and when the phase comparison result from the phase comparison circuit 16 is "advance", the value of the counter is r+tJL, and when it is "lag", it is "-1".
"do. As a result, when the value of this counter reaches "10N", an "advanced" phase control signal is output, and when it reaches r-NJ, a "lag" phase control signal is output, and at the same time, the counter value is set to "0". Reset. When there is no phase control signal, the variable frequency divider circuit 4 divides the oscillator 5 at a certain frequency division number.
This frequency division number is called the reference frequency division number. When there is a phase control signal, the variable frequency divider circuit 4 sets the frequency division number to be lower than the reference frequency division number in "advanced" phase control.
+1" and "-1" in the "delay" phase control to output a clock phase-synchronized with the input signal to the output terminal 7, and at the same time, this clock is input to the phase comparator circuit 16.

[Problem to be solved by the invention]

Since the conventional digital phase synchronization circuit is configured as described above, even when the phase difference between the phase information of the input signal and the output clock signal from the variable frequency divider circuit 4 is almost 0, there is no "lead" or "lead". The phase comparison result of "delay" is output from the phase comparison circuit 16, and as a result, there is a problem that the jitter of the output clock becomes thick.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a digital phase synchronization circuit that can suppress the output voltage to a low level.

[Means for Solving the Problems 1] A digital phase-locked circuit according to the present invention includes an oscillator that outputs a high-speed clock, and a variable circuit that divides and outputs the high-speed clock input from the oscillator based on an input phase control signal. A frequency divider circuit, a phase comparator circuit that compares the phase of the clock signal output from this variable frequency divider circuit and an input signal and outputs a phase comparison result, and an input signal based on the phase comparison result input from this phase comparator circuit. An offset detection circuit that determines the direction of the frequency offset of the signal and outputs a dead zone setting control signal to the phase comparison circuit to set a dead zone in the opposite direction to the determined direction, and proceeds with phase control based on the input phase comparison result. It is equipped with a sequential loop filter that outputs a phase control signal to the variable frequency divider circuit to instruct whether to perform the control on the side or the delay side.

[Operation] In the present invention, the offset detection circuit determines the direction of the frequency offset of the input signal, and outputs a dead zone control signal that sets a dead zone in the opposite direction to the determined direction. is set, so if the phase difference between the input signal input into the phase comparison circuit and the clock signal is within the range of the dead zone, no phase control is performed.

[Embodiment 1] FIG. 1 is a block diagram showing an embodiment of the digital phase synchronization circuit of the present invention. In this figure, the same or corresponding parts as in FIG. 4 are designated by the same reference numerals, and redundant explanation will be omitted. Reference numeral 1 denotes a phase comparator circuit which multi-level quantizes the phase difference between input phase information and a clock signal, and a dead zone is set by an input dead zone setting control signal. 2 is an offset detection circuit that determines whether the frequency offset of the input signal is in the "advance" direction or the "delay" direction based on the input phase comparison result, and a dead zone setting control signal that sets a dead zone in the opposite direction to the determined direction. is output to the phase comparator circuit 1. Further, FIG. 2 is a diagram showing a partial configuration example of the offset detection circuit 2 and the phase comparison circuit 1, and the area within the frame indicated by the dotted line corresponds to the offset detection circuit 2. In this figure, 8 is an up/down counter, and 9 is a set/reset counter.
Flip-flop (hereinafter abbreviated as 5R-FF), 10
a and 10b are OR gates, 11a and 11b are AND gates, 12 is an input terminal for delayed phase information N1 to NM that has been multi-valued quantized into M pieces [M is a natural number], and 13 is also multi-valued quantized into M pieces. Input terminal for the advanced phase information P1 to PM, 1
4 is an output terminal for a smoothed "lag" signal, and 1 and 5 are output terminals for a smoothed "advanced" signal.

Next, the operation will be explained.

The phase comparator circuit 1 quantizes the number of bits of the input phase information in the direction of "lead" or "lag" with respect to the clock signal, using the high-speed clock output from the oscillator 5 as a unit, by M-value quantization. The result is smoothed by the OR gate 10b into only "advance" and "delay" information and output to the offset detection circuit 2.5LF3. This phase comparison result corresponds to "advance" information a and "delay information" b in FIG. The "advance" information a increments the value of the up/down counter 8 by "+1", and the "delay" information a increments the value by "-1". The up/down counter 8 takes values from "10k" to "-k", where k is a natural number, and the count value is "10k".
”, sets 5R-FF9 and resets the count value to rOJ, and when the count value reaches r-kl, resets 5R-FF9 and resets the count value to “
0”. When 5R-FF9 is set,
A dead zone is set by inhibiting the least significant bit N1 of the M multi-level quantized delayed phase information N1 to NM by the AND gate 11a. On the other hand, 5R-
When FF9 is reset, the least significant bit P1 of the M multi-level quantized advanced phase information P1 to PM becomes AN
A dead zone is set by being inhibited by the D gate 11b. It is shown that the above operation reduces the jitter of the clock signal.

FIG. 3 shows the change in phase difference when the input signal has a positive offset with respect to the clock signal.

In the figure, the vertical axis represents the phase difference, where the phase advance of the input signal with respect to the clock signal is positive, and the numerical value attached to this is in units of 1 bit of the high-speed clock, and the horizontal axis represents time. The numerical value attached to represents the number of times the clock signal is input to the phase comparator circuit 1. If the offset advances by 2/3 bits during one output clock period, the mark rate is 1, and there is no initial phase difference, the phase will be r+2/3 J bits by one sample time. Then, the variable frequency divider circuit 4 controls the reference frequency division number Mtr by "-1" and advances the phase of the output clock, so that at the time of 2 samples, the phase difference is reduced by 1 bit from r+4/3J bits and r
It becomes +1/3 J bit. In this way, the phase difference becomes approximately O at the time of 3 samples.

However, in the case of a conventional digital phase-locked circuit, even if the phase difference is slightly negative, the variable frequency divider circuit 4 performs "+1" control on the reference frequency division number M 1 r, as shown in the figure. As shown by the dotted line, when there are 4 samples, the phase difference is approximately r + 5
/ 3 J bits.

On the other hand, in the case of the digital phase synchronized circuit according to the present invention, as shown in FIG. 2 which is an example of the configuration of the offset detection circuit 2, a positive offset always causes the phase comparison result of the "advanced" information a to be the phase of the "lag" information a. Since the output is larger than the comparison result, the value of up/down counter 8 is always "
As a result, N1 is inhibited, and a dead zone corresponding to one bit in the negative direction is set as shown in FIG. That is, as a result, the delay up to 1 bit is ignored, the phase comparison result is not output at the time of 3 samples, and the variable frequency divider circuit 4 uses the reference frequency division number M.
Since the frequency is divided by fr, the phase difference becomes approximately r+2/3J bits at the time of 4 samplings, as shown by the solid line in FIG.

Below, if we consider the same way and draw up to 9 sampling times, the result will be as shown in the figure.

In the example shown in this figure, the rNJO value of the up/down counter 8 of the 5LF3 is 1. Further, the method of configuring the offset detection circuit 2 shown in FIG. 2 can cope with the case where the offset changes.

Further, in the above embodiment, the dead zone is set on the delayed side, but it goes without saying that it may be set on the advanced side.

〔Effect of the invention〕

As described above, according to the present invention, there is provided an oscillator that outputs a high-speed clock, a variable frequency divider circuit that divides and outputs the high-speed clock input from the oscillator based on an input phase control signal, and A phase comparison circuit that compares the phase of the clock signal output from the circuit and the input signal and outputs the phase comparison result, and a phase comparison circuit that determines the direction of the frequency offset of the input signal based on the phase comparison result input from this phase comparison circuit. , an offset detection circuit that outputs a dead zone setting control signal that sets a dead zone in the opposite direction to the determined direction to the phase comparison circuit, and a control signal that determines whether to perform phase control on the leading side or the delayed side based on the input phase comparison result. Equipped with a sequential loop filter that outputs a phase control signal that instructs the variable frequency dividing circuit to the variable frequency divider circuit, excessive phase control will be avoided if the phase difference between the input signal input to the phase comparison circuit and the clock signal is within the dead band range. Since this is not done, it has the effect of suppressing ivy.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital phase synchronization circuit according to the present invention, FIG. 2 is a circuit diagram showing a partial configuration example of an offset detection circuit and a phase comparison circuit, and FIG. FIG. 4, which is a diagram for explaining the effect of noise reduction, is a block diagram showing a conventional digital phase synchronization circuit. In the figure, 1 is a phase comparison circuit, 2 is an offset detection circuit, 3 is a sequential loop filter, 4 is a variable frequency divider circuit, and 5 is an oscillator. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) who amended the No. 1 Zuden on July 9, 1991.Relationship with the case: Patent applicant Address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4, Agent Address 5, Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo, 5, Details of the detailed description of the invention in the specification subject to amendment 6, Contents of amendment (1) No. 1 of the specification Correct the "phase information" on page 3, line 6, to "phase of clock signal." (2) Similarly, "up-down counter 8" on page 10, lines 16-17 is corrected to "up-down counter."that's all

Claims (1)

[Claims] an oscillator that outputs a high-speed clock; a variable frequency divider circuit that divides and outputs the high-speed clock input from the oscillator based on an input phase control signal; and a clock signal output from the variable frequency divider circuit. a phase comparison circuit that compares the phases of input signals and outputs a phase comparison result; and a phase comparison circuit that determines the direction of the frequency offset of the input signal based on the phase comparison result inputted from the phase comparison circuit, and determines the direction of the frequency offset of the input signal, and an offset detection circuit that outputs a dead zone setting control signal for setting a dead zone in the opposite direction to the phase comparison circuit;
A digital phase shifter comprising a sequential loop filter that outputs a phase control signal to the variable frequency divider circuit to instruct whether to perform phase control on the leading side or the delayed side based on the inputted phase comparison result. synchronous circuit.