JP2570472B2 - Digital PLL circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital PLL circuit in which all components of a PLL (Phase Locked Loop) are digitized.

[Prior Art] Conventionally, a digital PLL circuit is configured as shown in FIG. In this figure, the input pulse Pi supplied serially from the outside is DPC (Digital Phase
(Comparator) 1. The DPC 1 is composed of a counter, an exclusive OR gate, etc., and receives an externally supplied input pulse Pi and a DCO
(Digital Control Oscillator) A phase difference from the output pulse Po supplied from the digital control oscillator 3 is detected, and a pulse signal corresponding to the phase difference is supplied to the loop filter 2. In the loop filter 2, the carrier component and the noise component of the input pulse Pi included in the output pulse signal of the DPC1 are removed, and setting data corresponding to the actual phase difference is supplied to the DOC3 as a predetermined multi-bit digital signal. You. The DCO 3 is constituted by a counter or the like, and outputs a pulse signal having a frequency corresponding to the supplied setting data. The pulse signal output from the DCO 3 is output to the outside as an output pulse Po and is also supplied to the DPC 1.

The above-described DPC1 and DCO3 function as a phase comparison and a VCO (voltage controlled oscillator) of a normal analog PLL circuit, respectively. As a result, the whole operates following the frequency of the input pulse Pi, and operates in a direction in which the phase difference between the input pulse Pi and the output pulse Po is always “0”.

Note that a digital filter using a loop filter as described above
Although the PLL circuit is of a digital type, there is an advantage that the characteristics of the PLL can be easily and analogously designed by changing the setting of the loop filter. For example, it is possible to flexibly select a desired characteristic such as whether or not to make it difficult to respond to noise or whether or not to make the tracking speed of phase lock fast, and to obtain a desired characteristic. PLLs can be easily designed.

[Problems to be Solved by the Invention] By the way, in the above-described digital PLL circuit, when processing a high-frequency pulse signal, it is necessary to separately provide high-speed operable counters for both DPC1 and DCO3, and the configuration is complicated There was a problem of becoming. Further, in the loop filter 2, the output from the DPC1 is set to 1 corresponding to the phase difference between the input pulse Pi and the output pulse Po from the DOC3.
Because of the bit pulse output, there are many harmonic components, and it is extremely difficult to convert this into a multi-bit digital signal.The carrier component of the input pulse Pi generated by the DPC1 cannot be effectively removed, and this loop filter There was also a problem that the design of No. 2 was extremely complicated.

The present invention has been made in view of the above circumstances, and has as its object to provide a digital PLL circuit that simplifies the circuit configuration and the loop filter design.

Means for Solving the Problems According to the present invention, there is provided a counter for presetting an initial value in response to the arrival of a coincidence signal, and thereafter counting the count value at a constant gradient from the initial value, and an input supplied in serial. An input pulse edge detecting means for detecting a rising or falling edge of a pulse, and a count value of the counter is taken as phase error data at the timing when an edge of the input pulse is detected by the input pulse edge detecting means, and the output is held. Latch means, a loop filter for removing unnecessary frequency components from the phase error data output and held by the latch means, and outputting the same as correction data corresponding to the phase error data, and a sign of the correction data of the loop filter To supply a value obtained by inverting the above as the initial value to the counter. Inverting means, and comparing means for comparing the correction data output from the loop filter with the count value of the counter, and when both match, supplying the match signal to the counter. It outputs a sign bit of the count value output from the CPU as an output pulse.

[Operation] According to the above configuration, the count value of the counter is always “0” at the rising or falling edge of the input pulse, that is, the phase error data is always “0”.
, And as a result, an output pulse that follows the rising or falling edge of the input pulse is obtained.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of one embodiment of the present invention.
In this figure, reference numeral 5 denotes an edge detection circuit for detecting a falling edge of an externally supplied input pulse Pi. When the falling edge is detected, an edge detection pulse ES having a fixed pulse width is latched. It is supplied to the clock input terminal CK of the circuit 6. Data latch circuit 6
Holds the count value output from the counter 8 when the edge detection pulse ES is supplied to the clock input terminal CK, and outputs the held content as phase error data θ. The counter 8 presets the initial value data supplied to the preset data input terminal D when a later-described coincidence signal EQ is supplied to the load input terminal L, and thereafter, every time a clock pulse φ of a fixed period arrives. An up-count is performed, and the count value is incremented by one.
The count value of the counter 8 is output from the data output terminal Q and supplied to the data latch circuit 6 and one input terminal A of the comparator 9. The comparator 9 compares data supplied to one input terminal A and data supplied to the other input terminal B, and outputs a match signal EQ from the output terminal Y when these data match. This coincidence signal EQ is supplied to the load input terminal L of the counter 8.

Reference numeral 10 denotes a loop filter that removes unnecessary frequency components from the phase error data θ output from the data latch circuit 6 and generates correction data e corresponding to the phase error data θ. It is composed of a DSP (Digital Signal Processor) which is a stored program type processor capable of real-time digital arithmetic processing. In this case, the loop filter 10 corrects the correction data e according to the positive or negative change of the phase error data θ.
Is changed based on a preset constant value. The correction data e output from the loop filter 10
Is supplied to the input terminal B of the comparator 9 and
The sign is inverted by the sign inversion circuit 11, and the inverted correction data e is supplied to the preset data input terminal D of the counter 8.

Next, the operation of the above-described embodiment will be described with reference to FIG.

First, an input pulse as shown in FIG.
When Pi is supplied, a falling edge of the input pulse Pi is detected by the edge detection circuit 5, and the edge detection circuit 5 outputs a detection pulse ES as shown in FIG. Each time this edge detection pulse ES is output,
The count value of the counter 8 is held by the data latch circuit 6, and the held content is supplied to the loop filter 10 as phase error data θ. In the loop filter 10, unnecessary frequency components are removed from the phase error data θ, and correction data e corresponding to the phase error data θ is generated. The correction data e is compared with the current count value of the counter 8 by the comparator 9, and when the correction data e and the count value match, a match signal
EQ is supplied to the load input terminal L of the counter 8. As a result, the count value of the counter 8 becomes equal to the correction data output from the loop filter 10, as shown in FIG.
_{e 1, e 2, e 3} , ... each time that coincides with the value -e ₁ by inverting their sign, -e _2, -e _3, preset ... to, after -e _1, ~
_{e 2, ~e 2 ~e 3,} -e 3 ~e 4, ... so on, repeating the sequential increase with a constant slope determined by the period of the clock pulse phi. Each time the input pulse Pi falls, the counter value of the counter 8 is held by the data latch circuit 6, and the held data is used as phase error data θ as shown in FIG. Supplied to On the other hand, the reproduction clock can be obtained by using the sign bit of the count value output from the counter 8 as the output pulse Po. By repeating the above-described operation, the operation is performed so that the count value always becomes “0” at the falling edge of the input pulse Pi, that is, the direction in which the phase error data θ always becomes “0”. An output pulse Po that follows the falling edge of Pi is obtained.

[Effects of the Invention] As described above, according to the present invention, the DPC and the DCO, which have conventionally been configured with separate counters, can be configured with a single counter. The counter value is held at the rising or falling edge of the digital input pulse, and the held content (multi-bit digital signal) is directly supplied to the loop filter as phase error data. Therefore, the carrier component of the input pulse generated by the DPC can be effectively removed, and the loop filter can be constituted by, for example, a DSP, which facilitates the design of the loop filter. As a result, a digital PL using a loop filter
The advantage that the advantages of the L circuit can be fully utilized and the cost of the entire digital PLL circuit can be reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a digital PLL circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of each part for explaining the operation of the embodiment, and FIG.
FIG. 3 is a block diagram illustrating a configuration of a PLL circuit. 5 ... edge detection circuit, 6 ... data latch circuit (latch means), 8 ... counter, 9 ... comparator (comparison means), 10 ... loop filter, 11 ... sign inversion circuit (sign inversion means).

Claims (1)

(57) [Claims] An initial value is preset in response to the arrival of a coincidence signal, and thereafter, a counter that counts a count value at a constant gradient from the initial value and a rising or falling edge of a serially supplied input pulse. Input pulse edge detecting means for detecting, at the timing when the edge of the input pulse is detected by the input pulse edge detecting means, latch means for taking in the count value of the counter as phase error data and holding output, and the latch means A loop filter that removes unnecessary frequency components from the output-held phase error data and outputs it as correction data corresponding to the phase error data; and a value obtained by inverting the sign of the correction data of the loop filter to the initial value. Sign inverting means for supplying to the counter as Comparing means for comparing the correction data output from the counter with the count value of the counter, and when both match, supplying a match signal to the counter; and a count value output from the counter. Digital signal characterized by outputting a sign bit as an output pulse
PLL circuit.