JPH05110427A - Phase locked loop circuit - Google Patents
Phase locked loop circuitInfo
- Publication number
- JPH05110427A JPH05110427A JP3102287A JP10228791A JPH05110427A JP H05110427 A JPH05110427 A JP H05110427A JP 3102287 A JP3102287 A JP 3102287A JP 10228791 A JP10228791 A JP 10228791A JP H05110427 A JPH05110427 A JP H05110427A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- output
- frequency comparator
- input signal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ディジタルシステムの
クロック供給回路に関し、さらに詳しくはディジタル信
号の位相同期回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock supply circuit for a digital system, and more particularly to a phase lock circuit for digital signals.
【０００２】[0002]
【従来の技術】ディジタル位相同期回路では、できるだ
け広い周波数引き込み範囲（プルインレンジ）を得るた
めに、位相比較部に位相周波数比較器が用いられる。位
相同期回路のプルインレンジは、位相周波数比較器の比
較特性によって電圧制御発振器の発振周波数範囲と一致
し、その発振周波数範囲内の周波数誤差であれば必ず位
相同期が得られる。2. Description of the Related Art In a digital phase synchronizing circuit, a phase frequency comparator is used in a phase comparing section in order to obtain a frequency pull-in range as wide as possible. The pull-in range of the phase-locked loop circuit matches the oscillation frequency range of the voltage-controlled oscillator due to the comparison characteristics of the phase-frequency comparator, and if there is a frequency error within the oscillation frequency range, phase-locking is always obtained.
【０００３】図３はこのような位相周波数比較器を用い
た従来のディジタル位相同期回路の回路図を示す。この
回路は位相周波数比較器３０７およびチャージポンプ回
路（ＣＰ）１０２、ローパスフィルタ（ＬＰＦ）１０
３、電圧制御発振器（ＶＣＯ）１０４で構成される。入
力信号と電圧制御発振器１０４の出力信号との周波数誤
差または位相誤差は位相周波数比較器３０７によって検
出され、チャージポンプ回路１０２およびローパスフィ
ルタ１０３によってアナログ電圧に変換される。このア
ナログ電圧は制御電圧として電圧制御発振器１０４の発
振周波数を制御する。入力信号と電圧制御発振器１０４
の出力信号の位相が一致すると、制御電圧は一定になっ
て位相同期が完了し、同期信号が得られる。同期ははじ
めに周波数引き込み（プルイン）過程によって電圧制御
発振器１０４の発振周波数を入力信号の周波数に近づけ
た後、位相引き込み（ロックイン）過程によって位相同
期を行うという２つの過程を経る。FIG. 3 is a circuit diagram of a conventional digital phase locked loop circuit using such a phase frequency comparator. This circuit includes a phase frequency comparator 307, a charge pump circuit (CP) 102, and a low pass filter (LPF) 10.
3. A voltage controlled oscillator (VCO) 104. A frequency error or a phase error between the input signal and the output signal of the voltage controlled oscillator 104 is detected by the phase frequency comparator 307, and converted into an analog voltage by the charge pump circuit 102 and the low pass filter 103. This analog voltage controls the oscillation frequency of the voltage controlled oscillator 104 as a control voltage. Input signal and voltage controlled oscillator 104
When the phases of the output signals of 1) match, the control voltage becomes constant, the phase synchronization is completed, and the synchronization signal is obtained. The synchronization first involves bringing the oscillation frequency of the voltage controlled oscillator 104 close to the frequency of the input signal by a frequency pull-in process, and then performing phase synchronization by a phase pull-in process.
【０００４】図４に従来の位相周波数比較器３０７の回
路図を示す。従来の位相周波数比較器３０７は、ＮＡＮ
Ｄゲート４０１，４０２，４０３，４０４，４０５およ
びＲＳフリップフロップ４０６，４０７からなる順序回
路である。図５にその動作を示す。図５（ａ）は図４の
回路の動作表を示している。図中の記号は図４の位相周
波数比較器３０７を参照し、Ｒ，Ｖは入力、Ｕt ，Ｄt
は現在の出力、Ｕt+1 ，Ｄt+1 は入力が変化した後の出
力、Ｌ，Ｈはそれぞれ論理レベル”Ｌ”，”Ｈ”、上向
きの矢印および下向きの矢印はそれぞれパルスの立ち上
がりエッジおよび立ち下がりエッジを示す。×は任意入
力を示す。この位相周波数比較器３０７は２つの入力信
号の立ち下がりエッジを検出し、その位相差に応じた信
号を出力する。例えばＲの位相がＶのそれよりも進む
と、出力Ｕが位相差だけＬになり、出力ＤはＨのままで
ある。また逆の場合、出力ＵはＨのままで、出力Ｄが位
相差だけＬなる。図５（ｂ）はＲがＶよりも位相が進ん
だ場合の位相周波数比較器３０７の動作波形を示してい
る。Ｒの位相がＶよりも少し進んだ入力信号を与える
と、位相周波数比較器３０７は図５（ａ）に従って、ま
ずＲの立ち下がりを検出して出力ＵをＨからＬにし、次
にＶの立ち下がりを検出して出力ＵをＬからＨに戻す。
このとき出力ＤはＨのままである。このようにして位相
周波数比較器３０７は位相差を検出する。FIG. 4 shows a circuit diagram of a conventional phase frequency comparator 307. The conventional phase frequency comparator 307 is a NAN.
It is a sequential circuit including D gates 401, 402, 403, 404, 405 and RS flip-flops 406, 407. The operation is shown in FIG. FIG. 5A shows an operation table of the circuit of FIG. The symbols in the figure refer to the phase frequency comparator 307 of FIG. 4, R and V are inputs, U t and D t
Is the current output, U t + 1 , D t + 1 is the output after the input is changed, L and H are logic levels “L” and “H”, respectively, and the upward and downward arrows indicate the rising edge of the pulse. Shows edges and falling edges. X indicates an arbitrary input. The phase frequency comparator 307 detects the falling edges of the two input signals and outputs a signal corresponding to the phase difference. For example, when the phase of R leads that of V, the output U becomes L by the phase difference, and the output D remains H. In the opposite case, the output U remains H and the output D becomes L by the phase difference. FIG. 5B shows an operation waveform of the phase frequency comparator 307 when the phase of R advances from V. When an input signal in which the phase of R is slightly advanced from V is given, the phase frequency comparator 307 first detects the falling edge of R and changes the output U from H to L according to FIG. The fall is detected and the output U is returned from L to H.
At this time, the output D remains H. In this way, the phase frequency comparator 307 detects the phase difference.
【０００５】[0005]
【発明が解決しようとする課題】従来のディジタル位相
同期回路では、入力信号パルスの立ち下がりでしか位相
比較が行われない（エッジトリガである）ため、ロック
イン過程において同期時間を長く必要とし、また同期信
号の位相ジッタが大きくなり得るという欠点があった。In the conventional digital phase synchronization circuit, since phase comparison is performed only at the falling edge of the input signal pulse (which is an edge trigger), a long synchronization time is required in the lock-in process, Further, there is a drawback that the phase jitter of the synchronization signal can be large.
【０００６】例えば図５（ｂ）の動作例でも明らかなよ
うに、ある時刻ｔで位相差を検出してから次の位相差の
検出まで入力信号のほぼ一周期待たなければならず、そ
の間は位相周波数比較器３０７は検出動作をしていな
い。従ってこの間に生じた電圧制御発振器１０４の発振
周波数の不安定性（温度変化や電源電圧の変動など）や
雑音などによって生じる位相誤差の補正ができないの
で、同期信号の位相ジッタが大きくなり得る。逆に入力
信号の位相変化に対する追従が同じ理由で緩慢になり得
ることがわかる。For example, as is clear from the operation example of FIG. 5B, it is necessary to expect almost one round of the input signal from the detection of the phase difference at a certain time t to the detection of the next phase difference, and during that period. The phase frequency comparator 307 is not detecting. Therefore, it is not possible to correct the phase error caused by the instability of the oscillation frequency of the voltage controlled oscillator 104 (temperature change, fluctuation of the power supply voltage, etc.) and noise that occur during this period, and the phase jitter of the synchronization signal may increase. On the contrary, it can be seen that the tracking of the phase change of the input signal can be slow for the same reason.
【０００７】本発明では従来よりも入力信号に対する位
相同期や追従が迅速に行われ、また電圧制御発振器１０
４の発振周波数の不安定や雑音などによる同期信号の位
相ジッタを減少させる位相同期回路を提供することを目
的とする。In the present invention, the phase synchronization and tracking of the input signal are performed more quickly than in the prior art, and the voltage controlled oscillator 10
It is an object of the present invention to provide a phase locked loop circuit that reduces phase jitter of a sync signal due to instability of oscillation frequency, noise, etc.
【０００８】[0008]
【課題を解決するための手段】本発明は、入力信号と同
期信号を入力とする位相比較部と、その出力を入力とす
るチャージポンプ回路と、その出力を入力とするローパ
スフィルタと、その出力を入力とする電圧制御発振器と
からなる位相同期回路において、前記位相比較部が入力
信号と同期信号をそのまま入力とする第１の位相周波数
比較器と、入力信号を反転する第１のインバータの出力
と同期信号を反転する第２のインバータの出力を入力と
する第２の位相周波数比較器と、第１の位相周波数比較
器の第１の出力と第２の位相周波数比較器の第１の出力
の論理積を出力とする第１のＡＮＤゲートと、第１の位
相周波数比較器の第２の出力と第２の位相周波数比較器
の第２の出力の論理積を出力とする第２のＡＮＤゲート
とからなる構成としている。DISCLOSURE OF THE INVENTION The present invention is directed to a phase comparing section having an input signal and a synchronizing signal as inputs, a charge pump circuit having its output as an input, a low-pass filter having its output as an input, and its output. In a phase-locked loop circuit composed of a voltage-controlled oscillator that receives as input, the phase comparator outputs a first phase frequency comparator that receives the input signal and the synchronization signal as they are, and an output of a first inverter that inverts the input signal. And a second phase frequency comparator that receives the output of the second inverter that inverts the synchronization signal, a first output of the first phase frequency comparator, and a first output of the second phase frequency comparator And a second AND gate that outputs the logical product of the second output of the first phase frequency comparator and the second output of the second phase frequency comparator. With a gate and To have.
【０００９】[0009]
【作用】ディジタル位相同期回路をこのような構成にす
ることによって、入力信号の立ち上がりと立ち下がりの
両方で電圧制御発振器１０４の発振出力との位相比較が
行われる。すると従来の立ち下がりのみで位相比較を行
っていた場合に比べて、同じ時間内に位相の補正回数が
２倍になるので、入力信号に対する位相同期や追従が迅
速に行われ、また電圧制御発振器１０４の発振周波数の
不安定性や雑音などによる同期信号の位相ジッタが減少
する。By configuring the digital phase locked loop circuit as described above, the phase comparison with the oscillation output of the voltage controlled oscillator 104 is performed at both the rising edge and the falling edge of the input signal. As a result, the number of times the phase is corrected is doubled in the same time as compared with the conventional case where the phase comparison is performed only at the falling edge, so that the phase synchronization and tracking of the input signal are performed quickly, and the voltage-controlled oscillator is used. Phase jitter of the synchronization signal due to instability of the oscillation frequency of 104, noise, etc. is reduced.
【００１０】[0010]
【実施例】次に図面を用いて本発明について詳細に説明
する。図１は本発明の位相同期回路の一実施例を示す回
路図である。この実施例は、位相比較部１０１とチャー
ジポンプ回路１０２、ローパスフィルタ１０３、電圧制
御発振器１０４で構成される。位相比較部１０１は入力
（Ｒ’，Ｖ’）即ち入力信号１１１と同期信号１１２を
そのまま入力（Ｒ1 ，Ｖ1 ）とする第１の位相周波数比
較器１０７と、Ｒ’を反転する第１のインバータ１０５
の出力とＶ’を反転する第２のインバータ１０６の出力
を入力（Ｒ2 ，Ｖ2 ）とする第２の位相周波数比較器１
０８と、第１の位相周波数比較器１０７の第１の出力Ｕ
1 と第２の位相周波数比較器１０８の第１の出力Ｕ2 の
論理積を出力Ｕ’とするＡＮＤゲート１０９と、第１の
位相周波数比較器１０７の第２の出力Ｄ1 と第２の位相
周波数比較器１０８の出力Ｄ2 の論理積を出力Ｄ’とす
る第２のＡＮＤゲート１１０からなる。The present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the phase locked loop circuit of the present invention. This embodiment comprises a phase comparator 101, a charge pump circuit 102, a low pass filter 103, and a voltage controlled oscillator 104. The phase comparison unit 101 includes a first phase frequency comparator 107 that receives the input (R ′, V ′), that is, the input signal 111 and the synchronization signal 112 as they are (R 1 , V 1 ), and a first phase frequency comparator 107 that inverts R ′. Inverter 105
And the output of the second inverter 106 that inverts V ′ as the input (R 2 , V 2 ), the second phase frequency comparator 1
08 and the first output U of the first phase frequency comparator 107
The AND gate 109 which outputs the logical product of 1 and the first output U 2 of the second phase frequency comparator 108 as the output U ′, the second output D 1 of the first phase frequency comparator 107 and the second output D 1 It comprises a second AND gate 110 which outputs the logical product of the output D 2 of the phase frequency comparator 108 as the output D ′.
【００１１】図１において、入力信号と電圧制御発振器
１０４の発振出力が位相比較部１０１に入力され、これ
らの入力の立ち上がりと立ち下がりで位相誤差が検出さ
れる。その位相誤差はチャージポンプ回路１０２および
ローパスフィルタ１０３によってアナログ電圧に変換さ
れて電圧制御発振器１０４の発振周波数の制御電圧とな
り、電圧制御発振器１０４はこの制御電圧に応じた周波
数で発振する。入力信号と電圧制御発振器１０４の発振
出力信号の位相が一致すると、電圧制御発振器１０４の
制御電圧は一定となって位相同期が完了し、同期信号が
得られる。In FIG. 1, the input signal and the oscillation output of the voltage controlled oscillator 104 are input to the phase comparator 101, and the phase error is detected at the rising and falling edges of these inputs. The phase error is converted into an analog voltage by the charge pump circuit 102 and the low-pass filter 103 and becomes a control voltage of the oscillation frequency of the voltage control oscillator 104, and the voltage control oscillator 104 oscillates at a frequency according to this control voltage. When the phases of the input signal and the oscillation output signal of the voltage controlled oscillator 104 match, the control voltage of the voltage controlled oscillator 104 becomes constant and phase synchronization is completed, and a synchronization signal is obtained.
【００１２】図２は本発明を構成する位相比較部１０１
の動作の一例を示す波形図である。入力（Ｒ’，Ｖ’）
の信号をそのまま入力する第１の位相周波数比較器１０
７の出力Ｕ1 ，Ｄ1 と、入力の信号をそれぞれ反転して
入力する第２の位相周波数比較器１０８の出力Ｕ2 ，Ｄ
2 とをそれぞれについて論理積をとることによって、出
力（Ｕ’，Ｄ’）にＲ’とＶ’の立ち上がりと立ち下が
りの両方で位相比較した結果が出力される。位相同期は
この出力信号によって、電圧制御発振器１０４の発振周
波数が補正されて実現されるため、位相誤差の検出の回
数が同じ時間内に従来の回路に比べて２倍になった分ロ
ックイン過程が迅速に行われる。このことによって従来
よりも入力信号に対する位相同期や追従が迅速に行わ
れ、また電圧制御発振器１０４の発振周波数の不安定性
や雑音などによる同期信号の位相ジッタを減少させるこ
とが可能になる。FIG. 2 shows a phase comparison section 101 which constitutes the present invention.
6 is a waveform chart showing an example of the operation of FIG. Input (R ', V')
Phase frequency comparator 10 for directly inputting the signal of
7 outputs U 1 and D 1 and outputs U 2 and D of the second phase frequency comparator 108 for inverting and inputting the input signals, respectively.
By logically ANDing 2 and 2 , the result of phase comparison at both the rising and falling edges of R'and V'is output at the output (U ', D'). Since the phase synchronization is realized by correcting the oscillation frequency of the voltage controlled oscillator 104 by this output signal, the number of times of detecting the phase error is doubled as compared with the conventional circuit within the same time, so that the lock-in process is performed. Is done quickly. As a result, the phase synchronization and tracking of the input signal can be performed more quickly than in the conventional case, and the phase jitter of the synchronization signal due to the instability of the oscillation frequency of the voltage controlled oscillator 104 and noise can be reduced.
【００１３】以上、実施例をもって本発明を説明した
が、本発明はこの実施例のみに限定されるものではな
い。例えば、位相比較部に用いる位相周波数比較器は入
力パルスの立ち下がりエッジを検出するものを例にとっ
て説明しているが、立ち上がりエッジを検出するものを
用いても本発明が適用できることは明らかである。The present invention has been described above with reference to the embodiment, but the present invention is not limited to this embodiment. For example, the phase frequency comparator used in the phase comparison unit has been described taking the case of detecting the falling edge of the input pulse as an example, but it is obvious that the present invention can be applied to the case of using the one detecting the rising edge. ..
【００１４】[0014]
【発明の結果】本発明によると、従来よりも入力信号に
対する位相同期や追従が迅速に行われ、また電圧制御発
振器の発振周波数の不安定性や雑音などによる位相ジッ
タを減少させた、安定な同期信号を得ることができる。According to the present invention, phase synchronization and tracking of an input signal are performed more quickly than in the past, and stable synchronization is achieved by reducing phase jitter due to instability of oscillation frequency of a voltage controlled oscillator and noise. You can get a signal.
【図１】本発明の第１の実施例を示す位相同期回路の回
路図である。FIG. 1 is a circuit diagram of a phase locked loop circuit showing a first embodiment of the present invention.
【図２】本発明で用いた位相比較部の動作波形図であ
る。FIG. 2 is an operation waveform diagram of a phase comparison unit used in the present invention.
【図３】従来の位相同期回路の回路図である。FIG. 3 is a circuit diagram of a conventional phase locked loop circuit.
【図４】従来の位相比較部およびその動作を示す図であ
る。FIG. 4 is a diagram showing a conventional phase comparison unit and its operation.
１０１ 位相比較部 １０２ チャージポンプ回路（ＣＰ） １０３ ローパスフィルタ（ＬＰＦ） １０４ 電圧制御発振器（ＶＣＯ） １０５，１０６ インバータ １０７ 第１の位相周波数 １０８ 第２の位相周波数比較器 １０９，１１０，４０１〜４０５ ＡＮＤゲート ４０６，４０７ ＲＳフリップフロップ １１１，２０１，２０２ 入力端子 １１２，２０３，２０４ 出力端子 101 Phase Comparing Unit 102 Charge Pump Circuit (CP) 103 Low Pass Filter (LPF) 104 Voltage Controlled Oscillator (VCO) 105, 106 Inverter 107 First Phase Frequency 108 Second Phase Frequency Comparator 109, 110, 401-405 AND Gate 406,407 RS flip-flop 111,201,202 Input terminal 112,203,204 Output terminal
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【手続補正書】[Procedure amendment]
【提出日】平成４年１０月５日[Submission date] October 5, 1992
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Name of item to be corrected] Brief description of the drawing
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の第１の実施例を示す位相同期回路の回
路図である。FIG. 1 is a circuit diagram of a phase locked loop circuit showing a first embodiment of the present invention.
【図２】本発明で用いた位相比較部の動作波形図であ
る。FIG. 2 is an operation waveform diagram of a phase comparison unit used in the present invention.
【図３】従来の位相同期回路の回路図である。FIG. 3 is a circuit diagram of a conventional phase locked loop circuit.
【図４】従来の位相比較部の回路図である。FIG. 4 is a circuit diagram of a conventional phase comparison unit.
【図５】従来の位相比較部の動作を示す図である。FIG. 5 is a diagram showing an operation of a conventional phase comparison unit.
【符号の説明】 １０１ 位相比較部 １０２ チャージポンプ回路（ＣＰ） １０３ ローパスフィルタ（ＬＰＦ） １０４ 電圧制御発振器（ＶＣＯ） １０５，１０６ インバータ １０７ 第１の位相周波数 １０８ 第２の位相周波数比較器 １０９，１１０，４０１〜４０５ ＡＮＤゲート ４０６，４０７ ＲＳフリップフロップ １１１，２０１，２０２ 入力端子 １１２，２０３，２０４ 出力端子[Description of Reference Signs] 101 phase comparison unit 102 charge pump circuit (CP) 103 low pass filter (LPF) 104 voltage controlled oscillator (VCO) 105, 106 inverter 107 first phase frequency 108 second phase frequency comparator 109, 110 , 401-405 AND gate 406, 407 RS flip-flop 111, 201, 202 Input terminal 112, 203, 204 Output terminal
Claims (1)
較部と、その出力を入力とするチャージポンプ回路と、
その出力を入力とするローパスフィルタと、その出力を
入力とする電圧制御発振器とからなる位相同期回路にお
いて、前記位相比較部が入力信号と同期信号をそのまま
入力とする第１の位相周波数比較器と、入力信号を反転
する第１のインバータの出力と同期信号を反転する第２
のインバータの出力を入力とする第２の位相周波数比較
器と、第１の位相周波数比較器の第１の出力と第２の位
相周波数比較器の第１の出力を入力とする第１のＡＮＤ
ゲートと、第１の位相周波数比較器の第２の出力と第２
の位相周波数比較器の第２の出力を入力とする第２のＡ
ＮＤゲートとからなることを特徴とする位相同期回路。1. A phase comparison unit having an input signal and a synchronization signal as inputs, and a charge pump circuit having an output thereof as an input,
In a phase locked loop circuit comprising a low-pass filter having the output as an input and a voltage controlled oscillator having the output as an input, the phase comparator includes a first phase frequency comparator having an input signal and a sync signal as they are as inputs. , An output of the first inverter for inverting the input signal and a second for inverting the synchronization signal
Second phase frequency comparator which receives the output of the inverter of the above, and a first AND which inputs the first output of the first phase frequency comparator and the first output of the second phase frequency comparator
A gate, a second output of the first phase frequency comparator and a second output of the first phase frequency comparator.
Of the second A having the second output of the phase frequency comparator of
A phase locked loop circuit comprising an ND gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3102287A JP2811994B2 (en) | 1991-05-08 | 1991-05-08 | Phase locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3102287A JP2811994B2 (en) | 1991-05-08 | 1991-05-08 | Phase locked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05110427A true JPH05110427A (en) | 1993-04-30 |
| JP2811994B2 JP2811994B2 (en) | 1998-10-15 |
Family
ID=14323399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3102287A Expired - Lifetime JP2811994B2 (en) | 1991-05-08 | 1991-05-08 | Phase locked loop |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2811994B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0606779A2 (en) * | 1992-12-30 | 1994-07-20 | Digital Equipment Corporation | Improved phase comparator |
| WO1999048195A1 (en) * | 1998-03-13 | 1999-09-23 | Telefonaktiebolaget Lm Ericsson | Phase detector |
| US6700414B2 (en) | 2001-11-26 | 2004-03-02 | Renesas Technology Corp. | Phase comparator accurately comparing phases of two clock signals and clock generation circuit employing the same |
| US6906551B2 (en) | 1996-11-26 | 2005-06-14 | Renesas Technology Corp. | Semiconductor integrated circuit device |
| US7012476B2 (en) | 2003-03-20 | 2006-03-14 | Seiko Epson Corporation | Voltage-controlled oscillator, clock converter, and electronic device |
| WO2009044444A1 (en) * | 2007-10-01 | 2009-04-09 | Fujitsu Limited | Clock generating device and clock generating method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60173927A (en) * | 1984-02-20 | 1985-09-07 | Nissin Electric Co Ltd | Pll circuit |
| JPS62230225A (en) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | Phase comparator circuit |
| JPH0443716A (en) * | 1990-06-08 | 1992-02-13 | Nec Corp | Frequency multipying circuit |
-
1991
- 1991-05-08 JP JP3102287A patent/JP2811994B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60173927A (en) * | 1984-02-20 | 1985-09-07 | Nissin Electric Co Ltd | Pll circuit |
| JPS62230225A (en) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | Phase comparator circuit |
| JPH0443716A (en) * | 1990-06-08 | 1992-02-13 | Nec Corp | Frequency multipying circuit |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0606779A3 (en) * | 1992-12-30 | 1995-05-24 | Digital Equipment Corp | Improved phase comparator. |
| US5539345A (en) * | 1992-12-30 | 1996-07-23 | Digital Equipment Corporation | Phase detector apparatus |
| EP0606779A2 (en) * | 1992-12-30 | 1994-07-20 | Digital Equipment Corporation | Improved phase comparator |
| US6906551B2 (en) | 1996-11-26 | 2005-06-14 | Renesas Technology Corp. | Semiconductor integrated circuit device |
| US7518404B2 (en) | 1996-11-26 | 2009-04-14 | Renesas Technology Corp. | Semiconductor integrated circuit device |
| US7397282B2 (en) | 1996-11-26 | 2008-07-08 | Renesas Technology Corp. | Semiconductor integrated circuit device |
| US7112999B2 (en) | 1996-11-26 | 2006-09-26 | Renesas Technology Corporation | Semiconductor integrated circuit device |
| US6198355B1 (en) | 1998-03-13 | 2001-03-06 | Telefonaktiebolaget Lm Ericsson (Publ) | Dual edge-triggered phase detector and phase locked loop using same |
| AU760201B2 (en) * | 1998-03-13 | 2003-05-08 | Unwired Planet, Llc | Phase detector |
| GB2335322B (en) * | 1998-03-13 | 2002-04-24 | Ericsson Telefon Ab L M | Phase detector |
| JP2002507850A (en) * | 1998-03-13 | 2002-03-12 | テレフオンアクチーボラゲツト エル エム エリクソン（パブル） | Phase detector |
| WO1999048195A1 (en) * | 1998-03-13 | 1999-09-23 | Telefonaktiebolaget Lm Ericsson | Phase detector |
| US6700414B2 (en) | 2001-11-26 | 2004-03-02 | Renesas Technology Corp. | Phase comparator accurately comparing phases of two clock signals and clock generation circuit employing the same |
| US7012476B2 (en) | 2003-03-20 | 2006-03-14 | Seiko Epson Corporation | Voltage-controlled oscillator, clock converter, and electronic device |
| WO2009044444A1 (en) * | 2007-10-01 | 2009-04-09 | Fujitsu Limited | Clock generating device and clock generating method |
| JPWO2009044444A1 (en) * | 2007-10-01 | 2011-01-27 | 富士通株式会社 | Clock generating device, electronic device, and clock generating method |
| JP4669563B2 (en) * | 2007-10-01 | 2011-04-13 | 富士通株式会社 | Clock generating device, electronic device, and clock generating method |
| US7986176B2 (en) | 2007-10-01 | 2011-07-26 | Fujitsu Limited | Clock generating apparatus and clock generating method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2811994B2 (en) | 1998-10-15 |
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