JPS62230225A - Phase comparator circuit - Google Patents

Abstract

PURPOSE:To decrease the ripple by providing a signal leading or retarded to/ from an input signal by a half of the width of a synchornizing signal and charging/discharging a filter depending on the phase difference between the edge of the signal and the edge of the synchronizing signal. CONSTITUTION:A horizontal synchronizing pulse having a pulse width tw is inputted to a terminal 14 and frequency division signals A-C to be synchronized are inputted to terminals 15-17. The frequency division signal B is retarded by the pulse width tw to the frequency division signal A and the frequency division signal C is the inverse of the signal A led by the pulse width tw. Thus, when the edge of the signal A is at the center of the horizontal synchronizing pulse, the fall of the signal B and the rise of the signal C are overlapped with the edge of the reference signal, no charge/discharge is applied and the ripple near the center is almost eliminated.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is designed to reduce the amplitude of triangular ripples appearing at the end of a filter in a phase-locked loop (hereinafter referred to as PLL) type frequency multiplier circuit. Related to phase comparator circuit.

(Prior Art) It is known that a PLL is used to implement a frequency multiplier circuit that obtains an oscillation output with a frequency that is an integer multiple of a reference signal in an electronic circuit, and FIG. 8 is a block diagram showing an example thereof. be.

In FIG. 8, the frequency-divided output A of a voltage controlled oscillator (hereinafter referred to as ) is added to a phase comparator 3, and the phase is compared with a reference signal R input from an input terminal 1. The output is passed through a low pass filter (hereinafter referred to as LPF) 4 to obtain a DC voltage.

This DC voltage is applied to vco5. By applying feedback and controlling the oscillation frequency of vcos,
An oscillation output having a frequency N times the oscillation frequency of the reference signal is taken out from the output terminal 2, and is widely used in electronic circuits in general.

Color signal processing for consumer VTRs (video tape recorders) requires a frequency multiplication circuit called AFC that generates a low-frequency conversion signal that is phase-synchronized with the television signal, and is generally configured with a PLL like the one above. That's what I do.

The AFC circuit generates a low-frequency conversion signal with the same amount of jitter components as the jitter component in the recorded/reproduced color signal, and is important for removing the jitter component of the primary color signal when converting the frequency of the recorded/reproduced color signal. It has a role.

FIG. 9 is a basic circuit diagram of a conventional phase comparator and filter circuit used in this AFC circuit. This ninth
In the figure, AND gates 101 and 102 and an inverter constitute a phase comparator, and a capacitor Ci and a resistor R8 constitute a filter.

A horizontal synchronizing pulse R is input as a reference signal to the terminal 7, and a branch signal A of an oscillation output for synchronizing with the horizontal synchronizing pulse R is input to the terminal 8.

This frequency-divided signal A is shown in FIG. 10(1), and the horizontal synchronizing pulse R is shown in FIG. 10(b).

As is clear from Fig. 10, when the horizontal synchronizing pulse R is rHJ, the detector is activated and the fall of the branch signal A is 9.
Synchronization is performed with a phase relationship such that the horizontal synchronization/4' pulse R is located near the center of the pulse.

That is, the AND gate 101 calculates the logical product of the horizontal synchronizing pulse R and the branch signal A, and the inverted frequency division signal obtained by inverting the branch signal R by the inverter 103 and the horizontal synchronizing/4' pulse R.
The logical product of is taken by AND dart 102.

At this time, when the phase of the branch signal A is ahead of the phase of the horizontal synchronizing pulse R, the output R-
The generation time of X is longer than the generation time of output RA of ANDf-)101. This and f-) J OX,
The outputs RA and RA of the AND gate 102 control the opening and closing of the switches 11 and 12, respectively, and the output RA of the AND gate 102 is the output RA of the AND gate 101.
If the occurrence time is longer, the time during which the switch 12 is closed becomes longer than the time during which the switch 11 is closed.

Figure 1O (C) and Figure 10 (d) are respectively switch 1
1 and 12, and the shaded portion indicates the time during which it is closed.

In this way, when the switch 12 is closed for a longer time than the switch 11, the voltage at the filter end 10 decreases.

Conversely, when the phase of the branch signal A lags the phase of the horizontal synchronization signal R, the output R-A of the AND gate 101
The generation time of the output RA of the AND gate 102 is longer than the generation time of the output RA of the AND gate 102, and the time the switch 11 is closed is longer than the time the switch 12 is closed. As a result, the voltage at the filter end 10 increases.

That is, as the time that the switch 11 is closed increases, the control voltage increases as shown in FIG. 10(e), and the oscillation frequency increases as shown in FIG. 10(f).

Therefore, if the characteristics of the VCO 5 in FIG. 8 are selected as shown in FIG. 11, the PLL works to eliminate the phase difference, and the branch signal A becomes
Mouth and lisp with the phase relationship shown in the center of the figure.

FIG. 12 shows this state, and FIG. 12C) to FIG. 12(c) show the divided signal A, the horizontal synchronization t'P pulse R, and the voltage vc at the filter end 10, respectively. Figures 12(d) to 12(1) are similar to Figures 12(a) to 1.
FIG. 2 is an enlarged view of the part in FIG. 2(c).

Terminal 9 in FIG. 9 is at a fixed voltage V. For simplicity, the voltage vc at the filter end 10 is constant (actually, as shown in FIG. 12(i), a triangular ripple is superimposed on the filter end 10, but This Rizzol amplitude is sufficiently large compared to V.-vc).

Now, branch signal A (Figure 12 (&), Figure 12 (d))
The falling edge of is the horizontal synchronizing pulse R (Fig. 12).

It is assumed that they are synchronized in a phase relationship that is advanced by Δt with respect to the center of FIG. 12(e)). During the generation period of the output R-A of the andeto 101, the switch 11 is closed (see FIG. 12).
f) ), current I to the filter end. The switch 12 is closed during the generation period of the output R-A of the AND-DART 102, and the stain flow I flows from the filter end 10. is pulled out from capacitor C1 and connected to ground.

Furthermore, the period during which horizontal synchronization noise R occurs (Fig. 12(b)
) #Figure 12 (e)) shows that the switch 13 is closed due to this horizontal synchronization/arm pulse R, and the current value (vo-vc) A
1 (Fig. 12(k)) flows from terminal 9 to filter end 1.
Flows into 0.

All switches 11 to 13 are open during periods other than when the horizontal synchronization noise R is occurring, and the filter end 10 is open.
The voltage vc is held by the capacitor C8.

As a result, the capacitor C8 becomes -V before the horizontal synchronizing pulse R. )
/R1, and the filter end 10 has a discharge voltage of 1
) A triangular ripple appears.

Since we are currently considering a locked state, the voltage v(,) at the filter terminal 10 before and after detection is equal (the sum of the currents flowing into the filter terminal 10 in one cycle is equal to the sum of the currents drawn out), so the following formula is obtained. is established.

Solving this for vc gives the amplitude of the triangular ripple Δvc, □. When is Δt (tv, the detection stupidity μ of this detector is...(4).

However, the circuit shown in FIG. 9 has a problem in that ripples appear at the filter end 10. This filter end 10
Since is the control voltage of vCO, the presence of a ripple here means that the oscillation frequency during this period is different from the period when there is no ripple.

For example, when using the circuit shown in Figure 9 for the phase comparator and filter and detecting the falling edge of the branch signal A, if the characteristics of the VCO are selected as shown in Figure 11, the horizontal synchronizing pulse R will be rHJ.
During the period , the oscillation frequency of the VCO is higher than during the rLJ period.

However, since the divided signal A for phase comparison is obtained by dividing the oscillation output, the frequency information is averaged, and the correct frequency to be obtained is the voltage vc at the filter end 10.
The frequency corresponds to the smoothed voltage.

Therefore, the obtained output frequency is higher than the correct frequency during the period when the horizontal synchronization/4' pulse R is rHJ, and lower than the correct frequency during the period when the horizontal synchronization/4' pulse R is rLJ. In the circuit of FIG. 9, the error voltage at the filter end 10 corresponding to this frequency error is equal to the voltage obtained by smoothing the triangular ripple at the filter end 10.

This is Δvcerr. . If it is 1, TΔvcerroer ””A・tw・ΔvCp e
ak (approximation is tw) when Δt).

All the burst signals and video color signals in the VTR color signal exist during the period in which the horizontal synchronizing pulse R is rLJ, but the low frequency conversion frequency during this period has an error from the correct frequency for the above-mentioned reason.

For this reason, conventionally, an AF using the circuit shown in FIG. 9 as a phase comparator
In the C circuit, there is a problem in that a hue shift occurs in the reproduced color signal.

To solve this problem, pull ΔvCpeak
To do this, from equation (3), (1) current I.

There are two possible methods: (2) increasing the capacitance C8; however, (1) reduces the detection sensitivity compared to formula (4). In addition, (2) has the disadvantage that the loop response in high frequencies becomes poor and the performance of removing jitter at relatively high frequencies becomes poor.

That is, the phase comparator shown in FIG. 9 obtains a control voltage by converting the phase difference between the horizontal synchronizing pulse R, which is a reference signal, and the branch signal A, which is an oscillation output, into the charging and discharging time ratio of the filter end 10. Therefore, it is inevitable that a triangular ripple due to charging and discharging of the current is superimposed on the filter end 10. In particular, from FIG. As shown, the center of detection (when t=o) Δ
vCpeak becomes maximum.

However, in a PLL loop, the detection sensitivity is generally set very high, so in the locked state,
The phase difference Δt is sufficiently small compared to the pulse width tw. Therefore, the phase comparator is operated near the maximum value of the ripple amplitude ΔvCpeak.

(Problems to be Solved by the Invention) This invention solves the drawbacks of the above-mentioned conventional technology in that a triangular wave ripple voltage is superimposed on the filter end, and the detection sensitivity that causes a hue shift in the reproduced color signal. This was done in order to eliminate the disadvantage of causing a reduction in jitter and deteriorating the removal performance of relatively high frequency jitter. It is an object of the present invention to provide a phase comparator circuit that can reduce the amplitude of the ripple of the triangular wave that appears and reduce the error voltage.

[Structure of the Invention] (Means for Solving the Problems) The phase comparator circuit of the present invention compares two test wave signals with the same frequency shifted by a time close to or equal to the pulse width of the reference signal. A circuit is provided to detect the phase difference between normal rotation and inversion of the reference signal.

(Function) This invention detects the phase difference with the rising edge of one division signal at the rising edge of the reference signal, and detects the phase difference with the falling edge of the other divided signal at the falling edge of the reference signal. The charging current at the filter end is controlled using the detection output of this measured phase difference.

(Example) Hereinafter, an example of the phase comparator circuit of the present invention will be described based on the drawings. FIG. 1 is a circuit diagram of one embodiment. In FIG. 1, a horizontal synchronizing pulse R having a pulse width tW is input to a terminal 14 as a reference signal, and a terminal 15
, -17 are provided with frequency-divided signals A, B, and C of the oscillation output, respectively. These branch signals A-C
is a signal to be synchronized with the horizontal synchronizing pulse R.

The horizontal synchronizing pulse R is directly introduced into the first input terminal of the AND gate 201 and the second input terminal of the AND gate 203. , , 204 and 205, the switch 22 is turned on.

In addition, the frequency-divided signal A is
end, and through the inverter 211, the ANDR end 204
It is designed to be input to the third input terminal of.

The frequency-divided signal B is input to the second input terminal of the AND dart 202, and is also introduced to the first input terminal of the AND dart 203 via the inverter 209.

The frequency-divided signal C is introduced into the second input terminal of the AND gate 201 through the first input terminal of the AND gate 202 and the inverter 208.

The output terminal of AND gate 201 is the first one of 206. The output terminal of the AND gate 202 is connected to the second input terminal of the AND gate 204, and the output terminal of the AND gate 203 is connected to the first input terminal of the OR gate 207. .

Also, the output terminal of the AND gate 205 is the ORDART 207
is connected to the second input terminal of. Andoo),? 0
The output terminal of 4 is connected to the second input terminal of OR gate 206.

The output signal from the OR gate 206 turns on the switch 20, and the output from the OR gate 207 turns on the switch 21.

Switches 20 and 21 are connected in series between the power supply and ground, and a capacitor C3 is connected in parallel to switch 20, one end of which is connected to terminal 18 via switch 22 and resistor R8. A filter is formed by the resistor R8 and the capacitor C1.

Next, the operation of the embodiment shown in FIG. 1 will be explained. A horizontal synchronizing pulse with a pulse width tW is input to the terminal 14, and frequency-divided signals AC for synchronizing with the horizontal synchronizing pulse R are input to the terminals 15 to 17, respectively.

These branch signals A-C are shown in Figure 2 (,) to Figure 2 (C).
The horizontal synchronizing pulse R is shown in Fig. 2 (
d). This figure 2 (=) - figure 2 (d)
As is clear, the fall of the division signal B is delayed by tw/2 with respect to the fall of the frequency-divided signal A.

Furthermore, it is assumed that there is a phase relationship in which the rising edge of the divided signal C leads the falling edge of the divided signal A by tw/2 with respect to the falling edge of the divided signal A.

ANDGATE 201-205, OAGU) 206.

207, in the phase comparator constituted by inverters 208 to 211, when the logic of R+B-C by the horizontal synchronizing pulse R and the frequency-divided signals B and C is rHJ, the detector operates and the fall of the branch signal A is synchronized. are located near the center of the pulse of horizontal synchronization/4' pulse R.

Is the falling edge of the branch signal A the A of the horizontal synchronizing pulse R? When the clock moves toward the center line of the pulse, the logical product R-B of the horizontal synchronizing pulse R and the frequency-divided signal B and the horizontal synchronizing pulse R
The logical sum of the logical product π・A−B−C of , the switch 21 is closed as shown by diagonal lines in FIG. 2(f).

By closing this switch 21, the filter end 19
The voltage vc decreases as the charge on capacitor C2 is discharged through switch 21.

Conversely, when the fall of the branch signal A is delayed with respect to the center line of the water synchronous pulse R, the logical product R-C of the horizontal synchronization signal R and each frequency division signal A-C and the toss The logical sum of B-C, that is, (R-A-B-C+Ro
C) is output from the OR gate 206.

While the output of the OR gate 206 is being output, this output causes the switch 20 to
closes. By closing this switch 20, the power supply I. charges capacitor C8 through switch 20,
The voltage vc of the filter 19 increases.

That is, the falling edge of the branch signal B is the horizontal synchronizing pulse R.
If the falling edge of
-B-C, if the rising edge of the frequency-divided signal C is ahead of the rising edge of the horizontal synchronizing pulse R, the phase difference is R-
A-B-C can be detected and the two can be distinguished.

Therefore, the polarity of the output circuit is selected so that if R-B+R-A-B-'C is detected, the phase is delayed, and if R-C+R-A@B@C is detected, the phase is advanced, and the phase is compared. Realize the vessel.

In particular, if the time difference between the rising edge of the branch signal C and the falling edge of the branch signal B is set equal to the time difference between the rising edge of the horizontal synchronizing pulse R and the falling edge of the horizontal synchronizing pulse R, the horizontal synchronizing pulse R The time difference between the rising edge and the rising edge of the branch signal C and the time difference between the falling edge of the horizontal synchronizing pulse R and the falling edge of the branch signal B are equal to the time difference, and as a result, as mentioned above, the charging and discharging current at the center of detection is The ripple at the filter end near the center of detection can be almost eliminated.

In addition, even if the time difference between the rise of the division signal C and the fall of the frequency-divided signal B and the time difference of 9 between the rise and fall of the horizontal synchronization pulse R is different, it operates stably as a phase comparator regardless of the magnitude relationship between the two. The smaller the difference between the two time differences, the more the filter end sudsol can be reduced.

Therefore, if the characteristics of vCO5 in the PLL shown in FIG. 8 are selected as shown in FIG. It locks with respect to R with the phase relationship shown in the center part of Figure 2, and the oscillation frequency changes as shown in Figure 2 (h) in response to the control voltage in Figure 2 (g). Become.

Figure 3 shows an enlarged view of the voltages and currents at various parts of the phase comparator shown in Figure 1 in this locked state, and Figures 3(,) to 3(d) are shown in Figure 2(-). ) to FIG. 2(d), and FIG. 3(,) is the voltage vc at the filter end 19.
Figure 3 (f) to Figure 3 (c) are Figure 3 (2L).
- The part shown in Fig. 3 (@) is shown enlarged.

That is, Fig. 3(f) to Fig. 3(i) are Fig. 3(-)
- Corresponding to Fig. 3(d), Fig. 3←) corresponds to Fig. 3(d).
-), and FIGS. 3(j) to 3(g) respectively show the operating states of the switches 20 to 22.

As shown in the center of FIG. 2, when the PLL is locked, terminal 18 is at a fixed voltage V. For simplicity of explanation, the voltage vc at the filter ends 8, 19 is assumed to be constant. In reality, as shown in Figure 3 ←), a triangular wave ripple is superimposed on the filter end 19, but the amplitude of this ripple is sufficiently small compared to (Vo-V, ). .

Assume now that the fall of the branch signal A is synchronized in a phase relationship in which the falling edge of the branch signal A is advanced by Δt with respect to the center line of the horizontal synchronizing pulse R. At this time, as mentioned above, or gate 2
During the period of the output (R-B+R-A, B-C) of 07, the switch 21 is closed and the charge of the capacitor C1 is discharged from the filter end 19 (that is, the current is drawn out).

Furthermore, while the horizontal synchronizing pulse R is being input to the terminal 14, the switch 22 is turned on by this horizontal synchronizing pulse R.
) As flows through the terminal 18 and into the filter 19.

During other periods, all the switches 20 to 22 are open, and the voltage vc at the filter end 19 is held by the capacitor C3.

As a result, the capacitor C8 is discharged in the current flow for the time Δt immediately before the leading edge of the horizontal sync/4' pulse R ("fE - A - B - C), and the majority of the Noculus is discharged for the time tW - Δt ("fE - A - B - C). R-B) is charged with a current (vo-v, )7m, and is discharged with a current I.-(Vo Vc)As during the time Δt immediately before the trailing edge of the /4' pulse. As a result, ripples Al and A2 with waveforms as shown in FIG. 3 appear at the filter end 19.

Since we are now considering a closed state, the voltage at the filter end before and after detection is equal (the sum of the currents flowing into the filter end 19 in one cycle is equal to the sum of the currents drawn out from the filter end 19), so the following formula holds true. .

Solving this for gold vc, vc = v6 2 Rg I. , j t
-(5) tw Amplitude Δvc of the triangular ripple. ,4. ΔvCpea
k2 is when Δt is 0, respectively.

Further, the detection sensitivity of this phase comparator is equal to the detection sensitivity of the phase comparator shown in FIG. 10 according to equation (5).

Based on equations (6) and (7), ripple amplitude ΔvCpeak1 'ΔvCpea of filter end J9 with respect to Δt
k2 is shown in FIG. As can be seen from this Figure 13, Δ
When t is sufficiently small with respect to tη, the fill end 19 of the circuit in FIG. 1, fyv amplitude ΔvCpeak1'
ΔvCpeak2 is sufficiently small compared to the ripple amplitude 7vcak at the filter end 10 of the circuit shown in FIG. 10, and there is a large improvement effect.

Generally, in a PLL loop, the detection sensitivity is set very high, so that tw)Δt holds true in the locked state. Therefore, the improvement effect is very large.

Furthermore, the ripple waveform at the filter end 19 of the circuit shown in FIG. 1 has two triangular ripples A1. Since this holds true for A2, these cancel each other out, and the error voltage at the filter end 19 is significantly reduced.

Now, if the areas of ripples A1 and A2 are calculated, they will be respectively. Since the error voltage at the filter end 19 corresponding to the frequency error is equal to the voltage obtained by smoothing the ripple at the filter end 19 in one cycle, this is Δvcerr. 1, then T#ΔV = 12-AI c, @ r r Or.

Generally, when PLL Luso is in the state of
Since Δt, Δvc6rror expressed by α9 formula
is very small compared to ΔV expressed by equation (0).

CI! 1rFor Therefore, the oscillation frequency error of the optical system using the phase comparator of FIG. 1 of the present invention is extremely small compared to the conventional system using the phase comparator of FIG. 10.

In addition, the PLL using the phase comparator shown in FIG.

When the current is in this state, the charging/discharging current I0 to the filter end 19 is
Since the current flows only for a very short period of Δt, the current consumption can be reduced compared to the case where the phase comparator shown in FIG. 9 is used.

FIG. 4 is a circuit diagram showing a second embodiment of the invention.

In FIG. 4, parts that are the same as those in FIG. 1 are given the same reference numerals, and their explanation will be omitted, and only the parts that are different from FIG. 1 will be described.

In this Figure 4, an AND gate 2 is newly added to the circuit in Figure 1.
12 is added and the switch 22 is controlled by the output of this AND gate 212.
By adding the horizontal synchronization pulse R and the output of the AND gate 202 to
C is obtained, and this logical product R-B-C causes the switch 22
We are trying to control the

The signals of each part in FIG. 4 are shown in FIG. This figure 5(,)~Figure 5←) is shown in Figure 3(,)~Figure 3←)
Correspondingly, the current flowing through the switch 22 is almost equal to FIG. (Switch 22
) (Fig. 5 (1)) differs in that there are logical outputs R-B and C of the AND dirt 212. In this way, the two triangular ripples AJ and A4 appearing at the filter end 19 (Fig. 5) (X) have the same area, and the error voltage at the filter end 19 corresponding to the frequency error becomes completely zero. That is, there is no frequency error at all.

Generally, the detection sensitivity of the phase comparator is set very high, so it can be regarded as Δt-Q, and in the circuit of FIG. 1, as is clear from equation (G), Δv6. Y? , rl
) Σ0, most of the effects of this invention can be achieved with the circuit shown in FIG. However, when using a phase comparator with low detection sensitivity, the circuit shown in FIG. 4 becomes effective.

FIG. 6 is a circuit diagram showing a third embodiment of the invention.

In the case of FIG. 6, the horizontal synchronizing pulses R, which are input multiple times through the terminal 32, are introduced to the first input terminals of the AND gates 202 and 203, and to the first input terminal of the AND gate 212, respectively.

In addition, two divided signals A and B are used, and the divided signal A is input from the terminal 33 to the third input terminal of the AND gate 202 and the first input terminal of the AND gate 214, and is passed through the inverter 209 to the AND gate 202 and the first input terminal of the AND gate 214. Gate 201 first
It is designed to be input to the input terminal, the third input terminal of the AND-DART 203.

The branch signal B is inputted from the terminal 34 to the second input terminal of the AND gate 214 and the second input terminal of the AND gate 203, and is passed through the inverter 208 to the AND gate 214 and the second input terminal of the AND gate 203.
The signal is input to the second input terminal of the AND gate 201 and the second input terminal of the AND gate 202 .

The output of the AND gate 201 is input to the second input terminal of the AND route 212 and the second input terminal of the AND gate 204 through the OR gate 21326.

The output of AND root 204 is input to the first input terminal of OR gate 206, the output of AND dart 202 is input to the second input terminal of AND dart 206,
The output of 3 is input to the first input terminal of the OR gate 207,
The output of the AND dart 214 is connected to the second input terminal of the AND f-) 212 through the OR gate 213 and the AND dart 205
It is designed to be input to the second input terminal of.

From the output terminal of the AND dart 212 to the logical product R・(A−n+
*-B) is output, and the switch 22 is controlled by this.

Also, from OR gate 206, logical sum (R-A, 50 balls,
D.i) is output, and the switch 20 is controlled thereby.

Furthermore, from the OR gate 207, the logical sum (R・τ・B+R
・A-B) is output, and the switches and switches 21 are controlled accordingly.

The voltages and currents at each part of the embodiment shown in Fig. 6 are shown in Fig. 7 (,).
- As shown in FIG. 7(k). FIG. 7(a) and FIG. 7(b) show frequency-divided signals A and B, respectively, and FIG. 7(c)
shows the horizontal synchronizing pulse R, and FIG. 7(d) shows the voltage vc at the filter end 19.

In addition, Fig. 7(,) to Fig. 7 body) are Fig. 7(a) to Fig. 7
This is an enlarged view of the part in Figure (d), and Figure 7 (,)
7(g) corresponds to FIG. 7(a) to 7(C), FIG. 7(k) corresponds to FIG. 7(d), and FIG. 7(h)
~FIG. 7(j) shows the operation of the switches 20-22.

As is clear from FIG. 7, the frequency-divided signal B is an inversion of the frequency-divided signal A, and forms a rectangular wave with a period equal to or close to the pulse width tw of the horizontal synchronizing pulse R, centered on the positive edge. I'm using something embedded.

The basic principle of the embodiment shown in FIG. 6 is the same as that of the embodiment shown in FIG. A control current is output by detecting the phase difference between the fall of 9 and the horizontal synchronization/4' pulse R and the signal □.

When the branch signal B advances with respect to the horizontal synchronizing pulse R, (R-A-B + R-A-B) is output as a logical sum from the off-date 207, and this output closes the switch 21 (Fig. 7 0) ). This causes the charge on capacitor C2 to be discharged through switch 2, causing the current to flow through the switch. is pulled out and the voltage of the filter 19 is ■. decreases.

Conversely, when the branch signal B is delayed with respect to the horizontal synchronization pulse R, the OR dart 206 outputs the logical sum (R-A-
B+R-A-B) is output, and this output closes the switch 20 (FIG. 7 0)), and current is supplied to the capacitor C8 through this switch 20. flows, and the voltage at the filter end 19 increases.

Further, the switch 22 is closed by the AND output R.(AB+A-B) of the AND/DART 212, and the bias voltage V is applied to the terminal 35. The current (Vovc)/Rt is set at the filter end 19 according to the phase difference between the voltage V at the filter end 19 and the voltage V at the filter end 19.
supply to.

Therefore, the characteristics of this phase comparator are shown in FIGS. 1 and 4.
It is exactly the same as the embodiment shown in the figure.

Also, two triangular ripples A5. appearing at the filter end 19. Similar to the embodiment shown in FIG. 4, A6 (FIG. 7) also has the same area, and the error voltage at the filter end 19 corresponding to the frequency error is completely zero. Finally, the frequency error is completely eliminated.

In each of the above embodiments, the explanation has been limited to a PLL type frequency multiplier circuit, but the present invention is not limited to a frequency multiplier circuit. For example, the invention is not limited to a frequency multiplier circuit.
It is also applicable to PLL.

In this case, a time delay close to the pulse width of the reference signal can be generated by, for example, using a completely different clock pulse for time processing, or by using an analog delay line.

[Effects of the Invention] As described above, according to the phase comparator circuit of the present invention, the triangular ripple amplitude at the end of the loop filter is reduced, and at the same time, this ripple waveform also becomes bipolar, so that its peaks and valleys are reduced. By canceling each other out, the error voltage at the filter end can be significantly reduced.

Accordingly, frequency errors can be almost eliminated.

Furthermore, the frequency error can be completely reduced to zero with a simple configuration. Furthermore, since the control current is output only during the error phase, there is also the advantage that almost no power is consumed, especially in the erroneous state.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the phase comparator circuit of the present invention,
Figure 2 is a diagram showing the periodic process of the PLL using the phase comparison circuit as above, and Figure 3 is an enlarged diagram showing the waveforms of voltage and current at various parts when the PLL using the phase comparison circuit as above is phase-locked. , FIG. 4 is a circuit diagram showing a second embodiment of the phase comparison circuit of the present invention, and FIG. 5 shows the voltage and current waveforms of various parts when the PLL using the phase comparison circuit of FIG. 4 is in phase. The enlarged view, FIG. 6, shows the third phase comparison circuit of the present invention.
7 is an enlarged diagram showing the voltage and current waveforms of various parts when the PLL using the phase comparator circuit of FIG. A block diagram of a PLL type frequency multiplier circuit, Fig. 9 is a circuit diagram of a conventional phase comparison circuit, and Fig. 10 is a PLL type frequency multiplier circuit using the phase comparison circuit of Fig. 9.
Figure 11 is a diagram showing the phase locking process of LL, Figure 11 is a characteristic diagram showing the relationship between the control voltage and oscillation frequency of the voltage controlled oscillator, and Figure 12 is a diagram showing the relationship between the control voltage and oscillation frequency of the voltage controlled oscillator.
The figure is an enlarged view showing the voltage and current waveforms of various parts when the PLL using the phase comparator circuit of FIG. FIG. 3 is a diagram showing the relationship between ripple amplitude and ripple amplitude. 3... Phase comparator, 4... Low pass filter, 5...
Voltage controlled oscillator, 20-22... switch, 201-
205.212...and gate, 206,207*
213...OR gate, 208-211...inverter, C8...capacitor % R,...resistance.

Claims (1)

[Claims] The output of the voltage controlled oscillator of the phase-locked loop shifted by a time close to or equal to the pulse width of the reference signal, or the rising or falling edge of the first signal of the first and second two signals obtained by dividing the output. a first circuit that detects a phase between a rising edge or a falling edge of a pulse of the reference signal, and a falling edge or rising edge of the second signal and a falling edge of the pulse of the reference signal, which is opposite to the first signal; Or the second one that detects the phase difference with the rising edge.
and a circuit for controlling charging and discharging current at the filter end in the phase-locked loop using the outputs of the first and second circuits.