JPS5821968B2 - PLL method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL system that significantly improves transient characteristics with respect to phase changes in an input signal.

PLLs are now becoming widely used, and one of their effective uses is the ability to generate from a single input signal arbitrary polyphase signals that are synchronized to this input signal.

Taking as an example a control signal generator for a three-phase phase control forward converter using Thyrisk, the output of this converter can be made variable by changing the firing phase of the thyristor. The ignition signal is exactly 120
It is necessary to change the phase with respect to the power supply AC waveform while maintaining the phase difference of °.

Furthermore, since the frequency of the power source alternating current is relatively low at 50 Hz or 60 Hz, it is desirable to have a quick response characteristic of one cycle or less to a phase change signal in consideration of use in automatic control or the like.

Figure 1 shows a block diagram of a conventional three-phase phase control signal generator using the PLL system, including a phase shifter 1, a phase comparator 2, a low-pass filter 3, a VCO (voltage controlled oscillator) 4, a frequency divider (ternary counter) consists of 5.

To specifically explain the circuit operation of FIG. 1 using FIG. 2, which shows the operating waveforms assuming that the phase comparator 2 and the low-pass filter 3 are ideal, the standard pulse train an( n=1.2...) is in phase with the AC power supply of 60 Hz.

The output dn (n=1.2...) of the phase shifter 1 is shown in FIG.
The phase can be changed depending on x (x=1°2).

For example, if the other input Vsx to the phase shifter 1 is Vsl, the output d1 of the phase shifter 1 corresponding to the standard pulse a1 has a phase difference of θ, and the phase comparator 2 1 output d
Compare the phases of n and the output gn of the frequency divider 5 (n=1°2,...), and adjust the VC according to the phase difference between the outputs dn and gn.
Controls the input voltage elx (x-1, 2, 3) to O4.

If the PLL is in a locked state, for example, the output d1 of the phase shifter 1 and the output g of the frequency divider 5 in FIG. 2 C9e are completely in phase.

At this time, no differential voltage is obtained from the phase comparator 2, and the input voltage elx to the VCO 4 is set to ell, as shown in the figure.

The fact that the differential voltage is zero does not necessarily mean that ell is zero.

In this way, the oscillation output frequency of the VCO4 is exactly three times that of the AC power supply.The standard pulse example in Figure A shows the output waveform of the VCO4 between al and a2. It can be seen from the presence of pulses like this that the outputs of the frequency divider, that is, the counter
, 2, -1 same figure f), jn (n=1 , 2 ,...
, g) have a phase difference of exactly 120° from each other.

Also, when the input Vsx to the phase shifter 1 is changed from Vsl to VS2, the standard pulse example is a2 and the output d of the phase shifter 1.
2, the phase difference changes to θ2.

For this reason, until now, the output gn of the frequency divider 5 was no longer in phase with the output dn of the phase shifter 1, a voltage difference was generated in the phase comparator 2, and as a result, the input voltage el to the VCO 4 was increased as shown in the figure.
It changes from l to e12.

Then, the oscillation output frequency of the VCO 4 changes, and as shown in the figure e, after pulse g3, its phase changes to the output d of the phase shifter 1.
It will be matched to the phase of 3.

Similarly, when the input Vsx to the phase shifter 1 changes from VS2 to VS1, the input voltage elx to the VCO 4 changes due to the phase difference between the output g3 of the frequency divider 5 and the output d of the phase shifter 1.
changes, and eventually, after the pulse ga (e in the figure), the phase of the output of the frequency divider 5 is locked to the output dn of the phase shifter 1.

In this way, the response of the phase of the output dn to the input Vsx to the phase shifter 1 is delayed by one to two cycles, as is clear from FIG.

Moreover, in Fig. 2, phase comparator 2, low-pass filter 3
It idealizes the operation of
It still takes several tens of cycles for the output pulse phase response to be completed by a low pass filter with a long time constant to eliminate ripple on the input to the CO.

The present invention directly controls the VCO by changing the input signal to the transporter.
By changing the phase of the oscillation output of the PLL system, a PLL system with little delay as described above, that is, extremely fast response speed, is realized, and this is an extremely innovative invention.

FIG. 3 is a circuit block diagram of a three-phase phase control signal generator that embodies the PLL system of the present invention, and is completely different from the conventional one in that a phase adder/subtractor is added. There is.

That is, the phase of the oscillation output of the VCO 4 is directly controlled by Vsx.

Next, to explain the phase adder/subtractor 6 in detail, in order to better understand the phase adder/subtractor in the present invention, the UJT relaxation oscillator shown in FIG. 4 will be explained. UJT is an abbreviation for unit junction transistor. U.J.
As shown in FIG. 4, T is connected to a capacitor C1, a resistor R1, a power supply +Vcc, an N frequency divider 7, and a current source (2).

In the UJT relaxation oscillator configured in this way, with the sawtooth wave voltage Vp generated across the capacitor C, N
When the output frequency f of the frequency divider 7 is expressed, the following equation (1) is obtained.

Here, τ is the capacitance of capacitor C, N is the frequency division ratio by N frequency divider 7, ■ is the current from current source ■, and this current ■ is V
2 is controlled by the input voltage elx to CO4, but it becomes a constant value in a steady state, so if both sides of equation (1) are integrated over time t, the following equation (2) is obtained.

ft+θ=-I・t(2) VpN In this trend 2), the left side represents the i phase of the oscillation output of the VCO 4, and the right side represents the amount of charge flowing into the capacitor C.

Therefore, in order to change the phase of the oscillation output of this oscillator by ±Δθ, it is preferable to adjust the amount of charge flowing into the capacitor C by ±ΔQ.

That is, the following equation (3) is it.

ft+θ±△θ−-(I −t±△Q(3)VpN When rearranged using equations (1) and (2), ■ △Q=−△θ (4) get.

This equation (4) can be applied to relaxation oscillators in general.

FIG. 5 shows the VCO4 of the present invention by applying the relaxation oscillator of FIG. 4.
As shown in FIG. 5, the transistor T2 constitutes a constant current circuit controlled by elx shown in FIG. The amount of electric charge flowing into the capacitor C1 is controlled by.

'That is, since the charge addition coefficient ΔQ in the circuit of FIG. The capacity of C2 is calculated from the above formula (4) as C
2=-k (7).

The way to derive this equation (7) is to transform equation (6) to △Vsx
= △θ , e-1 is obtained, and when this is inserted into equation (5), △Q =
”2 i.

is obtained, and △θ−f obtained by transforming equation (4)
If engineering △Q is substituted, △Q ”= C2h・〒△Q becomes △
It is preferable to eliminate Q and express the formula for C2.

The timing chart of FIG. 6 serves to explain the operation of the circuit of FIG. 5 according to the method of the present invention.

Regarding FIG. 6, since the phase adder/subtractor 6 is only added to the circuit of FIG. 1, the circuit shown in FIG. 6a.

Explanation regarding b and c will be omitted.

Suppose that the input Vsx, which is the input to the phase shifter 1 and also the input to the phase adder/subtractor 6, has now changed from Vsl to Vs2 (change amount △Vsx = Vs2 - Vs1), △V
Since sx=♀9 (formula (5)), the phase of the phase adder/subtractor 6 advances by Δθ, and the phase of the oscillation output of the VCO 4 also follows this.

-△θ also when the input Vsx changes from Vs2 to Vsl
Proceed immediately by 2.

Furthermore, the phase difference between the pulses dn and gn applied to the phase comparator 2 is not affected by the input Vsx, and even if the time constant of the low-pass filter 3 is increased, the transient characteristics are not affected at all.

In this way, according to the PLL method of the present invention, the response characteristics of the output signal to the phase-shifted signal can be significantly improved without reducing the time constant of the low-pass filter, and especially when the frequency of the standard signal is low, it is possible to improve the response characteristics of the output signal to automatic control. It is effective in the application of

[Brief explanation of drawings]

Fig. 1 is a circuit block diagram of a three-phase phase control signal generator using the conventional PLL method, Fig. 2 is a timing chart for explaining the circuit operation, and Fig. 3 is a three-phase phase control signal generator using the PLL method of the present invention. Generator circuit block diagram, 4th
The figure is a circuit diagram of a relaxation oscillator for explaining the principle of the VCO and phase adder/subtractor in the PLL method of the present invention, and FIG. 5 is a specific circuit diagram of the VCO and phase adder/subtractor in the PLL method of the present invention. FIG. 6 is a timing chart for explaining the operation of the circuit shown in FIG. 1: Phase shifter, 2: Phase comparator, 3: Low pass filter,
4: vco, s: frequency divider, 6: phase adder/subtractor.

Claims (1)

[Claims] 1. It has at least a phase comparator, a low-pass filter, and a VCO, and the output of the phase shifter is used as an input to the phase comparator, and a phase control signal is introduced into the phase shifter to achieve this shift. In a PLL system in which the phase of the output of the phase shifter is changed, the phase control signal is used as a control input signal and the phase of the oscillation output of the VCO is adjusted by an amount corresponding to the amount of phase change of the output of the phase shifter. PL characterized by having a container
L method. 2 The PLL type capacitor relaxation oscillator according to claim 1 above is connected to the VCO (!:), and by adjusting a predetermined amount of charge flowing into the capacitor, the VCO
A PLL system characterized by being provided with a phase adder/subtractor that adjusts the oscillation phase of the oscillation phase.