JPH02127818A - Phase locked loop oscillator - Google Patents

Abstract

PURPOSE:To detect an accurate steady-state phase abnormal error without the effect of the deviation in elements, the temperature and secular change by generating a threshold level for detecting a steady-state phase error and abnormality with use of digital components only. CONSTITUTION:A phase locked loop oscillation section 20 consists of a phase comparator 1, a voltage controlled oscillator 2, and a frequency divider 4, which form an oscillation loop. In order that the phase locked loop oscillation section 20 detects a steady-state phase abnormal error, a 1st phase clock signal is led for the phase by (t) with respect to a 2nd phase clock signal and the 3rd phase clock signal is retarded by only the phase (t). The phase difference (t) is a threshold level for the detection of a steady-state phase abnormal error and depends on the phase difference of a 3rd phase clock signal. Moreover, a 3-phase clock generating circuit is formed by a digital circuit only depending on the period of the clock signal only. Thus, the detection of the steady-state phase error is attained without the effect of the deviation in the capacitance of components, the temperature characteristic and secular change.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronized oscillator, and particularly to a phase synchronized oscillator that outputs a steady phase error detection signal with respect to a reference input signal.

[Conventional technology]

A conventional steady phase error detection circuit provided with one phase synchronized oscillator will be explained with reference to FIG.

In the figure, 20 is a phase synchronized oscillator that always generates an output signal having a predetermined phase relationship with respect to the input reference input signal I, 21.22 is a time limit circuit constituted by a monostable multivibrator, etc., 23. 24 are two retiming circuits composed of D-type flip-flops, 25
is an OR circuit that ORs the outputs of these two retiming circuits 23 and 24. 100 is an input terminal to which a reference input signal is applied, 200 is an output terminal from which an output signal is obtained, and 300 is a phase difference alarm output terminal.

Usually, the phase synchronized oscillator 20' includes a phase comparator 1, a voltage controlled oscillator 2, and a frequency divider 4. Further, fl indicates a reference input signal, flo indicates an output signal of the phase synchronized oscillation unit 20', s hle tzs indicates a time limit circuit 21, 22, respectively.
shows each output signal.

Next, the operation of the conventional circuit shown in FIG. 4 will be explained with reference to FIGS. 5 and 6.

5 and 6 are waveform diagrams showing the operation of each part of the conventional circuit.
Steady phase error detection circuit 21 when is operating normally
FIG. 6 is a waveform diagram showing the operation of the steady phase error detection circuit 21 when the phase synchronized oscillation section 20' shown in FIG. 4 has a steady phase error abnormality. In addition, (a) in FIGS. 5 and 6 respectively shows the waveform of the reference input signal f1;
．． 22 shows each waveform of each output signal f21.122.

First, in FIG. 5, %T1 and T2 are respectively the time limit circuits 21s? and the timing (pulse width) determined by the timer circuit 22, and normally both values are equal. When the phase comparison period is T, the detection threshold t for a steady phase error abnormality is determined by the following equations (1) and (2)% (21). When the phase error exceeds the threshold above I as shown in FIG. The output signal ho of the phase-locked oscillator 20' is φ with respect to the signal f.
However, conversely, when the PJ phase progresses beyond the threshold value, the output of the retiming circuit 23 becomes @11'', and a steady phase LQ difference is detected.

[Problem to be solved by the invention]

In the conventional steady phase error detection circuit of the phase-locked oscillator described above, the detection threshold is T shown in equations (1) and (2).

The phase comparison period T is determined by the external conditions required of the phase synchronized oscillator. Therefore, the detection threshold is determined by the pulse widths T1 and T3 generated by the timer circuits 21,22. Here, if the requirements for threshold deviation are not strict, the time limit circuits 21 and 22 can be realized by a relatively simple monostable multi-pipe rake or the like. However, since the output pulse width is mainly determined by analog elements such as capacitors and resistors, it is necessary to set a highly accurate threshold value that cannot ignore the effects of capacitance deviations, temperature characteristics, changes over time, etc. of these elements. The disadvantage was that it was difficult.

[Means to solve the problem]

The phase synchronized oscillator of the present invention includes a voltage controlled oscillator, a frequency divider that divides the output signal of the voltage controlled oscillator and outputs a first signal, and a reference signal that is input from the outside and the first signal. a phase comparator that feeds back a phase difference signal obtained by comparing the phases of the two signals to the voltage controlled oscillator; a three-phase lock generation circuit that outputs second and third signals having the same characteristics; a first retiming circuit that receives the second signal and the reference signal and outputs a first determination signal; a second retiming circuit that receives a third signal and the reference signal and outputs a second determination signal;
and a logic circuit that inputs the first and second determination signals and outputs a logical product.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The embodiment of FIG. 1 has an input terminal 100 for the reference input signal f1,
Phase comparator 11 Voltage controlled oscillator 2.3 Phase lock generation circuit (for example, shift register) 3, Frequency divider 4 that outputs a signal for phase comparison with reference input signal f1, Retiming circuit (for example, D type flip-flop) 5 .6. A logic circuit (for example, a NAND circuit) 7 that takes the AND of the outputs of the two retiming circuits 5.6, an output terminal 200. It consists of a phase error alarm output terminal 300.

Here, the phase synchronized oscillation section 20 forms an oscillation loop with the phase comparator 1, the voltage controlled oscillator 2, and the frequency divider 4. First, the second phase clock signal f12 separated from the oscillation signal of the voltage controlled oscillator 2 is input to the three-phase clock generation circuit 3I.
f1 with! 1st phase clock signal ff” whose phase is more advanced
+ 3rd phase clock f13 whose phase is delayed from fsz
occurs.

Next, in order to detect that the phase synchronized oscillator 20 has a steady phase error abnormality, the first phase clock signal fil advances the phase of the second phase clock signal f121 by t, and the third phase clock signal fil leads the second phase clock signal f121 by t. The signal is rubbed once so that the phase is delayed by t. This phase difference t is a threshold for abnormality detection of a steady phase error, and is set based on design conditions l. Further, the phase difference t is determined by the amount of phase shift of the three-phase clock generation circuit 30, and as mentioned above, when the three-phase clock generation circuit 3 is composed of one shift register, It is determined by the period 1 of the clock signal.

Figures 2 and 3 are waveform diagrams showing the operation of each part of the embodiment in Figure 1, and each of Figures 2 and 3 is a reference input. Waveform of signal f1, (b
) is the second phase clock signal f1! (→ is the waveform of the first phase clock signal fll, (Φ is the waveform of the third phase clock signal h
s waveform is shown. Further, FIG. 2 shows a case where the device is operating normally without a steady phase error, and FIG. 3 shows a case where an abnormality occurs with a steady phase error. In the normal case shown in Fig. 2, that is, the phase difference between the reference input signal f, J and the second phase clock signal f12, which is an oscillation signal (0 in the figure).
is smaller than the phase difference t, the two retiming circuits 5
．． Since the outputs of 6 are both "H", the steady phase error abnormality detection signal is not output.

FIG. 3 shows the reference input signal f! For the phase synchronized oscillator 20
This shows a case where the output signal fH has a steady phase error of φ. Here, if φ is larger than the phase difference t between each phase of the three-phase clock described above, that is, 1φl>Itl
If the following relationship holds true, the level of the output of the retiming circuit 5 or 6 is inverted. Therefore, it is detected that the threshold phase difference t for steady phase error detection has been exceeded.

As explained above, the threshold for steady phase error detection is 3
It is determined by the phase difference between the phase clock signals. Zara ζko,
If the 3-phase clock generation circuit is configured as in this embodiment, it is possible to determine the period of the clock signal from only one digital circuit.

〔Effect of the invention〕

As explained above, according to the present invention, the threshold value for detecting a steady phase error abnormality is generated only by a digital element instead of the conventional time circuit of an analog element. And there is no effect of aging [
This has the effect of detecting steady-state phase error abnormalities. Furthermore, since the steady phase difference can be detected only by a digital circuit, not only is no adjustment work required, but it can also be integrated into an IC, which has extremely great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
(φ, Figures 3 (a) to (d) are waveform diagrams of this example,
The figure is a block diagram of a conventional phase-locked oscillator, Figure 5 (a)
〜(CI), FIG. 6(ω〜(d) is a waveform diagram of a conventional example. 100... Input terminal, 1... Phase comparator, 2......・Voltage controlled oscillator, 3...3
Phase clock generation circuit, 4... Frequency divider, 5, 6...
...Retiming circuit, 7...Logic circuit,
200... Output terminal, 300... Alarm output terminal, 20.20'... Phase synchronized oscillator,
21.22...Timed circuit, 23.24...
...Retiming circuit, 25...Logic circuit. Agent Patent Attorney Shinman Uchihara Figure 2 (Figure 2, Figure 3, Shoulder Figure 4) Figure P55, Figure B

Claims (1)

[Claims] a voltage controlled oscillator; a frequency divider that divides the output signal of the voltage controlled oscillator to output a first signal; a phase comparator that feeds back the phase signal obtained by the voltage control oscillator to the voltage controlled oscillator;
a three-phase clock generation circuit that outputs a signal; a first retiming circuit that receives the second signal and the reference signal and outputs a first determination signal; and a three-phase clock generation circuit that outputs the third signal and the reference signal. A second retiming circuit inputs a signal and outputs a second determination signal, and a logic circuit inputs the first and second determination signals and outputs an AND. Phase-locked oscillator.