JPS5839122A - Detecting circuit for step-out of synchronism - Google Patents

Abstract

PURPOSE:To detect the step-out of synchronism, by comparing the phase of an input clock signal with that of an output clock signal in the digital phase synchronizing system and discriminating an average DC voltage value of the output. CONSTITUTION:An input clock signal and an output clock signal of a digital phase synchronizing circuit 12 are applied to an exclusive OR circuit 7, and the output is amplified in an amplifier 8 to obtain an average DC voltage through a rectifying circuit 9 and a low-pass filter 10. When the input clock signal and the output clock signal are synchronized with each other, the average DC voltage is 0. When they do not synchronized with each other, the phase difference is random values, and the output of the exclusive OR circuit 7 is 1 and 0 alternately equivalently when they are averaged, and the average DC voltage is 1/2VH when the maximum output voltage of the low-pass filter 10 is defined as VH, and the average DC voltage is discriminated by a discriminating circuit 11 where the discriminating voltage is set to a value slightly lower than 1/2VH, and the output voltage becomes the maximum value VH, thus detecting step-out of synchronism.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital phase lock system (hereinafter referred to as DPLL), and relates to a synchronization loss detection circuit that detects synchronization loss by comparing the phases of an input clock signal and an output clock signal.

In the DPLL method, as a recent technological trend, there has been a demand for detecting abnormalities in each block in order to improve reliability.

OBJECT OF THE INVENTION It is an object of the present invention to provide a synchronization line deviation detection circuit that can detect out-of-synchronization in a DPLL system by adding a simple circuit in order to improve reliability.

In order to achieve the above object, the present invention uses a DPI, L system to compare the phases of an input signal and an output signal using a phase comparator, and calculates the average DC voltage value of the output of the phase comparator. If you calculate it and compare it with the reference voltage using the identification circuit, then
It is characterized by detecting synchronization line deviation.

Embodiments of the present invention will be described below with reference to the drawings. DP
The LL method detects the phase difference between the input clock signal and the output clock signal, and sets the frequency of a fixed oscillator, such as a crystal oscillator, to a little higher than N times the frequency of the input clock signal. A system that synchronizes the phase by removing or not removing the pulse of the crystal oscillator, or a fixed oscillator that is slightly higher or lower than N times the frequency of the input clock signal,
There is a method of synchronizing the phase by switching this oscillator.

FIG. 1 is a block diagram of an out-of-synchronization detection circuit of a pulse elimination DPLL method according to an embodiment of the present invention, and FIG. 2 is a time chart of waveforms of various parts in the case of FIG. 1.
(g) indicates the case of out of synchronization, and (4) to (■) indicate the case of synchronization.1. ．． (A) (in) is the input clock signal waveform, (B) (B→ is the output clock signal waveform, (C) (C
') is an exclusive OR circuit (hereinafter referred to as EX-OR circuit)
Output waveform % (D) (D→ is referred to as low-frequency F-wavelength or LPF) output voltage, (E) (E') indicates output voltage of the identification circuit.

In the figure, 1 is a flip-flop circuit (hereinafter referred to as FF);
2 is a quantization circuit, 3 is a loop filter, 4 is a pulse removal circuit, 5 is a crystal oscillator, 6 is a frequency divider, 7 is an EX-OR
circuit, 8 is an amplifier, 9 is a rectifier circuit, 10 is an LPF, 11
1 is an identification circuit, and 12 is a DPLL circuit.

The DPLL circuit 12 inputs an input clock signal and an output clock signal to the set and reset terminals of the FFI, and is triggered by a rising pulse.Noting that the output value of Q becomes a sawtooth wave due to the phase difference, the output clock is If the phase of the signal is delayed, it will be close to the O voltage, and if it is ahead, it will be close to the maximum value of the sawtooth wave. Therefore, the value of H is quantized by the quantization circuit 2, passed through the loop filter 3, and output as an ay signal. If it is progressing, the pulse removal circuit 4 removes, for example, one output pulse from the crystal oscillator 5 to lower the frequency, and if it is delayed, it remains as it is.
In addition to the divider 6 and the 1/N signal, in addition to the reset terminal of the FFI, the phase difference is made equal to obtain a phase-synchronized output signal. Therefore, as a feature of the DPLL, the phase change range of the output four-way signal with respect to the input four-way signal over the entire synchronization range is +3 using the division ratio N of the frequency divider.
It is expressed as 6072N to -360χ2N. That is, the steady phase error is within 360./2N. For example, N-64
Even when
value.

In this phase-synchronized situation, Figure 2 (A') to (
As shown in E'), the input clock signal shown in (A') and the output clock signal shown in (D') are synchronized, and as mentioned earlier, the steady phase error is very large. EX because it is small
The output voltage of -OR 7 becomes O as shown in (C'), which is amplified by amplifier 8' and the average DC voltage obtained by rectifier circuit 9 and LPFIO becomes 0 as shown in (D'). Even if the current input signal contains jitter, this value is small, so if the maximum output voltage of LPFIO is allowed, it will be 1/2 VII! 31 is a much smaller value. Therefore, if the identification voltage of the identification circuit 11 is made slightly smaller than VM/2, sufficient identification will be made and the output voltage will be set to zero. In the state that is out of synchronization, the phase difference between the input clock signal shown in (2) to ■ and the output four clock signal shown in ■ is a random value, and the output of 1&DEX-Rot is in phase. If the phase is shifted by 180 degrees, it becomes 1, and when viewed on average, it is equivalent to isometry (as shown in Q, half of 0 and 1 appear alternately). If this voltage is passed through the amplifier 8, rectifier circuit 9, and LPFIO to determine the average DC voltage, it will be 1/2VH.Therefore, the identification voltage of the identification circuit 11 should be slightly smaller than 1/2VH, so that it can be identified. The output voltage of the identification circuit 11 is the maximum value VH
Tona> It is possible to detect out-of-synchronization. Also, if the input clock signal and the output clock signal are out of phase by 180 degrees, they may become synchronized, but in this case, the LPFIG output will not be synchronized with VW, but the When the output is out of synchronization, the output of the separate circuit 11 is out of synchronization. If the value is 0, the out-of-synchronization can be detected.

Fig. 3 shows another embodiment of the present invention, a block diagram of a DPLL type out-of-synchronization detection circuit that switches the frequency of two fixed oscillators, and Fig. 4 is a time chart of waveforms of various parts in the case of Fig. 3. Adashi, prisoner~■ are the same.

% (A') to (E') indicate the case of out-of-synchronization, (A) (A') is the input clock signal waveform, (B) (B') is the output clock signal waveform, (C)
(C') is the output waveform of the D-shaped flip-flop tab (hereinafter referred to as D・FF), (D)ω) is the output voltage of the LPF, and (E) (E') is the output voltage of the identification circuit. In the figure, parts with the same functions as those in FIG. 1 are indicated by the same symbols. 12
is an EX-OR circuit, 13 is a gate circuit, 14.1B is a fixed silk generator, 16 is a D-FF%d is a divider, 12' is a DP
The LL circuit is shown.

In this DPLL system, the frequency of the fixed oscillator 14,15 is slightly higher or lower than N times the input clock signal. The input clock signal shown in Figure 44 and the output clock g1 shown in Figure 4 are input to t-EX-OR@path 12, and when the phase difference is 360 degrees with OJf, the output becomes 0, and when it is 180 degrees, it becomes the maximum value. Paying attention to the point where it becomes a triangular wave,
Synchronization t and 90 degrees at the points of 90 degrees and 270 degrees.If the output clock signal is delayed, the output of EX-OR12 will be high, and the output of the oscillator 14 with a frequency of only 44 will be gated. Also, when the number of the cuff lock 11 is advanced, the output of EX-OR 12 becomes low and one round'a! i, a slightly lower number of oscillations 41
The output of 5 is outputted through the gate circuit 11, and in both cases, it is outputted as a frequency of 1/N at the branch station Jada.
-0 or 2707 [0 or 2707] which inputs to OR1g and obtains an output signal that is phase-synchronized at a point where the phase is 90 degrees with the input clock v/01 [If O, the output clock signal is leading, if it is lagging, (If the output of DEX-OR12 is in the opposite direction to the above, the output of fixed 4A-15 is set to 1.)
The delayed output signal is fixed to obtain a phase-synchronized output signal at a point of 270 degrees. In this DPLL as well, the steady phase error is a very small value as in the previous example, and the detection described below can be applied.

To explain the case where synchronization is achieved at 90 degrees,
Looking at the input clock signal waveform shown in (4) at the rising point of the output clock signal waveform shown in (6), the output of Q is "1".
It is set as “O”. In this case, it is always 11°, so Q
The output of the discriminator circuit 11 is always ``1'' and is amplified by the amplifier 8 and passed through the rectifier circuit 9 and LPFIO, so the output voltage of the discriminator circuit 11 is vH. It is assumed that the phase relationship between the input signal waveform (A') and the output signal waveform (B') is random.
, at the rising point of the output p clock signal, the input clock signal waveform is @12 1) "O'. Therefore, in the relationship shown in 0), the output of D-FFI B is 10'
, In the relationship shown in (b), it is '1'', and in a certain period it becomes @Om and °1 electric half half. Therefore, the average DC voltage through the amplifier 8. rectifier circuit 9. I, PDIO is Va.
/2 force becomes O. Out-of-synchronization can be detected in any way. Also, if the input clock signal and output clock signal are synchronized with a phase difference of 270#e, D-FF'
If the output of 16 is set to 0 in a synchronized state, it is possible to detect out of synchronization. Furthermore, even if there is jitter in the input clock signal, the jitter value is relatively small and can be detected using this method.

As explained above, according to the present invention, it is possible to detect out-of-synchronization of the DPLL circuit by adding an SM circuit, which has the effect of improving reliability.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an out-of-synchronization detection circuit of a pulse removal DPLL method according to an embodiment of the present invention, and Fig. 2 is a time chart of waveforms of various parts in the case of Fig. 1. Block diagram of a DPLL type out-of-synchronization detection circuit that switches the frequencies of two fixed oscillators in the embodiment of 4.
The figure is a time chart of waveforms of various parts in the case of FIG. 3. In the figure, 1 is an FF, 2 is a quantization circuit, 3 is a loop filter, 4 is a pulse removal circuit, 5 is a crystal oscillator, 6.61 is a divider, 7.12 is an EX-OR circuit, 8 is an amplifier, 9 is a rectifier circuit, 10 is an LPF, 11 is an identification circuit, 12.12
is a DPLL circuit, 13 is a gate circuit, 14.15
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Claims (1)

[Claims] 1. An out-of-synchronization detection circuit in a gage digital phase synchronization method, characterized in that a phase comparator compares the phases of an input clock signal and an output clock signal, and an identification circuit identifies the average DC voltage value of the output of the phase comparator.