JPH022217A - Phase lock detection circuit - Google Patents

Phase lock detection circuit

Info

Publication number
JPH022217A
JPH022217A JP63145679A JP14567988A JPH022217A JP H022217 A JPH022217 A JP H022217A JP 63145679 A JP63145679 A JP 63145679A JP 14567988 A JP14567988 A JP 14567988A JP H022217 A JPH022217 A JP H022217A
Authority
JP
Japan
Prior art keywords
output
level
controlled oscillator
voltage controlled
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63145679A
Other languages
Japanese (ja)
Inventor
Kunio Yamakawa
山川 邦雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63145679A priority Critical patent/JPH022217A/en
Priority to US07/465,162 priority patent/US5099213A/en
Priority to PCT/JP1989/000593 priority patent/WO1989012930A1/en
Publication of JPH022217A publication Critical patent/JPH022217A/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To ensure the detection of a phase lock state by deciding the locking state depending on a level of a control voltage of a voltage controlled oscillator. CONSTITUTION:When a phase locked loop circuit is in the locking state, an output of a 1st level decider 7 goes to a high level and the output of a 2nd level decider goes also to a high level. Then a switch 9 is thrown to the position of a terminal (a) and an output high level of the said 1st level decider 7 becomes a phase locking detection signal. When the voltage controlled oscillator 5 is in the sweep state, the output of the 2nd level decider 8 repeats high/low levels. A synchronization detection signal goes to a low level. When the output frequency of the voltage controlled oscillator 5 is deflected out toward higher (lower) direction than the center frequency, the control voltage of the voltage controlled oscillator 5 is a positive (negative) power voltage. Thus, the output of the 1st level discriminator 7 goes to a low(high) level and the output of the 2nd level discriminator 8 goes to a high (low) level and the phase synchronizing detection signal goes to a low level.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は局部発振器などに用いる位相同期発振器の位相
同期検出回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase synchronization detection circuit for a phase synchronization oscillator used in a local oscillator or the like.

(従来の技術) 従来の位相同期検出回路は第4図に示すような構成であ
った。
(Prior Art) A conventional phase synchronization detection circuit has a configuration as shown in FIG.

すなわち入力端子1に加えられる入力信号と電圧制御発
振器5の出力を位相比較器2により位相比較し、前記位
相比較器2の出力を分岐して一方はループフィルタ4に
入力し、他方は掃引発振器3に入力し、前記ループフィ
ルタ4の出力と前記掃引発振器3の出力を結合して、前
記電圧制御発振器5に入力してループを構成し、前記電
圧制御発振器5の出力を三分岐して、帯域フィルタ17
と位相比較器2と発振出力端子11に入力し、前記帯域
フィルタ17の出力を振幅検波器18に入力し、前記振
幅検波器18の出力をレベル判定器19に入力し、位相
同期検出信号を前記レベル判定器19の出力端子10か
ら得ていた。
That is, the input signal applied to the input terminal 1 and the output of the voltage controlled oscillator 5 are phase-compared by the phase comparator 2, and the output of the phase comparator 2 is branched and one is input to the loop filter 4, and the other is input to the sweep oscillator. 3, the output of the loop filter 4 and the output of the sweep oscillator 3 are combined, input to the voltage controlled oscillator 5 to form a loop, and the output of the voltage controlled oscillator 5 is branched into three, bandpass filter 17
is input to the phase comparator 2 and the oscillation output terminal 11, the output of the bandpass filter 17 is input to the amplitude detector 18, the output of the amplitude detector 18 is input to the level determiner 19, and the phase synchronization detection signal is input. It was obtained from the output terminal 10 of the level determiner 19.

(発明が解決しようとする課題) しかし、このような構成のものでは、同期がはずれたと
きの前記電圧制御発振器5の周波数の中心周波数からの
偏位が小さい場合、帯域フィルタ17の帯域を狭くする
ことには限界があるため、同期が外れたときでも前記電
圧制御発振器5の周波数が前記帯域フィルタ17の帯域
内にあり、同期状態との判別が困雅になるという問題が
あった。
(Problem to be Solved by the Invention) However, with such a configuration, if the deviation of the frequency of the voltage controlled oscillator 5 from the center frequency when synchronization is lost is small, the band of the bandpass filter 17 is narrowed. Since there is a limit to what can be done, even when synchronization is lost, the frequency of the voltage controlled oscillator 5 remains within the band of the bandpass filter 17, making it difficult to distinguish it from a synchronized state.

本発明はこのような問題を解決するもので1位相同期状
態を確実に検出することを目的とする。
The present invention solves such problems and aims to reliably detect a one-phase synchronization state.

(3題を解決するための手段) 上記課題を解決する本発明の技術的な手段は、入力信号
と電圧制御発振器の出力とを位相比較し、その位相比較
した出力を分岐し、一方はループフィルタに入力し、他
方は掃引発振器に入力し、前記ループフィルタの出力と
前記掃引発振器出力を結合したのち三分岐し、前記電圧
制御発振器と振幅検波器と第二のレベル判定器に入力し
、前記振幅検波器の出力を第一のレベル判定器に入力し
、前記第二のレベル判定器の出力によりスイッチを制御
し、前記スイッチにより前記第一のレベル判定器の出力
とロウレベルを選択して、前記スイッチの共通端子から
位相同期検出信号を得るものである。
(Means for Solving the Three Problems) The technical means of the present invention for solving the above problems is to compare the phases of the input signal and the output of the voltage controlled oscillator, branch the phase-compared outputs, and divide one into a loop. one input to a filter, the other input to a sweep oscillator, the output of the loop filter and the output of the sweep oscillator are combined, and then branched into three, and input to the voltage controlled oscillator, amplitude detector, and second level determiner, The output of the amplitude detector is input to a first level determiner, a switch is controlled by the output of the second level determiner, and the output of the first level determiner and a low level are selected by the switch. , a phase synchronization detection signal is obtained from a common terminal of the switch.

(作 用) この技術的手段による作用は次のようになる。(for production) The effect of this technical means is as follows.

すなわち、同期状態では電圧制御発振器の制御電圧が正
のffl源電圧電圧低いある直流値であることを第一の
レベル判定器および第二のレベル判定器で判定し、非同
期状態では正の電源電圧であれば第一のレベル判定器で
判定し、負の電源電圧であれば第二のレベル判定器で判
定し、掃引状態であれば振幅検波器で検波したのち第一
のレベル判定器で判定する。このように電圧制御発振器
の制御電圧のレベルにより同期状態を判定するため位相
同期状態の検出が確実にできる。
That is, in a synchronous state, the first level determiner and the second level determiner determine that the control voltage of the voltage controlled oscillator is a certain DC value lower than the positive ffl source voltage; If it is a negative power supply voltage, it is determined by the first level determiner, if it is a negative power supply voltage, it is determined by the second level determiner, and if it is in a sweep state, it is detected by the amplitude detector and then determined by the first level determiner. do. In this way, since the synchronization state is determined based on the level of the control voltage of the voltage controlled oscillator, the phase synchronization state can be reliably detected.

(実施例) 第1図に本発明の一実施例を示す。2は位相比較器で、
入力端子1.に加えられる入力信号と電圧制御発振器5
の出力とを位相比較する。4はループフィルタで、前記
位相比較器2の出力より雑音や高周波数成分を除いた信
号を得る。3は掃引発振器で掃引信号を電圧制御発振器
5に与える。8は第二のレベル判定器で電圧制御発振器
5の制御電圧が負であればロウ、Ovまたは正ならばハ
イを出力する。6は振幅検波器で正電圧の振幅検波をす
る。振幅検波器6の具体例を第2図に示す。
(Example) FIG. 1 shows an example of the present invention. 2 is a phase comparator,
Input terminal 1. The input signal applied to the voltage controlled oscillator 5
Compare the phase with the output of 4 is a loop filter which obtains a signal from the output of the phase comparator 2 from which noise and high frequency components are removed. A sweep oscillator 3 provides a sweep signal to the voltage controlled oscillator 5. 8 is a second level determiner which outputs low if the control voltage of voltage controlled oscillator 5 is negative, and outputs high if Ov or positive. 6 is an amplitude detector which detects the amplitude of a positive voltage. A specific example of the amplitude detector 6 is shown in FIG.

12は入力端子で、13は検波用のダイオード、14は
抵抗器、15はコンデンサ、16は出力端子である。
12 is an input terminal, 13 is a detection diode, 14 is a resistor, 15 is a capacitor, and 16 is an output terminal.

7は第一のレベル判定器であり、前記振幅検波器6の出
力が正の電源電圧であればロウ、正の電源電圧以下なら
ばハイを出力する。9はスイッチであり、前記第二のレ
ベル判定器8の出力がロウならばロウレベル(端子b)
を、前記第二のレベル判定器8の出力がハイならば前記
第一のレベル判定器の出力(端子a)を選択する。
Reference numeral 7 designates a first level determiner, which outputs a low signal if the output of the amplitude detector 6 is a positive power supply voltage, and a high signal if the output is below the positive power supply voltage. 9 is a switch, and if the output of the second level determiner 8 is low, it is low level (terminal b)
If the output of the second level determiner 8 is high, the output of the first level determiner (terminal a) is selected.

つぎに動作を説明する。まず位相同期回路が同期状態に
あるとき、同期状態を検出する。すなわち同期状態であ
るので電圧制御発振器5の制御電圧Ovと正の電源電圧
の間の直流値をとり、振幅検波器6の出力は同レベルの
直流電圧となる。したがって第一のレベル判定器7の出
力はハイとなる。また第二のレベル判定器の出力はハイ
になる。
Next, the operation will be explained. First, when the phase locked circuit is in a synchronous state, the synchronous state is detected. In other words, since it is in a synchronous state, it takes a DC value between the control voltage Ov of the voltage controlled oscillator 5 and the positive power supply voltage, and the output of the amplitude detector 6 becomes a DC voltage of the same level. Therefore, the output of the first level determiner 7 becomes high. Also, the output of the second level determiner becomes high.

したがってスイッチ9は端子aを選択し、前記第一のレ
ベル判定器7の出力ハイが位相同期検出信号となる。
Therefore, the switch 9 selects the terminal a, and the high output of the first level determiner 7 becomes the phase synchronization detection signal.

つぎに位相同期回路が非同期状態にあるときはつぎの三
状態がある。第一に前記電圧制御発振器5が掃引状態に
あるとき、第二に前記電圧制御発振器5の出力周波数が
中心周波数より高い方に振り切れたとき、第三に前記電
圧制御発振器5の出力周波数が中心周波数より低い方に
振り切れたときである。
Next, when the phase-locked circuit is in an asynchronous state, there are the following three states. First, when the voltage controlled oscillator 5 is in a sweep state, second, when the output frequency of the voltage controlled oscillator 5 swings higher than the center frequency, and third, when the output frequency of the voltage controlled oscillator 5 is at the center This is when the frequency swings completely below the frequency.

まず第一に前記電圧制御発振器5が掃引状態にあるとき
は前記電圧制御発振器5の制御電圧は第3図(a)に示
すように鋸歯状の波形となる。したがって前記振幅検波
器6の出力は第3図(b)に示すように正の電源電圧と
なる。したがって前記第一のレベル判定器7の出力はロ
ウになる。また第二のレベル判定器8の出力はハイ、ロ
ウを繰り返し、スイッチ9は端子a、端子すの切り換え
を繰り返すが、端子a、端子すともにロウであるから同
期検出信号はロウとなる。なおスイッチ9は切り換えの
瞬間にも必ず端子aまたは端子すに接続されている。
First of all, when the voltage controlled oscillator 5 is in the sweep state, the control voltage of the voltage controlled oscillator 5 has a sawtooth waveform as shown in FIG. 3(a). Therefore, the output of the amplitude detector 6 becomes a positive power supply voltage as shown in FIG. 3(b). Therefore, the output of the first level determiner 7 becomes low. Further, the output of the second level determiner 8 repeats high and low, and the switch 9 repeats switching between terminal a and terminal S, but since both terminal a and terminal A are low, the synchronization detection signal becomes low. Note that the switch 9 is always connected to the terminal a or terminal A at the moment of switching.

第二に前記電圧制御発振器5の出力周波数が中心周波数
より高い方に振り切れたときは前記電圧制御発振器5の
制御電圧は正の電源電圧になる。
Second, when the output frequency of the voltage controlled oscillator 5 swings higher than the center frequency, the control voltage of the voltage controlled oscillator 5 becomes a positive power supply voltage.

したがって振幅検波器6の出力は正の電源電圧となる。Therefore, the output of the amplitude detector 6 becomes a positive power supply voltage.

したがって第一のレベル判定器7の出力はロウとなる。Therefore, the output of the first level determiner 7 becomes low.

また前記第二のレベル判定器8の出力はハイとなる。し
たがってスイッチ9は端子aを選択し位相同期検出信号
はロウとなる。
Further, the output of the second level determiner 8 becomes high. Therefore, switch 9 selects terminal a, and the phase synchronization detection signal becomes low.

第三に前記電圧制御発振器5の出力周波数が中心周波数
より低い方に振り切れたときは前記電圧制御発振器5の
制御電圧は負の電源電圧になる。
Thirdly, when the output frequency of the voltage controlled oscillator 5 swings lower than the center frequency, the control voltage of the voltage controlled oscillator 5 becomes a negative power supply voltage.

したがって振幅検波器6の出力はOvとなる。したがっ
て第一のレベル判定器7の出力はハイとなる。また前記
第二のレベル判定器8の出力はロウとなる。したがって
スイッチ9は端子すを選択し位相同期検出信号はロウと
なる。以上のように同期状態のときはハイ、非同期状態
のときはロウの位相同期検出信号が得られる。
Therefore, the output of the amplitude detector 6 becomes Ov. Therefore, the output of the first level determiner 7 becomes high. Further, the output of the second level determiner 8 becomes low. Therefore, the switch 9 selects the terminal 1, and the phase synchronization detection signal becomes low. As described above, a phase synchronization detection signal that is high when in a synchronous state and low when in an asynchronous state is obtained.

(発明の効果) 以上のように本発明によれば、位相同期検出信号が確実
に得られる優れた効果がある。
(Effects of the Invention) As described above, according to the present invention, there is an excellent effect that a phase synchronization detection signal can be reliably obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における位相同期検出回路を
示すブロック図、第2図は本発明の一実施例における位
相同期検出回路に用いる振幅検波回路を示す回路図、第
3図は振幅検波回路の入出力信号の波形を示す図、第4
図は従来の位相同期検出回路のブロック図である。 2・・・位相比較器、 3 ・・・掃引発振器、4 ・
・・ループフィルタ、 5・・・電圧制御発振器、 6
 ・・・振幅検波器、 7 ・・・第一のレベル判定器
、 8 ・・・第二のレベル判定器、 9 ・・・スイ
ッチ、10・・・同期検出信号端子。 特許出願人 松下電器産業株式会社 第2図 第 図 (a) (b) +CC −CC
FIG. 1 is a block diagram showing a phase synchronization detection circuit in an embodiment of the present invention, FIG. 2 is a circuit diagram showing an amplitude detection circuit used in the phase synchronization detection circuit in an embodiment of the present invention, and FIG. 3 is an amplitude detection circuit in an embodiment of the present invention. Diagram showing waveforms of input and output signals of the detection circuit, No. 4
The figure is a block diagram of a conventional phase synchronization detection circuit. 2... Phase comparator, 3... Sweep oscillator, 4.
...Loop filter, 5...Voltage controlled oscillator, 6
...Amplitude detector, 7...First level judge, 8...Second level judge, 9...Switch, 10...Synchronization detection signal terminal. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 2 (a) (b) +CC -CC

Claims (1)

【特許請求の範囲】[Claims] 入力信号と電圧制御発振器の出力とを位相比較し、その
位相比較した出力を分岐し、一方はループフィルタに入
力し、他方は掃引発振器に入力し、前記ループフィルタ
の出力と前記掃引発振器出力を結合したのち三分岐し、
前記電圧制御発振器と振幅検波器と第二のレベル判定器
に入力し、前記振幅検波器の出力を第一のレベル判定器
に入力し、前記第二のレベル判定器の出力によりスイッ
チを制御し、前記スイッチにより前記第一のレベル判定
器の出力とロウレベルを選択して、前記スイッチの共通
端子から位相同期検出信号を得るように構成した位相同
期検出回路。
The input signal and the output of the voltage controlled oscillator are phase-compared, the phase-compared outputs are branched, one is input to a loop filter, the other is input to a sweep oscillator, and the output of the loop filter and the output of the sweep oscillator are divided. After joining, it splits into three branches,
input to the voltage controlled oscillator, amplitude detector, and second level determiner, input the output of the amplitude detector to the first level determiner, and control a switch by the output of the second level determiner. . A phase synchronization detection circuit configured to select the output of the first level determiner and a low level by the switch, and obtain a phase synchronization detection signal from a common terminal of the switch.
JP63145679A 1988-06-15 1988-06-15 Phase lock detection circuit Pending JPH022217A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP63145679A JPH022217A (en) 1988-06-15 1988-06-15 Phase lock detection circuit
US07/465,162 US5099213A (en) 1988-06-15 1989-06-14 Phase-locked oscillator with phase lock detection circuit
PCT/JP1989/000593 WO1989012930A1 (en) 1988-06-15 1989-06-14 Phase synchronous oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63145679A JPH022217A (en) 1988-06-15 1988-06-15 Phase lock detection circuit

Publications (1)

Publication Number Publication Date
JPH022217A true JPH022217A (en) 1990-01-08

Family

ID=15390582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63145679A Pending JPH022217A (en) 1988-06-15 1988-06-15 Phase lock detection circuit

Country Status (1)

Country Link
JP (1) JPH022217A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04271636A (en) * 1991-02-27 1992-09-28 Sanyo Electric Co Ltd Interface circuit and phase locked loop used therefor
CN1075532C (en) * 1994-04-28 2001-11-28 大金工业株式会社 Composite porous polytetrafluoroethylene membrane
US8534557B2 (en) 2006-03-22 2013-09-17 Bayer Innovation Gmbh Method and device for reading information optically

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04271636A (en) * 1991-02-27 1992-09-28 Sanyo Electric Co Ltd Interface circuit and phase locked loop used therefor
CN1075532C (en) * 1994-04-28 2001-11-28 大金工业株式会社 Composite porous polytetrafluoroethylene membrane
US8534557B2 (en) 2006-03-22 2013-09-17 Bayer Innovation Gmbh Method and device for reading information optically

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