JPH022217A - Phase lock detection circuit - Google Patents

Abstract

PURPOSE:To ensure the detection of a phase lock state by deciding the locking state depending on a level of a control voltage of a voltage controlled oscillator. CONSTITUTION:When a phase locked loop circuit is in the locking state, an output of a 1st level decider 7 goes to a high level and the output of a 2nd level decider goes also to a high level. Then a switch 9 is thrown to the position of a terminal (a) and an output high level of the said 1st level decider 7 becomes a phase locking detection signal. When the voltage controlled oscillator 5 is in the sweep state, the output of the 2nd level decider 8 repeats high/low levels. A synchronization detection signal goes to a low level. When the output frequency of the voltage controlled oscillator 5 is deflected out toward higher (lower) direction than the center frequency, the control voltage of the voltage controlled oscillator 5 is a positive (negative) power voltage. Thus, the output of the 1st level discriminator 7 goes to a low(high) level and the output of the 2nd level discriminator 8 goes to a high (low) level and the phase synchronizing detection signal goes to a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase synchronization detection circuit for a phase synchronization oscillator used in a local oscillator or the like.

(Prior Art) A conventional phase synchronization detection circuit has a configuration as shown in FIG.

That is, the input signal applied to the input terminal 1 and the output of the voltage controlled oscillator 5 are phase-compared by the phase comparator 2, and the output of the phase comparator 2 is branched and one is input to the loop filter 4, and the other is input to the sweep oscillator. 3, the output of the loop filter 4 and the output of the sweep oscillator 3 are combined, input to the voltage controlled oscillator 5 to form a loop, and the output of the voltage controlled oscillator 5 is branched into three, bandpass filter 17
is input to the phase comparator 2 and the oscillation output terminal 11, the output of the bandpass filter 17 is input to the amplitude detector 18, the output of the amplitude detector 18 is input to the level determiner 19, and the phase synchronization detection signal is input. It was obtained from the output terminal 10 of the level determiner 19.

(Problem to be Solved by the Invention) However, with such a configuration, if the deviation of the frequency of the voltage controlled oscillator 5 from the center frequency when synchronization is lost is small, the band of the bandpass filter 17 is narrowed. Since there is a limit to what can be done, even when synchronization is lost, the frequency of the voltage controlled oscillator 5 remains within the band of the bandpass filter 17, making it difficult to distinguish it from a synchronized state.

The present invention solves such problems and aims to reliably detect a one-phase synchronization state.

(Means for Solving the Three Problems) The technical means of the present invention for solving the above problems is to compare the phases of the input signal and the output of the voltage controlled oscillator, branch the phase-compared outputs, and divide one into a loop. one input to a filter, the other input to a sweep oscillator, the output of the loop filter and the output of the sweep oscillator are combined, and then branched into three, and input to the voltage controlled oscillator, amplitude detector, and second level determiner, The output of the amplitude detector is input to a first level determiner, a switch is controlled by the output of the second level determiner, and the output of the first level determiner and a low level are selected by the switch. , a phase synchronization detection signal is obtained from a common terminal of the switch.

(for production) The effect of this technical means is as follows.

That is, in a synchronous state, the first level determiner and the second level determiner determine that the control voltage of the voltage controlled oscillator is a certain DC value lower than the positive ffl source voltage; If it is a negative power supply voltage, it is determined by the first level determiner, if it is a negative power supply voltage, it is determined by the second level determiner, and if it is in a sweep state, it is detected by the amplitude detector and then determined by the first level determiner. do. In this way, since the synchronization state is determined based on the level of the control voltage of the voltage controlled oscillator, the phase synchronization state can be reliably detected.

(Example) FIG. 1 shows an example of the present invention. 2 is a phase comparator,
Input terminal 1. The input signal applied to the voltage controlled oscillator 5
Compare the phase with the output of 4 is a loop filter which obtains a signal from the output of the phase comparator 2 from which noise and high frequency components are removed. A sweep oscillator 3 provides a sweep signal to the voltage controlled oscillator 5. 8 is a second level determiner which outputs low if the control voltage of voltage controlled oscillator 5 is negative, and outputs high if Ov or positive. 6 is an amplitude detector which detects the amplitude of a positive voltage. A specific example of the amplitude detector 6 is shown in FIG.

12 is an input terminal, 13 is a detection diode, 14 is a resistor, 15 is a capacitor, and 16 is an output terminal.

Reference numeral 7 designates a first level determiner, which outputs a low signal if the output of the amplitude detector 6 is a positive power supply voltage, and a high signal if the output is below the positive power supply voltage. 9 is a switch, and if the output of the second level determiner 8 is low, it is low level (terminal b)
If the output of the second level determiner 8 is high, the output of the first level determiner (terminal a) is selected.

Next, the operation will be explained. First, when the phase locked circuit is in a synchronous state, the synchronous state is detected. In other words, since it is in a synchronous state, it takes a DC value between the control voltage Ov of the voltage controlled oscillator 5 and the positive power supply voltage, and the output of the amplitude detector 6 becomes a DC voltage of the same level. Therefore, the output of the first level determiner 7 becomes high. Also, the output of the second level determiner becomes high.

Therefore, the switch 9 selects the terminal a, and the high output of the first level determiner 7 becomes the phase synchronization detection signal.

Next, when the phase-locked circuit is in an asynchronous state, there are the following three states. First, when the voltage controlled oscillator 5 is in a sweep state, second, when the output frequency of the voltage controlled oscillator 5 swings higher than the center frequency, and third, when the output frequency of the voltage controlled oscillator 5 is at the center This is when the frequency swings completely below the frequency.

First of all, when the voltage controlled oscillator 5 is in the sweep state, the control voltage of the voltage controlled oscillator 5 has a sawtooth waveform as shown in FIG. 3(a). Therefore, the output of the amplitude detector 6 becomes a positive power supply voltage as shown in FIG. 3(b). Therefore, the output of the first level determiner 7 becomes low. Further, the output of the second level determiner 8 repeats high and low, and the switch 9 repeats switching between terminal a and terminal S, but since both terminal a and terminal A are low, the synchronization detection signal becomes low. Note that the switch 9 is always connected to the terminal a or terminal A at the moment of switching.

Second, when the output frequency of the voltage controlled oscillator 5 swings higher than the center frequency, the control voltage of the voltage controlled oscillator 5 becomes a positive power supply voltage.

Therefore, the output of the amplitude detector 6 becomes a positive power supply voltage.

Therefore, the output of the first level determiner 7 becomes low.

Further, the output of the second level determiner 8 becomes high. Therefore, switch 9 selects terminal a, and the phase synchronization detection signal becomes low.

Thirdly, when the output frequency of the voltage controlled oscillator 5 swings lower than the center frequency, the control voltage of the voltage controlled oscillator 5 becomes a negative power supply voltage.

Therefore, the output of the amplitude detector 6 becomes Ov. Therefore, the output of the first level determiner 7 becomes high. Further, the output of the second level determiner 8 becomes low. Therefore, the switch 9 selects the terminal 1, and the phase synchronization detection signal becomes low. As described above, a phase synchronization detection signal that is high when in a synchronous state and low when in an asynchronous state is obtained.

(Effects of the Invention) As described above, according to the present invention, there is an excellent effect that a phase synchronization detection signal can be reliably obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a phase synchronization detection circuit in an embodiment of the present invention, FIG. 2 is a circuit diagram showing an amplitude detection circuit used in the phase synchronization detection circuit in an embodiment of the present invention, and FIG. 3 is an amplitude detection circuit in an embodiment of the present invention. Diagram showing waveforms of input and output signals of the detection circuit, No. 4
The figure is a block diagram of a conventional phase synchronization detection circuit. 2... Phase comparator, 3... Sweep oscillator, 4.
...Loop filter, 5...Voltage controlled oscillator, 6
...Amplitude detector, 7...First level judge, 8...Second level judge, 9...Switch, 10...Synchronization detection signal terminal. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 2 (a) (b) +CC -CC

Claims (1)

[Claims] The input signal and the output of the voltage controlled oscillator are phase-compared, the phase-compared outputs are branched, one is input to a loop filter, the other is input to a sweep oscillator, and the output of the loop filter and the output of the sweep oscillator are divided. After joining, it splits into three branches,
input to the voltage controlled oscillator, amplitude detector, and second level determiner, input the output of the amplitude detector to the first level determiner, and control a switch by the output of the second level determiner. . A phase synchronization detection circuit configured to select the output of the first level determiner and a low level by the switch, and obtain a phase synchronization detection signal from a common terminal of the switch.