JPS5821862B2 - phase synchronized circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase locked circuit having a function of expanding the locking frequency range.

Conventionally, in phase-locked circuits, one method of expanding the frequency range (so-called synchronization pull-in frequency range) in which the circuit goes from an asynchronous state to a synchronous state was proposed in the Japanese Patent Publication No. 51.
-10752, a circuit using an oscillator that automatically stops oscillation due to a change in the internal impedance of the phase locked circuit is used.

When this circuit is used as a phase locked circuit of an N-phase phase demodulation circuit, the clock frequency is set to fc.
Then, a so-called pseudo-lock-in phenomenon occurs in which synchronization is maintained at a frequency that has changed by fc/n (n is a positive integer), and if this pseudo-lock-in frequency exists within the desired lock-in range of the phase-locked circuit, then As a result of pseudo-pull-in, the impedance in the loop decreases and the oscillation circuit with a self-control function stops oscillating, so the pseudo-pull-in state may be maintained and a correct demodulated signal may not be obtained.

FIG. 1 is a block diagram of a conventional circuit, in which 1 is a signal input terminal, 2 is an N-phase phase demodulation circuit, 3 is a voltage controlled oscillation circuit, 4 is an N-phase phase modulation circuit, 5 is a phase detection circuit, and 6 and 7 are resistance circuits, 8 is a low-pass filter circuit, and 9 is an oscillation circuit having a self-control function.

In this operation, first, an N-phase phase modulation signal is applied to the signal input terminal 1, and the phase is demodulated by the N-phase phase demodulation circuit 2 using the output signal of the voltage controlled oscillation circuit 3 as a reference carrier wave.

On the other hand, the input signal branched between the input terminal 1 and the N-phase phase demodulation circuit 2 is applied to the N-phase phase modulation circuit 4, where N
Phase modulation is performed by the demodulated output of the phase demodulation circuit 2.

This N-phase phase modulation circuit has the following characteristics for input N-phase phase modulation signals.

Phase modulation is performed so as to cancel the modulation component, and N phase]-
A carrier wave signal is obtained at the output of the 1' modulation circuit 4.

This carrier signal is applied to a phase detection circuit 5, and its phase is compared with the output of the voltage controlled oscillation circuit 3.

The output of this phase detection circuit 5 is low in the resistance circuits 6 and 7.

The signal is applied to the voltage controlled oscillation circuit 3 via the area filter circuit 8, and controls the output frequency of the voltage controlled oscillation circuit so as to achieve phase synchronization.

The oscillation circuit 9 having a self-control function is branch-connected between the resistor circuits 6 and 70, and when the phase-locked loop is in the synchronous pull-in state, the impedance when looking inside the loop from between the resistor circuits 6 and 7 is as follows. Since the voltage becomes almost zero, the oscillation circuit 9, which has a self-control function, stops oscillating.

However, when the phase-locked loop is in an asynchronous state, the impedance seen inside the loop is the resistance value series R of the resistor circuits 6 and 7.
, R2 are R1 and R2, respectively. Since □ and R, +R2 have a somewhat high impedance, the oscillation circuit 9 having a self-control function starts oscillating, and as a result, the synchronous pull-in frequency is expanded.

However, N phase. In a phase synchronized circuit for a phase modulated wave, when the clock frequency is fc, synchronization occurs at a frequency shifted by fc/n (n is a positive integer), that is, so-called pseudo-locking occurs.

This situation is shown in the characteristic diagram of FIG.

In FIG. 2, the horizontal axis represents the difference frequency between the input frequency and the oscillation frequency of the voltage controlled oscillation circuit 3, and the vertical axis represents the control voltage 10 of the voltage controlled oscillation circuit.

The diagonal lines A, B1 to B6 indicate a state in which synchronous pull-in is being performed, A indicates a correct synchronous pull-in state, and B1. B2...
. . B8 represents a state of pseudo-retraction, and the uneven line represents an asynchronous state.

In the figure, a represents the synchronization pull-in range in the absence of the oscillation circuit 9 having a self-control function, and range b1 represents the synchronization pull-in range to be obtained.

In the conventional circuit, when the output of the oscillation circuit 9 having a self-control function is increased in order to obtain the synchronous pull-in range, state B
1 or B2, the loop impedance decreases, the oscillation operation of the oscillation circuit 9 stops, and the '1. There is a drawback that the synchronization pull-in ends while the state B1 or B2 remains, and the phase synchronization circuit may not operate correctly.

An object of the present invention is to provide a phase-locked circuit that can avoid such pseudo-synchronous pull-in. , and an oscillation circuit which has a function of sustaining oscillation for an arbitrary period of time when a synchronized state is attained, and then stopping oscillation, are branch-connected in a loop.

This is a very effective means for expanding the locking frequency range of the phase synchronization circuit used in the N-phase phase demodulation circuit for the N-phase phase modulation signal.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram of an embodiment of the present invention, in which 1 to 8 are the same as in FIG. 1, 11 is a means for determining the phase synchronization state, and 12 is a means for determining a phase synchronization state, and 12 is a means for stopping oscillation after it continues for an arbitrary period of time. Oscillation circuits 101 and 102 having functions are oscillation circuits, 1
03 is a bandpass filter circuit that passes only the output signal of the oscillation circuit 101; 104 is a level detection circuit that has a function of determining whether the output signal level of the bandpass filter circuit 103 is below a threshold value; and 105 is a level detection circuit. a control circuit 106 having a function of passing or cutting off the output signal of the oscillation circuit 102 according to the output signal of the oscillation circuit 104 and the output signal of the counting circuit 106;
is the control circuit 10 based on the output signal of the level detection circuit 104.
This counting circuit has a function of counting the number of repetitions of the output signal No. 5 and sending a signal to the control circuit 105 to turn off the signal when the value reaches a predetermined number of times.

The output terminal of the oscillation circuit 101, the input terminal of the bandpass filter circuit 1030, and the output terminal of the control circuit 105 are all branch-connected to the connection point between the resistance circuits 6 and 7.

The output signal of the bandpass filter circuit 103 is sent to the level detection circuit 104.
The output signal of the level detection circuit 104 is applied to the first input terminal of the control circuit 105 and the counting circuit 10.
6 to the first input terminal.

The output signal of the oscillation circuit 102 is connected to the second input terminal of the control circuit 105, and the output signal of the oscillation circuit 102 is connected to the third input terminal of the control circuit 105.
06 output signal is connected.

The output signal of control circuit 105 is connected to a second input terminal of counting circuit 106 .

The operation will be explained below.

The output signal of the oscillator circuit 101 is selected to have a very low frequency, for example, about several + 1000 Hz, and a low level that has no effect on the phase-locked loop.

As mentioned above, when the phase-locked loop is in the synchronous state, the impedance within the phase-locked loop is low, so the output level of the oscillation circuit 101 becomes a very low level, and the level detection circuit 104 detects that it is below the threshold, that is, in the synchronous state. is detected.

When the phase-locked loop is in an asynchronous state, the impedance within the loop is high, so the output level of the oscillation circuit 101 increases, and the level detection circuit 104 detects the asynchronous state.

The output signal of this level detection circuit 104 is transmitted to the control circuit 10.
5 and the first input terminal of the counting circuit 106.

When the phase-locked circuit is in an asynchronous state, control circuit 1
05 passes through and sends out the output signal of the oscillation circuit 102, the counting circuit 106 resets the contents of the counting circuit to zero, and sends a signal indicating that the predetermined count value has not been reached as the output signal of the counting circuit to the control circuit 105. to the third input terminal of.

In this state, the output signal of the oscillation circuit 102 is added to the phase-locked loop, so the output frequency of the voltage-controlled oscillation circuit 3 changes depending on the output voltage, and a sweep for synchronization is performed.

In this state, if synchronization of the phase-locked loop is established (in this case, it may be a correct synchronization pull-in or a pseudo-synchronization pull-in), the level detection circuit 104 detects the synchronization state, and the synchronization state is established. A signal is sent from the output indicating that the

The control circuit 105 does not operate in response to this output signal.

On the other hand, the counting circuit 106 starts a counting operation by this output signal, and counts the number of repetitions of the output signal of the control circuit 105.

When the count value reaches a predetermined value, the counting circuit 105
sends a signal indicating the counting completion state to the third input terminal of the control circuit 105, and the control circuit 105 operates to turn off the output signal of the oscillation circuit 102.

A waveform diagram at each point in this case is shown in FIG.

201 to 207 in FIG. 4 are the signals 201 to 20 in FIG.
7.

An example of the retracting operation in this case is shown in the characteristic diagram of FIG.

The arrows in the figure represent temporal state changes, the horizontal axis represents the difference frequency between the input frequency and the oscillation frequency of the voltage controlled oscillation circuit 3, and the vertical axis represents the input signal 10 of the voltage controlled oscillation circuit 3.
represents.

Normally, state A representing a normal retracted state is different from B1, which is a pseudo retracted state. B2...The frequency range is sufficiently wider than B6.

Now, if the state at the time of starting synchronization pull-in is represented by 01, and the sweep circuit starts operating so that the frequency difference ΔF becomes ΔF → 0, state C1 moves to the left in the figure, and state C2
A pseudo-synchronized state B2 occurs at the point.

In the conventional synchronous circuit, the synchronous pull-in ends in this state, and C2
It moved from point D to point D, stopped at point D, and was pseudo-fixed.

(201 in FIG. 4) The circuit of the present invention does not immediately stop the sweep (oscillation) in this state, but continues the sweep from point C2 to point C3.

(Do not stop at time T, as shown in 205 in Figure 4, but operate until time T2.) Here, the sweep width (i.e., 20
By selecting the amplitude (amplitude of
4 points, further moves toward the maximum point C5 of the sweep, and then vibrates so as to move toward another maximum point C6.

After moving in C5 to C6 the number of times determined by the counting circuit 106 (i.e., time T2-T1) in this way, C7
The sweep ends at the point.

That is, by continuing the T2 oscillation for a predetermined period of time and then stopping the oscillation circuit 120, by continuing the sweep for several cycles even after it is determined that synchronization pull-in has been established, even if the pseudo Even if the synchronous pull-in occurs, the normal synchronous pull-in state can be achieved eventually.

Note that the waveform of the coupling portion of the resistance circuits 6 and 7 is shown in FIG.
As shown in FIG. 2, when out of synchronization, the sweep signal 205 and the low level oscillation signal 201 form a heavier waveform, and when in synchronization, the impedance in the loop decreases, so the low level sweep signal 205 is connected for a certain period of time.

The block diagram in FIG. 6 is an embodiment in which the present invention is applied to a so-called re-modulation type phase-locked circuit, and the block diagram in FIG. 7 is an embodiment in which the present invention is applied to a so-called base frequency band signal processing type phase-locked circuit. be.

In this figure, numeral 20 is a signal processing circuit which receives the output signal of the phase demodulation circuit and generates a phase synchronization signal, and a specific example of this circuit is shown in Japanese Patent Publication No. 46-2695.

FIG. 8 shows another embodiment of the oscillation circuit 12 of the present invention,
301 is a 1/m frequency dividing circuit.

That is, the output of the oscillation circuit 101 is supplied to the terminal 403 of the oscillation circuit 12, and the frequency is divided by 1/m to generate the oscillation signal 204.
shall be.

, Therefore, in this case, the number of oscillation circuits is small.

FIG. 9 shows another embodiment of the oscillation circuit of the present invention, which oscillates when the phase-locked circuit is in an asynchronous state and continues to oscillate for a predetermined period of time when the phase-locked circuit becomes in a synchronous state.

In the figure, 501 is an up/down counting circuit;
02 is a D/A conversion circuit.

The operation of this circuit starts from the terminal 401 to the control circuit 28.
When a control signal 203 that changes from synchronous to asynchronous is given, UP/DOW which is UP (or DOWN)
The N counter 501 starts counting the oscillation signal 201 supplied from the input terminal 403.

When the output of this counter 501 reaches a predetermined count value, the counting direction is reversed to DOWN (or OP) and counting is continued.

Repeating this UP/DOWN, the D/'A converter 5
02 converts it into a triangular wave analog voltage and outputs it to terminal 40.
1 output from 2, and the control circuit 16 receives the control signal 2
03 changes from asynchronous to synchronous, a predetermined number of UP (or DOWN) signals are counted, and the counting of the counter 501 is stopped.

Naturally, the present invention can also be applied to a general phase synchronization circuit composed of a voltage controlled oscillation circuit, a phase detection circuit, and a low-pass filter circuit.

Further, the resistor circuits 6 and 7 can be omitted by substituting the output impedance of the phase detection circuit 5 and the input impedance of the low-pass filter circuit 8, respectively.

Therefore, by using the present invention, it is possible not only to expand the locking frequency of a general phase-locked circuit, but also to
Even in a phase-locked circuit that causes pseudo-locking, such as a phase-locked circuit for N-phase phase demodulation, it is possible to stably cause normal lock-in.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional phase synchronization circuit, Fig. 2 is a conventional operating characteristic diagram, Fig. 3 is a block diagram of an embodiment of the present invention, Fig. 4 is a waveform diagram explaining the operation of the present invention, and Fig. 4 is a waveform diagram explaining the operation of the present invention. 5 is an operational characteristic diagram of the present invention, FIGS. 6 and 7 are block diagrams of second and third embodiments of the present invention, and FIGS. 8 and 9 are diagrams of other embodiments of the oscillation circuit 12 of the present invention. FIG. 2 is a block diagram of an embodiment. In the figure, 1... Signal input terminal, 2... N-phase phase demodulation circuit, 3... Voltage controlled oscillation circuit, 4... N-phase phase modulation circuit, 5... Phase detection circuit, 6, 7... Resistance circuit, 8... Low-pass filter circuit, 9... Oscillator circuit having self-control function, 10... Input voltage of voltage control circuit,
DESCRIPTION OF SYMBOLS 11... Phase synchronization detection means, 12... Oscillation circuit that oscillates in an asynchronous state and continues oscillation for a predetermined time in a synchronous state, 20... Signal processing circuit, 101,
102...Oscillation circuit, 103...Band filter circuit, 1
04... Level detection circuit, 16, 105... Control circuit, 106... Counting circuit, 201... Oscillation circuit 10
1 output signal, 202... output signal of the band filter circuit 103, 203... output signal of the level detection circuit 104,
204... Output signal of the oscillation circuit 102, 205-...
Output signal of control circuit 105, 206... counting circuit 10
6 output signal, 301...1/m frequency dividing circuit, 401,
403...Input terminal, 402...Output terminal, 50
1 =-uplD OWN counting circuit, 502...D/
This is an A conversion circuit.

Claims (1)

[Scope of Claims] 1. A voltage controlled oscillator circuit that generates a variable frequency output signal according to a predetermined control voltage; a phase-locked loop of a polyphase phase-locked circuit including a phase comparator that supplies the control voltage as a control voltage; Maintaining the pseudo-entrainment during the oscillation continuation period from the time when the detection signal of the detection means detects the asynchronous state of the phase-locked loop to the time when the detection signal detects synchronization and the time required to escape from the pseudo-entrainment state. A phase synchronization device comprising: low frequency oscillation means for forming a frequency sweep voltage with an amplitude fluctuation voltage larger than the normal pull-in holding range; and means for supplying the low frequency sweep voltage to the voltage controlled oscillator together with the control voltage. circuit. 2. The phase synchronization detection means includes an oscillator that is connected to the phase synchronization loop and starts or stops oscillation at a predetermined frequency depending on synchronization or non-synchronization of this loop, and oscillation detection means that detects the presence or absence of an oscillation output of this oscillator. A phase-locked circuit according to claim 1. 3. The low frequency oscillation means includes a counting control means for outputting a predetermined count signal during the oscillation continuation period after detecting the oscillation output of the oscillation detection means, and receiving and receiving a count signal output from the counting control means. A reversible counter that periodically performs reversible counting, and the output of this reversible counter according to its counting output,
3. The phase locked circuit according to claim 2, further comprising a D/A converter that performs D/A conversion to obtain the low frequency sweep voltage.