JPH0468633A - Secondary data channel transmission system - Google Patents

Abstract

PURPOSE:To keep DC balance and to make transmission by sending a secondary data channel depending whether or not a bipolar violation is to be set for each even number of times of a frame bit being logical 1. CONSTITUTION:A frame pulse FP is incoming to a terminal 10, the pulse FP is subject to bipartite frequency division at a flip-flop 11 and a counter 12 outputs a carry every time a counter 12 counts four period of the pulses FP. A secondary channel data SC is incoming to a terminal 13 and a NAND circuit 14 generates a signal multiplexed with the secondary channel for only once at four periods of the frame pulse. An output of a flip-flop 15 is extracted to be a pulse width of the frame pulse FP at AND circuits 16,17 when the frame pattern is logical 1 respectively and positive logic FP+ and negative logic FP- being bipolar pulses are outputted respectively from terminals 18,19.

Description

[Detailed Description of the Invention] [Summary] Regarding a secondary data channel transmission method for transmitting a secondary data channel for network maintenance and monitoring, it is possible to transmit secondary data without changing the frame configuration or signal speed and without destroying the DC balance. A transmission system that transmits digital data to a network using a bipolar code with logic II+ and a pulse, with the purpose of channel transmission being to construct a frame with frame bits set for each predetermined number of bits. In a secondary data channel transmission method that transmits a secondary data channel for maintenance monitoring, logic 1) determines whether or not to set a bipolar violation for every even number of frame bits that become 1. Logic correspondingly determined and configured to transmit the secondary data channel.

[Industrial application field]

The present invention relates to a secondary data channel data transmission system, and more particularly, to a secondary data channel transmission system for transmitting a secondary data channel for network maintenance and monitoring.

[Conventional technology]

The signal format on the subscriber line of the digital data transmission system is 6-bit data D1 as shown in Figure 7.
~D6 is surrounded by frame bits F and status bits S in an envelope format. The code is AMI (alternate mark inversion), which is a type of bipolar code suitable for baseband transmission.
symbol is used.

Frame bit F is a bit for recognizing the frame phase of the envelope, and is used as a frame pattern (,1,
(1) A police box is used. The status bit S indicates whether or not communication is in progress; Ijl indicates that communication is in progress, and +01 indicates that communication is not in progress. Furthermore, by combining the status bit s='o' and the data bit pattern, various information as shown in FIG. 8 can be transmitted as a control code from the network.

[Invention or problem to be solved]

In recent years, these data transmission systems have been required to provide secondary data channels for network maintenance and monitoring in addition to the main signal transmission function, in response to demands for larger scale systems and higher system reliability. is necessary. However, if a secondary data channel is to be time-divisionally transmitted using the existing subscriber line signal format, it is necessary to increase the signal speed. As a result, there is a problem in that the transmission distance of the subscriber line is limited. Furthermore, it was necessary to change the frame format, signal speed, etc. from the existing system, making it unsuitable for expansion of the existing system.

The present invention has been made in view of the above points, and its primary purpose is to provide a secondary data channel transmission method that transmits secondary data channels without changing the frame structure or signal speed and without disturbing the DC balance. do.

[Means to solve the problem]

The secondary data channel transmission method of the present invention configures a frame with frame bits provided for each predetermined number of bits,
In a transmission system that transmits digital data to a network using a bipolar code with a pulse at logic 1)', a frame that becomes logic Ill in a secondary data channel transmission system that transmits a secondary data channel for network maintenance and monitoring. Whether or not to set a bipolar violation for every even number of bits is determined in accordance with the logic of the data of the secondary data channel, and the secondary data channel is transmitted.

[For use]

In the present invention, the secondary data channel is transmitted depending on whether bipolar violation is set or not for every even number of frame hits where logic 1) is 1, so even if bipolar violation is set, DC balance is not maintained. There is no need to change the frame structure or signal rate.

〔Example〕

FIG. 1 shows a configuration diagram of an embodiment of a transmitting circuit according to the present invention.

In the figure, a frame pulse FP shown in FIG. 2(A) with a frame period is input to the terminal 10, and this frame pulse F
P is frequency-divided by 1/2 by the JK flip-flop 11 which performs T-type operation according to the clock input, and a (1,0) alternating frame pattern signal shown in FIG. 2(B) is generated here. In addition, the 2-bit counter 12 receives the frame pulse FP.
A carry shown in FIG. 2(C) is output every time four cycles of are counted.

The terminal 13 receives secondary channel data S shown in FIG. 2(D).
C comes in, and the secondary channel data SC is sent to the NAND circuit 14.
By calculating the frame pattern signal of the output of the flip-flop 11 and the carry of the output of the counter 12, the signal shown in FIG. Ru.

The JK flip-flop 15, which performs T-type operation based on the clock input, normally receives a frame pattern signal, alternates every 1)', or receives secondary channel data! JK large input when 1'
0', the alternation is stopped to generate the signal shown in FIG. 1′
The pulse width of the frame pulse FP is taken out from terminals 18 and 19, respectively, as shown in FIG. 2 (G).

The plus side and minus side logics FP+ and FP- of the bipolar pulse shown in (H) are output.

Due to the alternating stop of the flip-flop I5, frames of pattern 111 are sent out twice in succession with the same polarity,
A violation occurs in a frame pattern. This frame pattern of frame bits is multiplexed with other data bits and control bits and sent to the subscriber line as a bipolar signal.

This circuit transmits secondary channel data bits (SC) once every four frames. When the secondary channel data bit is '1', the frame bit F has the same polarity as the frame bit F two frame periods before, as shown in FIG. 3(A), that is, there is a bipolar violation between the frame bits. On the other hand, when the secondary channel data bit is '01, as shown in FIG.
In other words, there is no bipolar violation. The frame bit of logic 1)' which does not set bipolar violation is always set to have the opposite polarity to the frame hit one frame period before.

FIG. 4 shows a circuit configuration diagram of an embodiment of the receiving circuit according to the present invention.

In the figure, each of the terminals 21 and 22 is shown in FIG. 5(A).

The plus side and minus side frame pulses FP+ are extracted from the bipolar signal shown in (B).

FP- is received, and a frame pattern signal with a two-frame period shown in FIG. Flip-flop 24 is a frame pulse F
It is set by P+, reset by frame pulse FP-, and outputs the signal shown in FIG. 5(D) from its Q terminal.

The Q terminal output of the flip-flop 24 is directly supplied, and then delayed by one period of the frame pattern, that is, two frame periods, by the D flip-flop 25, and then supplied to the AND circuit 26. Here, it is detected that the same polarity has continued for two frame periods, and the second A signal shown in FIG. 5(F) is generated, and this signal is expanded to a pulse width of 4 frame periods by a D flip-flop 27 and an OR circuit 28 to become a signal shown in FIG. 5(G) and supplied to an OR circuit 29. be done.

Similarly, the terminal output of flip-flop 24 is directly and D
A flip-flop 30 delays the frame pattern by one period, that is, two frame periods, and supplies the signal to an AND circuit 31, which detects that the same polarity continues for two frame periods and generates the signal shown in FIG. 5(H). This signal is expanded by the D flip-flop 32 and the OR circuit 33 to a pulse width of 4 frame periods, and is supplied to the OR circuit 29 as a signal shown in FIG. 5(I).

The OR circuit 29 obtains the secondary channel data SC shown in FIG. 5(J) and outputs it from the terminal 33.

By the way, if the logic '1' exists between two bipolar violations an even number of times, the consecutive violations will have the same polarity as shown in FIG. 6(A), and the DC balance will be disrupted. However, as shown in FIG. 6(B), if logic 11' exists an odd number of times, there will be continuous violations or the polarity will be reversed, and the DC balance will be maintained. Generally, the number of times that logic 1) appears in a data bit is not determined, so setting a violation with the previous bit including the data bit may disrupt the DC balance. However, if we focus only on the frame bits, the logic 11Z+□+ is fixed, so the number of occurrences of the logic 1)' within a specific period is known. Therefore, if a violation is set every cycle in which logic 111 appears an even number of times, the number of times logic 1)' appears between violations will always be an odd number, so DC balance can be maintained. Also, at this time, for bits other than the F bit, F
If the polarity is always set to 11' or the opposite polarity except for the bit, the DC balance can be maintained as a whole.

In the present invention, since the frame bit pattern is (1°0) alternating and appears 11+ or 2 times within 4 frame periods, by setting 1 violation bit in 4 frame periods, the number of II+ between violation bits can be reduced. or an odd number, and the DC balance is maintained as in FIG. 6(B).

Note that the frame bit F is '11' instead of (1,0) alternating.
If it is fixed to , violation pits can be set and transmitted at two-frame intervals, and the invention is not limited to the above embodiment.

In this way, the secondary data channel is transmitted depending on whether bipolar violation is set or not for every even number of frame bits that result in logic 111.
Even if a violation is set, the DC balance can be maintained, and there is no need to change the frame configuration or signal speed.

〔Effect of the invention〕

As described above, according to the secondary data channel transmission method of the present invention, it is possible to transmit the secondary data channel without changing the frame configuration or signal speed and without destroying the DC balance, which is extremely useful in practice. be.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a transmitting circuit according to the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit in FIG. 1, and FIGS.
Each figure is a diagram for explaining bipolar violation, Figure 4 is a circuit configuration diagram of an embodiment of the receiving circuit according to the present invention, Figure 5 is a signal waveform diagram of each part of the circuit in Figure 4, and Figure 7 is a diagram for explaining bipolar violation. The figure shows the signal format, and FIG. 8 shows the control code. In the figure, 11.15.24 are JK flip-flops, 12 is a counter, 14 is a NAND circuit, 16.17, 26.31 are AND circuits, 25.27, 3
0.32 is a D flip-flop, and 28.29.33 is an OR circuit. The same diagram for explaining bipolar violation.

Claims (2)

[Claims] (1) A transmission system that transmits digital data to a network using a bipolar code in which a frame is composed of frame bits provided for each predetermined number of bits, and a logic '1' indicates a pulse. In the secondary data channel transmission method that transmits the secondary data channel, whether or not bipolar violation is set for every even number of frame bits that become logic '1' is determined in accordance with the logic of the data of the secondary data channel. A secondary data channel transmission method characterized in that: determining and transmitting a secondary data channel. (2) The frame bit has a pattern of alternating logic '1' and '0', and it is determined whether or not to set a bipolar violation to the frame bit which becomes logic '1' every four frames. A secondary data channel transmission system according to claim (1).