JPS58169614A - Bus control system - Google Patents

Abstract

PURPOSE:To prevent the breakdown of a bus control system due to the permanent waiting for answer although an access is erroneously given to an undefined region, by providing a circuit which delivers an answer signal in a fixed time after a command is given to a slave device from a processor. CONSTITUTION:Slave devices 3A, 3B... like a parity checker 7, a memory, an I/O device, etc. are connected to a CPU1 via a bus 2. At the same time, an answer signal generating circuit 9 is provided to the CPU1. Then the CPU1 gives an access to a specific slave device such as 3B and transmits a bus command BCS. The command BCS is supplied also to the circuit 9, and an answer signal ABS is supplied to the CPU1 in the lapse of a fixed time T. The I/O3B has a low working speed and does not finish its process within the time T. Thus the I/O3B transmits an answer inhibiting signal AIS to the circuit 9 to inhibit the output of the signal ABS. When the I/O finishes its process, the transmission of the signal AIS is stopped and the signal ABS is transmitted. As a result, an answer is given after a period of time T although the CPU1 gives erroneously an access to an underfined region. Thus, the permanent waiting for answer is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention In the present invention, the CPU is under the control of the CPU. The present invention relates to a control method for a bus of a response confirmation type in which when a bus command signal is output to a device (hereinafter referred to as a "slave device"), a response signal corresponding to the command is output from the slave device.

(2) Technical background FIG. 3 is a block diagram of an information processing system showing a conventional bus control method, and FIG. 4 is a time chart of bus control in the system of FIG. 3.

Normally, in response confirmation type buses, Figures 3 and 4 are
As shown in the figure, when the CPU 1 is busy, it accesses a specific slave device and outputs a bus command signal BC8 from l'' to 0#, which instructs the slave device to read and write.

Then, the response signal AB8 becomes 11 when the slave device has fixed the data DATA on the bus 2.
# is output as @0'' and after a certain period of time after signal AB8 becomes @0'', signal BC8 returns from @O'' to 11'', completing the bus cycle of the CPU 1.

(31 Prior Art and Intercondylar Point However, in this method, if the CPU 1 mistakenly accesses the non-existent Isshu definition area of the slave devices 3A, 3B, 3D, etc., the device that outputs the response signal AB8 Since the CPU 1 does not exist, there is a drawback that the CPU 1 becomes in a state of waiting for a permanent response and the system goes down.

(4) Purpose of the Invention In order to eliminate the above-mentioned drawbacks, the present invention aims to provide a bus control method that does not cause a permanent response wait even when a CPU accesses an undefined area where a slave device does not exist. It is something to do.

(5) Structure of the Invention In other words, the present invention provides a response signal generation circuit, outputs a response signal after a certain period of time after outputting the bus command signal, and also performs a parity check on data on bus t. It is composed of

(6) Embodiments of the Invention The present invention will be specifically described below based on embodiments shown in nine drawings.

FIG. 1 shows a block diagram 21st!21ti! showing an example of an information processing system to which the present invention is applied. 2 is a time chart of bus control in the system shown in FIG. 1;

As shown in FIG. 1, the information processing system 5 has a busy CPU
1, and the CPU 1 is connected to slave devices such as a parity checker 7, memory, and input/output devices via a bus 2.
3A, 3B*3D, 3g... are connected. Further, a response signal generation circuit 9 is connected to the CPU 1, and the slow slave device 3 is connected to the circuit 9.
B, 3C, and 3D are connected via a response inhibit 112a in bus 2.

Since the information processing system 5 has the above configuration, the CPU 1 normally accesses a specific slave device (for example [3B) t-7 and sends the bus command signal BC8, as shown in FIG. @ Change from l” to 10”. Signal BC!
It is also input to the S Fi response signal generation circuit 9;
After inputting the signal BO8, the response signal A is output for a certain period of time Tvl.
] 3S automatically C! It has a function to output to PU 1, and the operation speed is slow and data D'A T
1. Device 3B cannot ensure that A is on path 2. Response prohibition signal Al8t? -1'' to 0# to inhibit the output of the response signal AE8 from the circuit 9 via the inhibit #!2a.

When the device determines data I)YA to bus 21Kll,
The device 3 Bt signal AI8 changes from @0' to 1 bit, and in response to this, the circuit 9 outputs the response signal A]38 as "1" and °02, and returns the I number BO8 of the CPU 1 to "1" to complete the bus cycle. terminate.

Even if the CPU 1 accesses an undefined area where no slave device exists, the response signal generation circuit 9 outputs the response signal AB8 to the CPU 1 after a certain period of time T, so the CPU 1ti will not be permanently busy waiting for a response. do not have. Also,
Since no data data is established on bus 2, all data lines and parity lines within bus 2 are "l".
"(Also, Fi@o" becomes a parity error state. When the signal BO8 becomes @l, the parity checker 7 immediately detects a parity error by checking the parity of the data on the bus 2. The CPU 1 can immediately know of the abnormality.

Note that the slave device flsAFi receives data D within time T.
Since ATA can be fixed to bus 2, there is no need to have a response inhibit line 2a, and the signal Al1 from circuit "9"
No problem occurs even if the bus cycle of CPU 1 is completed at 8.

(7; As described in detail, according to the present invention, the response signal generation circuit 9 is provided, and the response signal AB8 is output after a certain period of time T after the output of the bus command signal BC8. Since the parity of the data DATA on system 5 is changed, it is possible to prevent the occurrence of the permanent response waiting state of CPU 1, and CPU 1 is
It is possible to immediately recognize an abnormality as a parity error, making it possible to provide a bus control system with high reliability.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a block diagram showing an example of an information processing system to which the present invention is applied; Fig. 1 is a time chart of bus control when the system is busy; Fig. 3 is a conventional system. FIG. 4 is a block diagram of an information processing system showing a bus control method, and is a time chart of bus control in the system of FIG. 3. 1...CPU 2...Path 3A, 3B, 3D, 3g...Slave device T...Parity checker 9...Response Signal generation circuit BO2...Pass command signal AB8...Response signal T...Certain time Applicant Fujitsu Limited Agent Patent attorney Hiroshi Matsuoka Department

Claims (1)

[Claims] In the response confirmation method, when a bus command signal is output from the processing device to the slave device fK via the bus, the slave device outputs one response signal corresponding to the command signal. A bus system, a foot power system, configured to output a response signal after a certain period of time after outputting the bus command signal, and to check the parity of data on the bus.