JPS5891598A - Data processor - Google Patents

Abstract

PURPOSE:To prevent a malfunction, by providing a means for decoding and holding only a specified address signal from a CPU at the time of an instruction fetch cycle, and a means for inputting a command signal from the CPU to a memory by said decoding signal at the time of an execution cycle. CONSTITUTION:An instruction cycle is time-constituted of an instruction fetch cycle T1 and an execution cycle T2. In the cycle T1 and the cycle T2, a signal for designating an address where an instruction in a memory 21 is stored, and a signal for designating an address where write is executed are outputted, respectively, from a CPU20. A signal outputted in T1 is decoded, and if it is a signal from a specified program, it is held by an FF circuit 28. In the cycle T2, a write data signal is inputted to the memory through an AND circuit 29 by the held decoding signal. In this way, in a state that plural programs are processed by keeping pace with each, a malfunction is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to the numerals of a data processing device with a memory protection function.

Technical background of the invention Generally, a central processing unit (hereinafter referred to as CPU) and a storage device (
In data processing devices such as electronic computers equipped with memory (hereinafter referred to as memory), a memory protection circuit is usually used to prevent data stored in the memory from being destroyed or stolen by other log systems. (hereinafter referred to as a memory/fvx protect circuit) is provided, and the memory area in which the above-mentioned data is stored is designed not to accept access signals unless permission is specifically granted.

Therefore, there is a conventional data processing apparatus as shown in FIG. 1 which is equipped with the above-mentioned message/grotect circuit. To explain the device with the following, J is for writing data,
CPU that performs calculation control from reading K, 1 is CPU
Written by J.

This is memory for reading. (Other stones have multiple memori, and the explanation here is exemplified by megori 1.) And C
Between the PTj J and the memory 1, there is an address bus 3° data/4 bus for exchanging data signals between the two. A write signal line 5 is interposed.

However, the address bus 1 is divided into two directions; one side is connected to the select terminal cB of the memory 1 through a decoder, and the other side is directly connected to the address input terminal D of the memory 2. Further, the data bus 4 is connected to the input terminal of the memory 1.Furthermore, the write signal line 5 is connected to one input terminal of the circuit r, and the write signal line 5 is connected to the input terminal of the memory xO through the circuit 1 of this circuit. Connected to end WR. A fixed DC voltage is applied to the other input end of the paulownia circuit 1 via a resistor 1, and at the same time, a protect switch 9 for instructing the protect function is connected between this input end and the ground.

As described above, with the above configuration, a memory protect function is added when data is written from CPU J to memory 1. This will be explained using the signal tie chart shown in FIG.

First of all, when you do not want to operate the Meminesu-fa Tect function, please use the above! Lotecto Sui, Chi9 becomes open and hazy. Therefore, the CPU
When a write operation is performed from J to memory 1 at the timing tl in FIG. 2, the address signal (&) and data signal +b) shown in the figure are output from CPU J. Then, the address signal is input to the address input terminal ADo of the memory 2 via the 7 address '4 bus 3, and at the same time, the address signal is input to the decoder 6.
This decoder 6 inputs the address signal to the second
Figure (c) 1. The subsequent rising signals are decoded and input to the chip select terminal C8o of the memory 1.

At this time, the memory 2 is instructed to write at the timing of the 0th order tl when the memory area is designated and becomes writable. As shown in FIG.
The signal is input to one input end of the D circuit 2 via the write signal line 5. Therefore, the other input terminal of this AND circuit 10 has the DC voltage E applied in advance.

is input to. The memory 1 is inputted from the data bus 4 according to the write signal inputted by B (see Fig. 2).
Start writing data to the memory next! When operating the protection function, the protection switch 9 is closed. Therefore, the DC voltage E of the circuit 1 is
The input terminal to which K is applied is always grounded. That is, the AND circuit 1 is always in a closed state 11
In 6th, even if the pulse signal commanding the write from CPU J is input to the other input terminal of 4, the same circuit r does not output anything to the write signal input terminal of memory 2. Therefore, memory 1 is Memory preservation is performed in such a way that the data sent from s is not written.

Problems with the Background Art However, although the above-mentioned conventional device performs a sufficient protection function in program checks/four-steps such as modifying program modules, it cannot be used when multiple program modules are monopolized and operate in parallel with each other. %9 and 1 are under development
It is extremely difficult to prevent a situation where a program is accidentally written to a normally running program or a data area that is updated every time a program is executed, and this can cause the program to run out of control. .

OBJECTS OF THE INVENTION The present invention provides a data processing device that can prevent erroneous writing and reading of program and data areas in memory even when a plurality of log systems are executed in parallel. The purpose is to

Summary of the Invention In order to achieve the above-mentioned object, the present invention provides an apparatus for processing data by transmitting and receiving data between a CPU and a memory.
The CPU decodes only the address signal from a specific log 2 among the address signals output from the CPU during instruction 7 of the instruction cycle in which the CPU performs writing and reading, and executes the instruction until the execution cycle of the instruction cycle. A means for holding the K CPU during the execution cycle is provided.
This data processing device prevents erroneous writing and reading from an unspecified Ofrodatum by providing means for inputting the held decoded signal into the memory by the write/read ON/OFF signal outputted from the data processor.

11 Embodiments of the Invention Figure 3 shows a configuration diagram of an embodiment of the present invention.The explanation will be given at the time of write operation.20CompaniesA CPU that performs arithmetic processing by writing and reading, 2J is a CPIJ J O
It is a memory in which data is written and read by K. Dom data signal end DA
It is provided with a Hm command 7, a signal output terminal OF, and a write command signal input terminal R1. Further, the memory 11 is provided with at least a Chizzo select signal C8, an e-address signal terminal DI, and a data signal DAl# write command signal input terminal WR. Furthermore, the address signal terminal D1 of the CPUjgt
Address switch 21, data signal end DAsK company data t+xxx.

The instruction fetch signal line 2 is connected to the instruction fetch signal output terminal 6F.
4. The write command signal output terminal WRI receives the write command signal @
xi are connected to each other. The address bus 22 is divided into three directions, one to a first decoder 26 for decoding the address signal, and one to a specific!
The remaining decoder 27 is connected to the address signal terminal A D m of the memory 2J, and the second decoder 27 is set with the address signal from the program.

The output terminal of the first terminal 2# is connected to the select terminal CBmK of the memory 21, and the output terminal of the second terminal 22 is connected to the select terminal CBmK of the memory 21.
The output side of is a flip-flora f circuit 2 which has both output terminals, a positive logic output terminal Q and a negative logic output terminal Q, provided for signal holding.
8 (hereinafter referred to as the FF circuit) is connected to one input terminal DK. In addition, the data bus 2sFi memory 2JC) is connected to the other input terminal CPK, and the write command signal line 15
The output terminal is the memory yxio write command signal terminal WRsK1i
I! It is connected to one input terminal of a two-manufactured AND circuit 1# connected to the input terminal. The other input terminal of this two-person type AND circuit 1# is connected to the positive logic output terminal Q of the F.r circuit 2I. Furthermore, the negative logic output terminal Q1 of the F.F.1gl circuit 11 is connected to the first decoder terminal. The output end of 2C and the write command signal fli2g are connected to each input end of a three-manual AND circuit 30, respectively.

Next, the operation of the apparatus constructed as described above will be explained using the signal tie chart shown in FIG. For the sake of simplicity, the signals handled by the CPU JO's address signal terminal D1, data signal terminal DA1e command terminal, CH signal output terminal OF, and write command signal output terminal WR will be briefly described as follows. The address signal terminal D1 is a signal for specifying an address, the data signal terminal DΔ1 is a signal for data to be written/read, and the instruction fetch signal output terminal 0FtiCPUJO is a memory 2! The write command signal output terminal WR handles a pulse signal indicating that a command is being retrieved from the memory, and a pulse signal instructing execution of writing, respectively.

Note that the instruction fetch signal may be a status signal for CPU K, but it can be easily converted into a pulse signal such as a bladder evacuation signal. When θ performs a write operation, it has an instruction cycle of time T shown in FIG. 4, and this instruction cycle is composed of an instruction fetch cycle T1 and an execution cycle T3. However, time TI
Memory 2 in which instructions in memory 21 are stored
A signal specifying address 1 and a signal specifying the memory address of memory 2J to which writing is to be performed at time T1 are output from the CPU J o (D address signal terminal AD, as shown in FIG. 4(a)). Further, at the time TI, the instruction signal output terminal 6F outputs the signal shown in FIG. 4(b).Then, the address signal output at time T! xtttK f: I-coded memory 2 select terminal C
Input to 8K. Here, the memory area corresponding to the address signal in the memory 21 is selected and a writable state I is created.
becomes. At the same time, the address signal at time T is also input to the second circuit 28, but if the address signal at time T is a signal from a specific program, it is decoded by the same decoder 22. input to the next page. and,
The decoded signal is held at the output terminal Q of the F/F circuit 28 at the timing when the pulse of the instruction fetch signal at the time T1 is input to the input terminal CP of the F-)' circuit 280. At this time, the signal at the output terminal Q of the same circuit 28 becomes as shown in FIG. Further, a /4 pulse signal shown in FIG. 4(d) is output from the write command signal output terminal WR1. This /parallel signal is a 2-person type AND circuit 2
It is input to one input end of 9. The other input terminal here is the time T1 held by the F@F circuit j8.
Since the data conversion signal of the address signal is inputted, the r-gate of AND circuit 2# is open. This AND
The output of the circuit 29 is shown in FIG. At the same time, the negative logic output terminal QO of the F-F circuit 28 is written to the three-man power forming circuit Jo.
The R force, write command signal, and tsl decometer JgO output are input, respectively. Here, if the address signal input to the second decoder 27 is a signal from a specific program that is allowed to be written, the output of the negative logic output terminals of the F-F circuit 28 will be 10'', so the three-man power Type AN
If the output signal of D circuit 10 is "0", conversely, if the address signal is a signal from a non-specific log 2m, the same AND circuit J0
The output is "l", and this output signal "1m" becomes a detection signal that notifies a write operation from a program other than the specific program. Figure 4(f) shows the output of the AND circuit SO.
Note that the solid line in FIG. 4(e) (@) (f) indicates the positive logic output terminal Q, 2 of the F@F circuit 28 when writing is performed from a specific program, and the dotted line indicates the positive logic output terminal Q, 2 of the F@F circuit 28 when writing is performed from a program other than the specific program. Human-powered AND circuit 29.3 Human-powered AND
The outputs of circuit 10 are shown respectively.

That is, the write command signal is controlled based on the address signal in the instruction fetch cycle input to the second debugger 21, so that writing is performed only from a specific permitted program.

As described above, in the embodiment of the above-mentioned structure, when performing memory protection, it can be constructed with common third circuits such as a decoder, an r.2 circuit, and an AND circuit, which is advantageous in terms of cost. The output of the above three AND circuit 30 is the CPU
If used as an interrupt signal or the like, it is possible to detect and process in advance that an abnormal program write is about to be performed.

In addition, the above embodiment is explained at the time of write operation.
Even during the continuous output operation, stealing can be prevented in the same way as described above by replacing the write command signal with the read command signal.

Effects of the Invention According to the present invention, when a plurality of programs coexist and are performing operations in parallel with each other, it is possible to automatically prevent eavesdropping during erroneous writing to memory by a program under development. You can. Therefore, it is possible to prevent the program from running out of control. Signals for detecting erroneous write and read operations from sources other than the specific program can also be easily extracted. That is, it is possible to clearly distinguish between the program area and the data area, and to provide a data processing device that has a more complete memory protection function and can be operated efficiently.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional data processing device, and Figure 2 is a diagram of a conventional data processing device.
FIG. 3 is a block diagram of an embodiment of the data processing device according to the present invention, and FIG. 4 is a signal time chart of the main phone having the configuration shown in FIG. 3. 20...CPU, jJ...Memory, J4-...Command signal line, 25...Write command signal line, 11...
...Second decoder, 2#...F@F circuit, 29...
・2-person-powered AND circuit, 30...3-person-powered AND circuit. Figure 1 t1t2 Figure 3 Figure 4

Claims (1)

[Scope of Claims] A CPU' that writes and reads data in an instruction cycle consisting of an instruction fetch cycle and an execution cycle, and outputs an address signal in each tickle;
The data is written and the output is performed according to the address signal outputted from this CPU, and the command signal is outputted from the CPU. Means for decoding and holding only a predetermined address signal that is output during a cycle, and nine decodes held by this means? 9 data processor: IIT device;