JPH04257957A - Error processing system in bus switching control - Google Patents

Abstract

PURPOSE:To prevent access from a bus master to a slave generating error concerning the error processing system in bus switching control to control the switching of plural bus masters and plural slaves at plural buses based on access information. CONSTITUTION:Bus switching circuits 2a and 2b are provided to output the access information, which is outputted from bus masters 1a and 1b, to the buses to slaves 4a and 4b as access objects, and bus selecting circuits 3a and 3b are provided to connect the buses outputting the access information to the slaves 4a and 4b as the access objects, to execute error processings by transmitting error signals to the connected bus masters 1a and 1b when error is generated at the slave, and to prevent the access from the other bus master to the slave by transmitting a stop signal to the other bus master.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error handling method in bus switching control for switching between a plurality of bus masters and a plurality of slaves on a plurality of buses based on access information.

0002

[Prior Art] In a system in which multiple bus masters (representing processors, input/output devices, etc.) mutually share multiple slaves (referring to memory, etc.), a single bus is normally used to connect the bus masters and slaves. A method is used in which data is transferred between a specific bus master and a specific slave by using this bus in a time-sharing manner. However, this system has the disadvantage that when there are many bus masters, the waiting time of bus masters other than the connected bus masters increases, resulting in a decrease in data transfer efficiency.

[0003] Therefore, a method has been proposed in which a bus master and a slave are connected by multiple buses to transfer data (
Patent application No. 2-256350). FIG. 5 is a block diagram illustrating such a bus switching control method. In the figure, two bus masters 1a, 1b connect two slaves 4a, 4b.
The following is an example of a system that shares the following information. 2a and 2b are bus switching circuits provided corresponding to the bus masters 1a and 1b, respectively;
Based on the access information output from a and 1b, a bus master is connected to the bus to the slave to be accessed, and the access information is output. 3a and 3b are slaves 4a and 4b
If the corresponding slave is not being accessed, a bus selection circuit provided corresponding to each of the buses connects the bus that outputs the access information to the slave.

In FIG. 5, for example, when the bus master 1a accesses the slave 4b, the bus master 1a
Access information (slave 4
b address, etc.) is output. The bus switching circuit 2a is
Decode the address and connect to bus 12 to slave 4b. When the bus selection circuit 3b receives this access information via the bus 12, it connects to the slave 4b if the slave 4b is not accessed by another bus master 1b.

In this way, the bus master 1a can access the slave 4b, but during this access, for example, if the bus master 1b accesses the slave 4a, the bus master 1b and slave 4a are connected via the bus 14. Ru. Therefore, bus master 1a and bus master 1b can perform data transfer simultaneously.

[0006] Even in a system composed of two or more bus masters and slaves, each bus master can transfer data simultaneously, as in the above example, and the efficiency of data transfer can be improved.

[0007]

[Problem to be Solved by the Invention] However, in the conventional method as described above, connection is made to one of the slaves based on access information output from the bus master, and the connection is controlled based on information from the slave side. I can't. Therefore, if an error occurs in a slave connected to a specific bus master, this cannot be notified to other bus masters, and as a result, a situation arises in which another bus master accesses the slave that has caused the error.

[0008] When errors occur twice as described above, it becomes difficult to recover from them, resulting in a problem that, for example, the system must be reset once and the entire system operation must be temporarily stopped.

Accordingly, it is an object of the present invention to prevent access to a slave in which an error has occurred.

0010

[Means for Solving the Problem] The above problem is solved by providing bus switching circuits 2a, 2b provided corresponding to a plurality of bus masters 1a, 1b, respectively, and a plurality of slaves 4a, 4b.
Bus selection circuits 3a and 3b provided correspondingly to
and a plurality of buses 11 to 18 respectively connected between the bus switching circuit and the bus selection circuit, and the bus switching circuit selects the bus to the slave to be accessed based on the access information output from the bus master. The above access information is output, and the above bus selection circuit connects the bus that outputs the above access information to the slave to be accessed, and when an error occurs in the above slave, it sends an error signal to the connected bus master to handle the error. This is achieved by an error processing method in bus switching control characterized in that the slave is prevented from accessing the slave by other bus masters by causing the bus master to perform the operation and sending a stop signal to the other bus master.

[0011]

[Operation] FIG. 1 is a diagram explaining the principle of the present invention, 1a, 1b
is the bus master, 2a, 2b are the bus switching circuits, 3a, 3b
1 is a bus selection circuit, 4a and 4b are slaves, and 11 to 18 are buses. In the figure, when no error occurs in the slaves 4a and 4b, the bus 1
Bus master 1a, 1b and slave 4a by 1 to 14
, 4b are interconnected to perform data transfer. For example, bus master 1a connects slave 4 via bus 12.
If an error occurs in the slave 4b while accessing the slave 4b, the bus selection circuit 3b provided corresponding to the slave 4b sends an error signal to the bus master 1a via the bus 15 to cause the bus master 1a to perform error handling. Since the stop signal is sent to the other bus masters 1b via the bus 17, the other bus masters 1b can know that the slave 4b has caused an error and can stop the access.

[0012] Therefore, since a double error in which another bus master accesses the slave in which the error has occurred is prevented, the system can be recovered immediately after the error processing of the slave 4b is performed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, and is the same as the diagram for explaining the principle of the present invention. FIG. 2 shows an example of the bus switching circuit 2a (2b has the same configuration) in FIG. 1, in which 21 is an address decoder, 22,
23 is a gate. In the figure, an address decoder 21 decodes the address output from the bus master 1a and opens a gate 22 or a gate 23 in accordance with the address space allocated to the slaves 4a and 4b. Therefore, for example, when the bus master 1a accesses the slave 4b, the gate 23 is opened and the access information is output onto the bus 12. Similarly, when the slave 4a is accessed, access information is output onto the bus 11.

FIG. 3 shows an example of the bus selection circuit 3b (3a has the same configuration) in FIG. 1, in which 31 and 32 are FFs (flip-flops), 33 and 34 are gates,
41 is an AND gate, and 42 is a NOT circuit. The bus selection circuit 3b selects the buses 12 and 13 from the bus masters 1a and 1b using gates 33 and 34, and selects the buses 12 and 13 from the bus masters 1a and 1b to
b.

When the bus master 1a accesses the slave 4b, the access request signal REQa becomes "1" on the bus 12 in FIG. When slave 4b is not accessed by another bus master, the REQ signal on slave 4b is "0", so the AND
Gate 35 opens and FF 31 is set, which opens gate 33 and connects bus 12 and slave 4b. At this time, the access request signal REQ is sent to the other bus 13.
Even if b appears, the gate 34 remains closed and REQ
The bus master 1b that outputs the signal b goes on standby.

Similarly, bus master 1b connects slave 4
If the bus master 1b accesses the slave 4a and the slave 4a is not accessing the bus master 1b, the bus master 1b is connected to the slave 4a. Note that the FFs 31 and 32 are reset when the output of the bus request signal REQ stops.

Furthermore, the gate 39 shown in FIG. 3 determines the priority order when the bus masters 1a and 1b access the same slave 4b at the same time, and in the example of FIG.
EQa is set to have a higher priority than REQb.

Next, the case where an error occurs in the slave 4b while the bus master 1a is accessing the slave 4b will be described below with reference to the timing diagrams shown in FIGS. 1 to 3 and 4.

First, as shown in FIG.
When the access information of a becomes "1" at an earlier time or at the same time as the access information of the bus master 1b, the bus master 1a is connected to the slave 4b and the bus master 1b is placed on standby, as described above. When an error occurs in the slave 4b, the error signal output from the slave 4b becomes "1" and is sent to the AND gates 36, 37, 40, and 41 as shown in FIG.

[0020]Currently, the bus master 1a is accessing the slave 4b, so the FF31 is in the set state, and the FF32 is in the set state.
is in a reset state. Therefore, when an error occurs in the slave 4b, the output of the AND gate 36 becomes "1" and is output to the bus 15 to notify the bus master 1a of the error. In bus master 1a, slave 4b
It is possible to know that an error has occurred and perform error handling. Also, at this time, the output of the AND gate 41 is “
1" and is output to the bus 17 and sent to the bus master 1b. The bus master 1b knows that the slave 4b has caused an error and sets the access information to "0" to stop accessing the slave 4b.

As described above, the output of the AND gate 36 is used as an error signal to the bus master 1a, and
The output of ND gate 41 is used as a stop signal for access to bus master 1b.

After that, the error is repaired and the slave 4b
When the error signal becomes "0", the output of the AND gate 36 becomes "0", and the bus master 1a knows that the error has been corrected. On the other hand, the output of AND gate 41 is also “0”
Therefore, the bus master 1b can know that the error has been repaired.

Similarly, bus master 1b connects slave 4
If an error occurs in the slave 4b while accessing ``b'', the output of the AND gate 40 is sent to the bus master 1b to notify the error, and the output of the AND gate 37 is sent to the bus master 1a, and the output from the bus master 1a is sent to the slave 4b. Prevent access to.

In this embodiment, a system having two bus masters and two slaves has been described, but a system having three or more bus masters can be similarly prevented from accessing a slave in which an error has occurred from the bus master. Can be done.

[0025]

As described above, according to the present invention, since no other bus master accesses a slave in which an error has occurred, errors do not occur twice, and therefore, after the error is repaired, the system The functionality of the system will be restored immediately, which is beneficial for improving the reliability of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the present invention;

[Fig. 2] A block diagram showing the configuration of a bus switching circuit.

FIG. 3 is a block diagram showing the configuration of a bus selection circuit;

FIG. 4 is a timing diagram showing an embodiment of the present invention;

FIG. 5 is a block diagram illustrating a bus switching control method according to a conventional example;

[Explanation of symbols]

1a, 1b bus master,
21 Address decoder, 2a, 2b bus switching circuit,
22, 23, 33, 34 gate, 3a, 3b bus selection circuit,
31, 32 FF, 4a, 4b slave,
35-41 AND gate,

Claims (1)

[Claims] [Claim 1] Bus switching circuits (2a, 2b) provided corresponding to a plurality of bus masters (1a, 1b), respectively.
, bus selection circuits (3a, 3b) provided corresponding to the plurality of slaves (4a, 4b), and a plurality of buses (11 to 18) respectively connected between the bus switching circuit and the bus selection circuit. ), the bus switching circuit outputs the access information to the bus to the slave to be accessed based on the access information output from the bus master,
The bus selection circuit connects the bus that outputs the access information to the slave to be accessed, and when an error occurs in the slave, it sends an error signal to the connected bus master to perform error processing, and the other bus masters An error handling method in bus switching control characterized in that a stop signal is sent to the slave to prevent other bus masters from accessing the slave.