JPS63163949A - Multi processor system - Google Patents

Abstract

PURPOSE:To ensure a communication between processors by inputting the logical sum of acknowledge signals from a slave processor, to a host processor, at the time of the communication to all the slave processors. CONSTITUTION:A signal, the inverse of Tor, i.e., the logical sum of the acknowledge signals generated by respective slave processors S1-S4 for a strobing signal, the inverse of AS from the host processor H, and the signal Tand, i.e., the logical product of these acknowledge signals are supplied to the host processor H. Then, at the time of the communication between the host processor H and one number of the slave processor, the signal, the inverse of Tor is inputted to the host processor H, and at the time of the communication to all the slave processors S1-S4, the signal Tand is inputted to the host processor H. Accordingly, because it means that at the time of the communication to all the slave processors S1-S4, the most delayed acknowledge signal among the acknowledge signals from the respective slave processors S1-S4 is inputted, the communication between the processors can be surely performed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a multi-purpose computer for realizing high-speed calculations such as determinant calculation, sorting, maximum or minimum value calculation, graphic processing, image processing, etc. This is related to processor systems.

[Prior Art] As a conventional system for executing this type of high-speed calculation, for example, "IEICE Research Report (EC85-3
2) , Realization of BC processor array, October 1985
One example is the processor array announced at Obata, Miyagaki, and Kanen on May 24th. This processor array has a configuration in which one host processor and 256 slave processors are bus-coupled.Handshaking between the host processor and slave processors is based on a strobe signal and an acknowledge signal, but the acknowledge signal to the host processor is sent to each slave processor. The logical sum of the seven logic signals was formed using a wired OR using an open collector.

[Problems to be solved by the invention] FIG. 5 shows that in a conventional multiprocessor system,
7 is a timing chart illustrating a problem when an acknowledge signal to a host processor is formed by a wired OR of acknowledge signals of each slave processor.

In the figure, (As> is the strobe signal from the host processor, and (100), (b), and (te) are the acknowledge signals of each slave processor (in addition, one symbol in the figure means negative logic). ).

When detecting the fall of the strobe signal (AS) from the host processor, each slave processor sends back an acknowledge signal, but other acknowledge signals (a) such as acknowledge signal (6).

The signal delayed from (b) is the logical sum of the acknowledge signals (a>, (6>, (stone)), so the acknowledge signal of the host processor is the logical sum of the acknowledge signals (a>, (6>, (stone)).
Among (b) and (te), the earliest acknowledge signal (δ
) has priority, so the acknowledge signal (C) is delayed after the strobe signal becomes “H” (high level).
There is a possibility that it will become H11.

In other words, there is no problem when handshaking with one slave processor, but when handshaking with multiple slave processors at the same time, if the acknowledge signals of each slave processor vary due to signal delays, each acknowledge Shin @ (a), (6), (c)
Problems occur due to timing disturbances. Needless to say, in such a case, data will be transferred incorrectly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a multiprocessor system that easily and reliably communicates with a plurality of slave processors.

[Means for Solving the L Problem] The multiprocessor system according to the present invention is a system composed of a host processor and a large number of slave processors, and the multiprocessor system according to the present invention is configured to perform a logical sum and an acknowledge signal of each slave processor in response to a strobe signal from the host processor. a circuit that generates a logical product, a circuit that selects the logical sum acknowledge signal when communicating between one slave processor and the host processor, and a circuit that selects the logical product acknowledge signal when communicating between all the slave processors and the host processor. It has the following.

[Operation] In the present invention, when the host processor issues a strobe signal to a specific slave processor, the OR acknowledge signal is selected by the host processor, so the acknowledge signal of the slave processor is inputted as is to the host processor. . Then, when the strobe signal is issued to all slave processors, the AND acknowledge signal is selected, so the most delayed acknowledge signal is input to the host processor.

Embodiment FIG. 1 is an overall configuration diagram of a multiprocessor system according to an embodiment of the present invention.

In the figure, (H) is the host processor, (Sl), (
32>, (33), and (34) are slave processors, and these host processor (H) and slave processors (31), (32>, (S3), and (34) constitute a multiprocessor system.

The strobe signal (AS) of the host processor (H>) is transmitted to each slave processor (31), (32>).

(33), enters (S4) and each slave processor <3
1), (32>, (S3), and (S4)).
nd) is connected as an open collector output and input to the host processor (H).

FIG. 2 is a generation circuit diagram of the logical sum acknowledge signal (TOr>) and the logical product acknowledge signal (Tand) used in the multiprocessor system according to the embodiment of the present invention.

In the figure, a slave processor (31).

(32>, (33), (34), respectively, the logical sum acknowledge signal @(TOr>) and the logical product acknowledge signal (
Tand> generation circuit, in which the acknowledge signal (1) is an open collector output is the OR acknowledge signal (T.

r), the acknowledge signal (1) is inverted by an inverter circuit, and the open collector output is the AND acknowledge signal (Tand>).

FIG. 3 is a diagram of an acknowledge signal selection circuit provided in a host processor (H) used in a multiprocessor system according to an embodiment of the present invention.

In the figure, the acknowledge signal selection circuit provided in the host processor (H) is connected to all slave processors (31
), (32), (33), and (S4), the signal (BC) is activated, so the signal (Tand) is selected; otherwise, the OR acknowledge signal (
TOr) is selected and becomes an acknowledge signal for the host processor (H).

In the multiprocessor system of one embodiment of the present invention configured in this manner, a host processor (H) and a plurality of slave processors (Sl), (32>, (33)
), (34), each slave processor (31), (32>,
(33).

(S4) A circuit that generates a logical sum of the acknowledge signals (1) as an open collector output to obtain a logical sum acknowledge signal (TOr), and each slave processor (31) in response to a strobe signal from the host processor (H). .

(S2>, (33), (34)) A circuit that inverts the acknowledge signal (1) that generates the logical product of the acknowledge signals (34) using an inverter circuit and obtains the logical product acknowledge signal (Tand> that is output from the open collector), and a slave processor. (81).

(32>, (33), (34)), a circuit that selects the logical OR signal as an acknowledge signal to the host processor, and a circuit that selects the logical sum signal as an acknowledge signal to the host processor when communicating with one of (32>, (33), (34));
1), (32>, (S3).

(S4) includes a circuit for selecting the AND signal as an acknowledge signal to the host processor.

Therefore, all slave processors (31).

When communicating with (32>, (33), and (34), the AND acknowledge signal (Tand) is selected as the acknowledge signal, so each slave processor (
31), (32>, (33).

(S4) acknowledge signals (a), (b).

Even if there are variations in (C), the AND acknowledge signal (a) is synchronized with the slowest acknowledge signal (C).
Since the signals b) and (C) become the acknowledge signal,
The problem described in FIG. 5 as in the conventional case does not occur.

Also, a slave processor (Sl), (32>).

When communicating with one of (33) and (S4), the logical sum (TOr>) is selected as the acknowledge signal, but the acknowledge signal of the corresponding slave processor becomes the acknowledge signal to the host processor as it is, and no problem occurs.

Since the OR acknowledge signal and the AND acknowledge signal are obtained as open collector outputs, a system can be constructed with a simple configuration and at low cost. [Effects of the Invention] As explained above, the multiprocessor system of the present invention includes a circuit that generates the logical sum and logical product of the acknowledge signals of each slave processor in response to the strobe signal from the host processor, and one slave processor. The apparatus includes a circuit that selects the logical sum signal as an acknowledge signal to the host processor during communication, and a circuit that selects the logical product signal as an acknowledge signal to the host processor for communication with all slave processors. Yes, each slave processor generates an OR acknowledge signal and an AND acknowledge signal in response to a strobe signal from the host processor, and the acknowledge signal can be selected between when all slave processors are communicating and when not. Communication between the processor and slave processors can be ensured.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a generation circuit diagram of a logical sum acknowledge signal and a logical product acknowledge signal used in the multiprocessor system according to an embodiment of the present invention, and FIG. The figure is a diagram of an acknowledge signal selection circuit provided in a host processor used in a multiprocessor system according to an embodiment of the present invention, FIG. 4 is a timing chart of a multiprocessor system according to an embodiment of the present invention, and FIG. 5 is a conventional multiprocessor system. It is a timing chart explaining a malfunction of the system. In the figure, H: host processor, 31.32, 33.34 Nislepe processor. In addition, in the figures, the same reference numerals and the same symbols indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a multiprocessor system consisting of a host processor and multiple slave processors, a circuit that generates an OR of the acknowledge signal of each slave processor in response to a strobe signal from the host processor, and a circuit for each slave processor in response to a strobe signal from the host processor. A circuit that generates a logical product of acknowledge signals of the processor, a circuit that selects the logical sum signal as an acknowledge signal to the host processor when communicating with one slave processor, and a circuit that generates a logical product of the logical sum signals for communication with all slave processors. A multiprocessor system comprising: a circuit for selecting a signal as an acknowledge signal to a host processor; (2) The multiprocessor system according to claim 1, wherein the OR signal and the AND signal are configured by negative logic and positive logic open collector connections, respectively.