JPH0433152A - Bus system - Google Patents

Abstract

PURPOSE:To make transfer efficient by providing a burst transfer signal line showing that a bus is used for burst transfer and executing transfer through the use of only an address bus. CONSTITUTION:If a device 1 asserts a request signal to a bus arbiter 9 through a control bus 10 when devices 3 and 4 execute transfer, the arbiter 9 outputs an acknowledge signal to the device 1 through the bus 10. The device 1 outputs the address and data to the address bus 6 since the burst transfer signal line 7 is active and executes transfer. The devices 1 and 2 use only the bus 6 and the devices 3 and 4 use only a data bus 5 in the middle of transfer so as to simultaneously execute two transfer. Thus, data can efficiently be transferred.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus system for performing data transfer between electronic devices.

[Conventional technology]

A block diagram of a conventional bus system is shown in FIG. In the figure, (1) to (4) are devices connected to the bus and transfer data, (5) is a data bus from which devices (1) to (4) output data, and (6) is device (1). ~
(4) is an address bus that outputs addresses, (9) is a panuarbiter that determines whether to permit use of the bus to devices (1) to (4) that request transfer, and (10) is a device ( 1) to (4) are a control bus which is a group of various control signal lines used for transfer. Note that the devices (1) to (4) have built-in means for executing burst transfer in which a plurality of data are successively transferred by outputting one address to the address bus (6).

Next, the operation will be explained. First, consider the case where device (1) transfers data to device (2).

First, the operation when the transfer is not a burst transfer will be explained. The device (1) asserts a request signal to the bus arbiter (9) through the control bus (10) in order to obtain the right to perform the transfer. When permitting the transfer, the bus arbiter (9) outputs an acknowledge signal to the device (1) through the control bus (10). Device (1), which has obtained the right to perform the transfer, sends the address to device (2) on the address bus (6) and the data bus (5).
Output the data to be transferred to. At this time, the device (1
) and the device (2) exchange signals for controlling transfer timing via a control bus (10).

During the transfer, the bus is in use, so other devices cannot perform the transfer.

Next, the operation when the transfer is burst transfer will be explained. The device (1) asserts seven request signals to the bus arbiter (9) through the control bus (10) in order to obtain the right to perform the transfer. If the arbiter (9) permits the transfer, it outputs an acknowledge signal to the device (1) through the control node (10). Having obtained the right to perform the transfer, the device (1) outputs an acknowledge signal to the device (2) through the control node (10). ), one address is output to the address bus (6). After that, multiple data are output continuously to the data bus (5). While multiple data are being transferred, the address bus (6) is output. ) No address is output to the device (1
) and the device (2) receive signals for controlling the timing of transfer via the control bus (10).

During the transfer, the bus is in use, so other devices (3)
, (4) cannot be transferred.

Since burst transfer continuously transfers a plurality of data at once, the bus is used for a long time, but during that time, other devices (3) and (4) cannot perform transfer.

[Problems to be Solved by the Invention] Since the conventional bus system is configured as described above, when the bus is used for burst transfer, even though the address bus is not used, other devices There is a problem in that the transfer cannot be performed and the transfer is not performed efficiently.

The present invention has been made to solve the above problems, and aims to provide a bus system as described below.

1) When a bus is used for burst transfer, transfer is performed using only address buses that are not used between other devices to improve transfer efficiency.

2) In the bus system described in item 1) above, when transfer is performed between certain devices using only the address bus, transfer efficiency can be further improved by performing transfer between other devices using only the data bus. raise.

[Means to solve the problem]

The bus system according to the present invention has the following features: 1) A burst transfer signal line connected between devices and indicating that the bus is used for burst transfer; This device is equipped with means for executing transfer using only an address bus so that transfer can be executed between other devices at the same time.

2) In the bus system of item 1) above, when transfer using only the address bus is performed by /<-nuto transfer, a means for transferring using only the data bus and a means connected between each device, It is equipped with a bus designation signal line that indicates whether the address bus or the data bus can be used when the bus is used for burst transfer.

[Function] The bus system according to the present invention has the following features: 1) When the bus is used for burst transfer, another device outputs an address to the address bus, and then outputs data to the address bus to perform the transfer. Therefore, two transfers are performed at the same time.

2) In addition to item 1) above, when a burst transfer is performed between certain devices using only the address bus, another device outputs an address to the data bus, and then outputs data to the data bus. Therefore, two transfers are performed at the same time.

[Example 1 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the Vanu system, which is an embodiment of the first aspect of the present invention. In the figure, (7)
This is a burst transfer signal line that uses a bus for burst transfer. Note that the other symbols are the same as those in the third conventional example, so their explanation will be omitted.As for UDPs (1) to (4), when the bart transfer signal line (7) is not active,
Transfer is performed by outputting an address to the address bus (6) and data to the data bus (5) in the same way as the conventional one, and when the burst transfer signal line (7) is active,
The address bus (6) has built-in means for realizing a function of outputting data to the address bus (6) and performing transfer after outputting K addresses. The path arbiter (9) has a function of activating the burst transfer signal line (7) when the VANU is used for burst transfer.

Next, the operation of the first embodiment shown in FIG. 1 will be explained. Consider the case where device (1) performs K transfer to device (2) The operation when performing transfer from a state in which low-pass is not used for burst transfer is the same as that of the conventional device described above. That is, the transfer is performed by outputting the address to the address bus (6) and the data to the data bus (5).

The operation when performing a transfer from a state where a path is used for burst transfer will be explained. Device (3) and Device (4)
) is performing burst transfer.

In order to obtain the right to perform the transfer, the device (1) asserts a request signal to the path arbiter (9) through the control path (10). The path arbiter (9) controls the control path (1) when the burst signal is active.
An acknowledge signal is output to device (1) through device (0). Device (1), which has obtained the right to perform the transfer, performs the transfer with device (2). Since the burst transfer signal line (7) of device (1) is active, device (1)
outputs an address to the address bus (6), and then outputs data to the address bus (6) for transfer. At this time, the device (1) and the device (2) exchange signals for controlling the transfer timing via the control bus (10). During this transfer, device (1) and device (2) use only address bus (6), and device (3) and device (4) use only data bus (5), resulting in two simultaneous transfers. ing.

FIG. 2 is a block diagram of a pass synutem according to a second embodiment of the present invention. In the figure, (8) is a bus designation signal line indicating which of address bus (6) and data bus (5) can be used. Note that the other symbols are the same as those in FIG. Devices (1) to (4) have the same functions as the first embodiment, and in addition, when the path designation signal line (8) is Iliigh, the address bus (6)
After 6 digits of address, a)” V 7. I<s(
6) to perform the transfer, and when the path designation signal line (8) is Low, output the address to the data bus (5), then output the data to the data bus (5) to perform the transfer. It has built-in means to implement the functions it performs. The bus arbiter (9) has the same functionality as the first embodiment, in addition, when the address bus (6) is available,
Set the bus designation signal line (8) to High and connect the data bus (5).
is available, the path designation signal line (8) is held low.
It also has a function of not asserting the acknowledge signal when neither the address bus (6) nor the data bus (5) can be used.

Next, the operation of the second embodiment will be explained. device(
Consider the case where 1) transfers to device (2).

The operation when performing transfer from a state where the path is not used for burst transfer is the same as that of the conventional method. That is, the transfer is performed by outputting the address to the address bus (6) and the data to the data bus (5).

The operation when performing a transfer from a state where a path is used for burst transfer will be explained. Device (3) and Device (4)
) is performing burst transfer.

The device (1) asserts a request signal to the bus arbiter (9) through the control bus (10) in order to obtain the right to perform the transfer. The bus arbiter (9) uses the bus designation signal line (8) if the address node (6) is available.
) is set High, and if the data bus (5) is available, the bus designation signal 4jM(s) is set Low, and an acknowledge signal is output to the device (1) through the control bus (10). If neither is available, no acknowledge signal is output. The device that has obtained the right to make the transfer (
1) performs transfer with device (2). Device (1)
Since the burst transfer signal line (7) is active, transfer is performed using only one bus, and the bus designated signal line (7) is active.
8) is High, outputs the address bus (611C), then outputs data to the address bus (6) for transfer, and then connects the bus designation signal line (8).

If it is W, the address is output to the data bus (5), and then the data is output to the data bus (5) for transfer. Device (1) and device (2) are connected to the control bus (10). exchange signals that control the timing of transfer. During this transfer, device (1) and device (2) use only the Fi address bus (6) or only the data bus (5), and device (3) and device (4) also use only the address bus (6). Alternatively, two transfers are performed simultaneously using only the data bus (5).

If a burst transfer using only the address bus (6) and a burst transfer using only the data bus (5) are performed at the same time, a burst transfer using only the data bus (5) is performed only using the address bus (6). When the address bus (6) is completed before the burst transfer using the address bus (6), only the burst transfer using only the address bus (6) is performed.

In this situation, when a transfer request is received from another device, the transfer can be performed using only the data bus (5).

〔Effect of the invention〕

As described above, according to the present invention, data can be transferred efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bus system according to a first embodiment of the present invention, FIG. 2 is a block diagram of a bus system according to a second embodiment of the present invention, and FIG. 3 is a block diagram of a bus system according to a conventional example. It is a block diagram. In the figure, (1) to (4) are devices, (5) is a data bus x, (6) is a U address bus, (7) is a burst transfer signal line, and (8) is a bus designation signal line. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1

Claims (2)

[Claims] (1) When connected to multiple devices and transferring data between these devices, the device transferring data outputs the address of the device to which the data is transferred, and the device transferring data connects to the address bus. ,
In a bus system having a data bus for outputting data to be transferred, and a means for executing burst transfer for successively transferring a plurality of data by outputting one address built in the device to the address bus, the device A burst transfer signal line that is connected between the device and indicates that the bus is being used for burst transfer, and a line that is built into the device and is connected when the bus is being used for burst transfer and that burst transfer is not being performed at the same time. A bus system comprising means for executing transfer using only an address bus so that transfer can be executed between other devices. (2) When the transfer using only the address bus is performed by burst transfer, the means for transferring using only the data bus and the address 2. The bus system according to claim 1, further comprising a bus designation signal line indicating which of the bus and data bus can be used.