CN115202612A

CN115202612A - Superconducting single-flux quantum clock domain crossing communication method and system based on asynchronous FIFO

Info

Publication number: CN115202612A
Application number: CN202210249404.9A
Authority: CN
Inventors: 刘建; 唐光明; 杨佳洪; 郑祥雨
Original assignee: Institute of Computing Technology of CAS
Current assignee: Institute of Computing Technology of CAS
Priority date: 2022-03-14
Filing date: 2022-03-14
Publication date: 2022-10-18

Abstract

The invention provides a superconducting single magnetic flux quantum clock domain crossing communication method and system based on asynchronous FIFO, comprising the following steps: initializing an FIFO, inputting a write signal to the FIFO by an external write circuit, generating a write address and a write mark by the FIFO according to the write signal, comparing the write address and the write mark with a read address and a read mark, waiting for the external read circuit to read data and generate a new read mark and a new read address if the read address and the write address are equal but the write mark and the read mark are opposite, and writing the data to be written into the FIFO according to the write address; otherwise, writing the data to be written into the FIFO according to the write address. The external reading circuit inputs a reading signal to the FIFO, generates a reading address and a reading mark, compares the reading address with the writing mark, and if the reading address is the same as the writing address and the reading mark is also the same as the writing mark, executes to wait for the external writing circuit to write data to generate a new writing address and a new writing mark, and returns the data to the external reading circuit according to the reading address, or returns the data to the external reading circuit according to the reading address.

Description

Superconducting single-flux quantum clock domain crossing communication method and system based on asynchronous FIFO

Technical Field

The invention relates to the field of superconducting single flux quantum (RSFQ) microprocessors in computer systems, in particular to cross-clock domain communication of superconducting single flux sub-processors.

Background

When asynchronous clock domain communication is carried out, because clock frequencies and phases of different clock domains are possibly different, problems such as data loss and unstable states are likely to occur when clock domain crossing communication is carried out. To solve these problems, a solution in the semiconductor field is to use asynchronous FIFOs, which operate by sequentially writing data into the asynchronous FIFOs by a circuit of a source clock domain and reading out data by a circuit of a destination clock domain, and the asynchronous FIFOs function to store data, determine whether the data is full or empty, and avoid data errors when an indeterminate state occurs.

The RSFQ circuit field does not currently have an asynchronous FIFO that can be used for cross-clock domain communication, and because of the difference between the semiconductor circuit and the RSFQ circuit, there are some problems after the asynchronous FIFO in the semiconductor circuit is directly implemented with the RSFQ circuit: firstly, when the number of registers is small, the circuits for generating addresses and converting into hamming codes for decoding consume too much resources, and secondly, in order to reduce the probability of metastable state, the semiconductor FIFO converts the addresses into hamming codes to ensure that only one address changes when generating the addresses each time so as to reduce the error probability, but because of the difference between the RSFQ and the semiconductor circuit, the design is not useful in the RSFQ circuit.

That is, because signals in the circuit change when the address changes, and the asynchronous FIFO needs to cross clock domains, the smaller the number of signals to be changed when communicating across clock domains, the better, the smaller the number of signals to be changed, and the easier the probability of generating an unstable state is reduced. In the semiconductor circuit, the level of two signal lines is inverted every time the address changes by using single hot coding, only one signal line is inverted by using the Hamming code, and the address range which can be represented by the Hamming code is larger for the same number of signal lines, so that the semiconductor adopts the Hamming code. Whereas the signal in the rsfq circuit is not a level signal but a pulse signal. 1 and 0 are represented by the presence or absence of a pulse between two clocks, with a pulse between the two clocks being 1 and the absence of a pulse being 0. Therefore, in the cross-clock domain communication, the rsfq circuit is required to have a small number of pulses, and the smaller the number of pulses, the less the error is, so that onehot coding with only one 1 is adopted. Therefore, the asynchronous FIFO in the semiconductor field cannot be directly applied to the RSFQ field.

An asynchronous FIFO that can be used in the context of RSFQ circuits is therefore needed to match the clock frequency and phase of the different clock domains.

Disclosure of Invention

The invention aims to solve the problem of clock domain crossing communication of an RSFQ circuit, and provides an asynchronous FIFO applicable to the RSFQ circuit.

Aiming at the defects of the prior art, the invention provides a superconducting single magnetic flux quantum clock domain crossing communication method based on asynchronous FIFO, which comprises the following steps:

step 1, initializing FIFO, inputting a write signal to the FIFO by an external write circuit, generating a write address and a write mark by the FIFO according to the write signal, comparing the write address and the write mark with a read address and a read mark, and executing step 2 if the read address and the write address are equal but the write mark and the read mark are opposite; otherwise, writing the data to be written into the FIFO according to the write address;

step 2, when the FIFO is fully written, after waiting for an external reading circuit to read data and generate a new reading mark and a new reading address, writing the data to be written into the FIFO according to the writing address;

step 3, the external reading circuit inputs reading signals to the FIFO, generates reading addresses and reading marks, compares the reading addresses and the reading marks with the writing addresses and the writing marks, if the reading addresses and the writing addresses are the same, and the reading marks and the writing marks are also the same, executes step 4, otherwise, reads data according to the reading addresses and returns to the external reading circuit;

and 4, when the FIFO is empty, after waiting for the data written by the external write circuit to generate a new write address and a new write mark, reading the data according to the read address and returning the data to the external read circuit.

2. The asynchronous FIFO-based superconducting single flux quantum cross-clock domain communication method of claim 1, wherein the FIFO comprises a register file, a read control circuit, a write control circuit;

the write control circuit consists of an address generator, an address register, a data register, a full judgment circuit and a clock gating circuit;

the address generator is composed of a plurality of D triggers, rtffl and a nondestructive reading unit, and is used for emptying all units in the address generator when a reset signal arrives, and inputting a pulse to the D trigger at the lowest bit, wherein the pulse shifts one bit upwards every time a clock comes from the external writing circuit, the outputs of all the D triggers form a group of addresses when the clock arrives, wherein only the output of the D trigger originally containing the pulse is 1, the rest outputs are 0, then the pulse arrives at the D trigger at the highest bit, then the clock comes, a pulse is output to the rtffl and the emptying end of the nondestructive reading unit, the nondestructive reading unit is emptied, then if the pulse arrives at the odd number of the rtffl, the rtffl outputs a pulse to the nondestructive reading unit, otherwise, the pulse cannot be output, when the pulse exists in the nondestructive reading unit, every clock comes, the nondestructive reading unit outputs a pulse, and the output of the address generator is the address output of all the D triggers and the address output mark of the nondestructive reading unit;

the address register is composed of a plurality of D triggers, the input is the address output by the address generator, and the stored address is output after the clock arrives;

the data register is composed of a plurality of D triggers, the input is multi-bit data given from the outside, and the multi-bit data can be output after the clock arrives;

the full judgment circuit consists of an address comparison circuit, a mark comparison circuit and a full mark generation circuit;

the address comparison circuit comprises a plurality of non-destructive read units and a multilayer fusion buffer, wherein the input of the non-destructive read units is a read address of the read control circuit, a clock is the write address of the write control circuit, and an emptying signal is a read clock transmitted by the control circuit; when the read-write addresses are equal, the read control circuit generates an address and then empties all the nondestructive read-out units in the address comparison circuit, then the read address is sent to all the nondestructive read-out units in the address comparison circuit, the write address generator sends the address to the clock circuits of all the nondestructive read-out units in the address comparison circuit after outputting a group of addresses, when the read-write addresses are equal, one nondestructive read-out unit in the address comparison circuit has both data and a clock, so that a pulse is output, and the pulse is output after the multilayer fusion buffer;

the mark comparison circuit consists of a non-destructive reading unit and an exclusive-or gate, wherein the input of the non-destructive reading unit is a reading address mark of the reading control circuit, the clock of the non-destructive reading unit is a writing clock, and the clearing circuit is a reading clock; the inputs of the exclusive-OR gate are respectively a write address mark and the output of the nondestructive reading unit, and the clock is a write clock; the read control circuit sends a read mark to the non-destructive reading unit of the mark comparison circuit after generating a read mark, then reads the non-destructive reading unit of the mark comparison circuit after a write clock arrives, and leads the clock of the exclusive-OR gate to arrive at the exclusive-OR gate after the inputs of the exclusive-OR gate all arrive by controlling delay, and when the inputs of the exclusive-OR gate are different, the read-write address marks are different, and output is generated;

the data input of the full mark generation circuit is the output of the mark comparison circuit, the clock is the output of the address comparison circuit, and the emptying circuit is the write clock; the write clock firstly reaches the D flip-flop of the full mark generation circuit to clear the D flip-flop, then the output of the mark comparison circuit reaches, then the output of the address comparison circuit reaches, and if the data and the clock reach in one write clock cycle, the output is generated;

the clock gating circuit consists of a plurality of D triggers and a nondestructive reading unit, the input of the nondestructive reading unit is a reset signal and a full mark signal passing through two stages of D triggers, the clock is a write clock directly input, an empty signal is a full mark signal, the nondestructive reading unit of the clock gating circuit directly controls the clock, when the nondestructive reading unit has data, the clock can act on the D triggers for storing the write signal after passing through the nondestructive reading unit, when the nondestructive reading unit has no data, the clock is shielded, and the write circuit stops working;

the read control circuit consists of an address generation circuit, an address register, a judgment circuit and a clock gating circuit;

the read control circuit has the same composition and working principle of an address generation circuit, an address register and a clock gating circuit as the address generation circuit, the address register and the clock gating circuit of the write control circuit;

the mark comparison circuit of the emptiness judging circuit is provided with one more NOT gate, the write address mark is firstly inverted once before entering the nondestructive reading unit, the NOT gate clock is a write clock, and other circuits of the emptiness judging circuit are the same as the fullness judging circuit of the write control circuit.

The asynchronous FIFO-based superconducting single flux quantum clock domain crossing communication method is characterized in that

The process of generating the write address and the write flag according to the write signal in the step 1 is specifically as follows: resetting the write mark and the write address according to the initialization signal, then increasing one write address every time the FIFO receives a write signal, and after increasing the specified times of the write address, negating the write mark and resetting the write address;

the process of generating the read address and the read flag in step 3 specifically includes: and resetting the read mark and the read address according to the initialization signal, wherein the read address is increased by one every time the FIFO receives a read signal, and the read mark is inverted and the read address is reset after the read address is increased by a specified number of times.

According to the superconducting single magnetic flux quantum cross-clock domain communication method based on the asynchronous FIFO, the write address and the read address both adopt single thermal coding.

The invention also provides a superconducting single magnetic flux sub-clock domain crossing communication system based on asynchronous FIFO, which comprises:

the write module is used for initializing the FIFO, an external write circuit inputs a write signal to the FIFO, the FIFO generates a write address and a write mark according to the write signal and compares the write address with a read address and the read mark, and if the read address is equal to the write address but the write mark is opposite to the read mark, the first wait module is called; otherwise, writing the data to be written into the FIFO according to the write address;

the first waiting module is used for waiting for the external reading circuit to read data and generate a new reading mark and a new reading address, and then writing the data to be written into the FIFO according to the writing address;

the reading module is used for inputting a reading signal to the FIFO by an external reading circuit, generating a reading address and a reading mark, comparing the reading address with the writing mark, calling the second waiting module if the reading address is the same as the writing address and the reading mark is the same as the writing mark, and otherwise, reading data according to the reading address and returning the data to the external reading circuit;

and the second waiting module is used for waiting for the external writing circuit to write data to generate a new writing address and a new writing mark, and then reading data according to the reading address and returning the data to the external reading circuit.

The superconducting single magnetic flux sub-clock domain crossing communication system based on the asynchronous FIFO comprises a register file, a read control circuit and a write control circuit;

the data register is composed of a plurality of D triggers, the input is multi-bit data given from the outside, and the multi-bit data can be output after the clock comes;

the mark comparison circuit consists of a non-destructive reading unit and an exclusive-or gate, wherein the input of the non-destructive reading unit is a reading address mark of the reading control circuit, the clock of the non-destructive reading unit is a writing clock, and the clearing circuit is a reading clock; the inputs of the exclusive-OR gate are respectively a write address mark and the output of the nondestructive reading unit, and the clock is a write clock; the read control circuit sends a read mark to the nondestructive read unit of the mark comparison circuit after generating a read mark, then reads the nondestructive read unit of the mark comparison circuit after a write clock arrives, and leads the clock of the exclusive-OR gate to arrive at the exclusive-OR gate after the input of the exclusive-OR gate arrives by controlling delay, and when the input of the exclusive-OR gate is different, the read-write address mark is different, output is generated;

the data input of the full mark generation circuit is the output of the mark comparison circuit, the clock is the output of the address comparison circuit, and the emptying circuit is the write clock; the write clock firstly reaches the D flip-flop of the full mark generation circuit to clear the D flip-flop for one time, then the output of the mark comparison circuit reaches, then the output of the address comparison circuit reaches, and if the data and the clock reach in one write clock cycle, the output is generated;

the clock gating circuit comprises a plurality of D triggers and a nondestructive reading unit, the input of the nondestructive reading unit is a reset signal and a full mark signal passing through the two-stage D triggers, the clock is a write clock directly input, the clear signal is a full mark signal, the nondestructive reading unit of the clock gating circuit directly controls the clock, when the nondestructive reading unit has data, the clock can act on the D triggers for storing the write signal after passing through the nondestructive reading unit, when the nondestructive reading unit has no data, the clock is shielded, and the write circuit stops working;

The asynchronous FIFO-based superconducting single-magnetic flux sub-clock domain crossing communication system is characterized in that

The write module is configured to generate a write address and a write flag according to the write signal, and specifically: resetting the write mark and the write address according to the initialization signal, then increasing one write address every time the FIFO receives a write signal, and after increasing the specified times of the write address, negating the write mark and resetting the write address;

the reading module is used for generating a reading address and a reading mark, and specifically comprises the following steps: and resetting the reading mark and the reading address according to the initialization signal, then increasing the reading address by one every time the FIFO receives a reading signal, and after increasing the reading address by a specified number of times, negating the reading mark and resetting the reading address.

The superconducting single-flux-sub cross-clock-domain communication system based on the asynchronous FIFO adopts the one-hot coding for the write address and the read address.

The invention also provides a storage medium for storing a program for executing any one of the asynchronous FIFO-based superconducting single-flux quantum cross-clock-domain communication methods.

The invention also provides a client used for any one of the asynchronous FIFO-based superconducting single magnetic flux sub-clock domain crossing communication systems.

According to the scheme, the invention has the advantages that:

the problem of communication of the RSFQ circuit across clock domains can be solved. Specifically, the invention provides a new address comparison circuit, which can reduce the probability of time sequence errors across clock domains and can prevent data errors when the time sequence errors occur; an address generation circuit is provided that generates a set of one hot (onehot) encoded addresses and generates a flag bit that changes once every address change.

Drawings

FIG. 1 is a schematic diagram of a circuit configuration of an address generator of a write control section;

FIG. 2 is a schematic diagram showing a circuit configuration of an address register in the write control section;

FIG. 3 is a schematic diagram showing a circuit configuration of a data register in the write control section;

FIG. 4 is a schematic diagram of a circuit configuration of a full determination portion of the write control portion;

FIG. 5 is a schematic diagram of a circuit structure of an address comparison portion of the address determination portion;

FIG. 6 is a schematic diagram of a circuit configuration of a flag comparison portion in the completion determination portion;

FIG. 7 is a circuit diagram of a register file.

Detailed Description

The inventor finds that by directly using onehot coding as an address, resource consumption can be reduced in an RSFQ circuit, the probability of occurrence of clock collision is reduced, the complexity in address generation is reduced, the RSFQ circuit can be realized by only using an improved shift register, and a decoding circuit is omitted. Then, the two parts of reading and writing adopt the address generated by the opposite side as data, the address generated by the opposite side is put into a group of ndro (non-destructive reading unit), the address generated by the self is used as a clock, if the two groups of addresses are the same, one ndro has the data and the clock at the same time, an output is generated, if the two groups of addresses are different, the ndro does not have the data and the clock, the ndro output is avoided, and each group of addresses only has one pulse, thereby reducing the probability of clock collision.

The invention relates to a superconducting single magnetic flux quantum clock domain crossing communication method based on asynchronous FIFO (first in first out), which comprises a writing part and a reading part, wherein the writing part comprises:

step W1: the FIFO is initialized for 1 restart signal and then issues a ready and write signal to the read/write circuit, respectively, indicating that reading and writing are possible.

Step W2: the external write circuit inputs a write signal to the FIFO. The external circuit refers to a circuit outside the FIFO, and since data in the FIFO needs to be written in from the outside and also can be read out from the outside, the circuit for writing in from the outside to the FIFO is an external write circuit, and the circuit for reading out from the outside to the FIFO is an external read circuit.

Step W3: returning a write signal to the external write circuit, wherein the write signal indicates that the external write circuit can output the written data to the FIFO and can give a write signal of the next writing; and produce and write address and write the mark at the same time, read address and read the mark to compare with this moment, if the equal mark of address is full of FIFO to show on the contrary, turn to step W6; otherwise, go to step W4. The write address and the write flag are generated according to the write signal and the previous write address write flag, the write address is increased by one (actually left-shifted by one bit because of onehot) every time the write signal comes, the write address becomes 1000_0000 after being left-shifted by seven times, the write flag is inverted by the next left shift, and the write address becomes 0000 \u0001. Initially, the write flag and write address are initialized to 0 by the restart signal, and 0000 \u0001. The read address and read flag are initially initialized by the restart signal to 0 and 0000 \ u 0001.Restart will not only be done at the read circuit but also at the compare portion of the write circuit to input the initialized read flag and read address.

Step W4: the external write circuit inputs the data to be written to the FIFO and can input the next write signal.

Step W5: and writing the data into the corresponding write address. If the next write signal is input in step W4, returning to the external write circuit a write signal indicating that the data of this write can be output to the FIFO and that the write signal of the next write can be given, and simultaneously generating a write address and a write flag, comparing with the read address and the read flag at this time, if the address equal flag indicates that the FIFO is full, going to step W6; otherwise, turning to the step W4; if the write signal is not input in step W4, the input of the write signal is waited, and the process proceeds to step W3 after the input.

Step W6: when the FIFO is full, it waits for the read section to read a set of data and generate a new read flag and read address, and then proceeds to step W4.

A reading part:

step R1: the FIFO is initialized for 1 restart signal and then issues a ready and write signal to the read/write circuit, respectively, indicating that reading and writing are possible.

Step R2: the external reading circuit inputs a read signal to the FIFO;

and step R3: if the read signal input by the external circuit to the FIFO does not read the corresponding data, reading the data according to the current read address and returning to the external read circuit; if no read signal is input to the FIFO by the external circuit before, no data to be read is output. A readable signal is returned to the external read circuitry indicating that the next read can be made. Generating a read address and a read mark, comparing the read address with the write mark, if the addresses are the same, the marks are the same and indicate that the FIFO is empty, and the reading can not be continued, and turning to the step R4; otherwise, turning to the step R2.

The FIFO circuit provided by the invention can not generate read data when the first read signal comes, each read signal outputs one data from the second read signal, which is equivalent to a pipeline with the depth of 2, so that the data to be read by the last read signal is read and returned to the external read circuit equivalent to each coming read signal.

Step R4: when the FIFO is empty, step R2 is performed after waiting for the write section to write a set of data to generate a new write address and write flag.

Through the reading and writing processes, the data of the original clock domain circuit can be written into the FIFO, the target clock domain circuit reads the data from the FIFO, and the quart clock domain transmission communication of the data is realized.

In order to make the aforementioned features and effects of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

The asynchronous FIFO comprises a register file, a read control part and a write control part.

The write control part consists of an address generation part, an address register, a data register, a full judgment part and a clock gating part.

As shown in fig. 1, the address generator is composed of 8 rdff (D flip-flop with reset port), one rtffl (T flip-flop with reset port, l indicates that there is a pulse output when there is an odd number of pulses), and one ndro, and first resets the restart signal to empty all the cells in fig. 1, including 8 rdff,1 ndro, and 1 rtffl cells, and inputs a pulse to the lowest rdff. This pulse will then shift up one bit every clock the write circuit so only one of the eight rdff will contain a pulse. The 8 rdff outputs will also form a set of addresses at the same time the clock arrives, with only the rdff output originally containing pulses being 1 and the remaining outputs being 0. Then, after the pulse reaches the eighth rdff, a clock is started, a pulse is also output to rtffl and the ndro emptying end, the ndro is emptied, and then if the pulse reaches the rtffl in an odd number, the rtffl outputs a pulse to the ndro, otherwise, the pulse is not output. When there is a pulse in the ndro, the ndro will output a pulse every clock. The output of the address generator is the 8-bit address of the 8 rdff output and the address tag of the ndro output.

As shown in fig. 2, the address register is composed of eight dff (D flip-flops), and the input is an address output from the address generator, and the saved address is output when the clock arrives.

As shown in fig. 3, the data register is composed of 16 dff, and sixteen bits of data given externally are input and output when the clock comes.

As shown in fig. 4, the full determination section is composed of an address comparison section, a flag comparison section, and a full flag generation section.

As shown in fig. 5, the address comparing section is composed of 7 cbs (merged buffer) of 8 ndro and 3 layers, the input of the ndro is the read address transmitted from the read control section, the clock is the write address transmitted from the write control section, and the clear signal is the read clock transmitted from the read control section. The working principle is as follows: the read address and the write address are in the same format, and are both 8 bits, only one bit is 1, the rest bits are 0, and when the bit with the read address being 1 is the same bit, the read address and the write address are equal. The read control section first clears the 8 ndros after generating the address, and then the read address is sent to the 8 ndros. The write address generator sends addresses to the 8 clock parts of the ndro after outputting a group of addresses, when the read and write addresses are not equal, the ndro has no data or no clock and data, so that no output exists, when the read and write addresses are equal, the ndro has both data and clock, so that a pulse is output, and the pulse is output after passing through the three layers cb.

As shown in fig. 6, the sign comparing portion is composed of an ndro and an xor gate. The input of the ndro is a read address mark sent by the read control part, the clock of the ndro is a write clock, and the emptying part is a read clock. The inputs of the exclusive or gate are the write address flag and the output of this ndro, respectively, and the clock is the write clock. The working mode is that after the read control part generates a read mark, the ndro is cleared firstly, then the read mark is sent into the ndro, then the ndro is read out after the write clock arrives, the clock of the exclusive-OR gate reaches the exclusive-OR gate after the input of the exclusive-OR gate arrives by controlling delay, and when the input of the exclusive-OR gate is different, the read address mark and the write address mark are different, output is generated.

The full flag generation section is one rdff, the data input is the output of the flag comparison section, the clock is the output of the address comparison section, and the clear section is the write clock. The operation is such that the write clock arrives first at rdff to clear it once, then the output of the tag compare section arrives (if any), then the output of the address compare section arrives (if any), and an output is generated if both the data and clock arrive in one write clock cycle.

The clock gating part consists of four dff, one ndro. The input of the ndro is a restart signal and a full mark signal passing through two stages dff, the clock is a write clock directly input, the clear signal is a full mark signal, the ndro directly controls the clock, the clock can pass through the ndro when the ndro has data and then acts on the dff for storing the write signal, when the ndro has no data, the clock is shielded, and the write part stops working. The clock of the first stage dff in the two stages dff through which the full mark reaching the ndro data input port passes is a read clock, which indicates that a new group of read addresses are generated, indicates that the register file is no longer full and can continue to write, and the clock of the second stage dff is a write clock which is not gated and has the function of delaying for one stage so as to avoid the occurrence of timing errors. The write signal is inputted first into a stage dff, and the write clock is outputted after the write clock comes, and outputted to the address generating section and the address comparing section, and simultaneously inputted to the next dff, and outputted to the outside, informing the external circuit that the data can be inputted and the next write signal can be inputted. The signal entering the next stage dff will be output after the write clock comes as the clock for the address register and the data register.

The read control part consists of an address generation part, an address register, a judgment part and a clock gating part.

The address generating part, the address register, the clock gating part and the write control part are the same.

The mark comparison part of the judgment part is provided with one more NOT gate, the write address mark is inverted once before entering the ndro, the NOT gate clock is a write clock, and the rest part is the same as the write control part.

As shown in FIG. 7, the register file is composed of 8 16-bit registers, each register is composed of two sets of sixteen rdffs, data is written into the first set of rdffs when data is written, then the write address determines which register to write into, the first set of rdffs of the selected registers will be written into the second set of rdffs by one clock, and each register will be cleared by a clear signal. When reading data, the register selected by the read address receives a clock signal to read the data.

Regarding clock collision problems across clock domains: because the read-write pointer adopts onehot coding, only one ndro has a clock and only one ndro has data at a moment, and the problem of timing conflict can occur when the ndro of the clock and the data is one.

Assuming that the read pointer is r _ addr, the read flag is r _ sign, the write pointer is w _ addr, and the write flag is w _ sign, assuming that timing conflict occurs at time t1, and the FIFO operates normally before, then r _ addr1= w _ addr1, r _ sign1=! The time interval of the part where r _ addr1, r _ sign1 and w _ addr1, w _ sign1 reach the full judgment part is extremely small and is smaller than the device holding time or the establishing time. Then we consider the last state that r _ addr0 and w _ addr0 are also equal, r _ sign0 and w _ sign0 are opposite, and it must be that r _ addr0 and r _ sign0 come first, because if w _ addr0 and w _ sign0 come first, which means that the write address has already exceeded the read address by one week, then the FIFO has already gone wrong, and this will not happen. Therefore, r _ addr0 and r _ sign0 come first, so that when w _ addr0 and w _ sign0 come, the full part is judged to be full, the generation of a write address is stopped, and a new write address is not generated until a next read pointer comes and a write cycle is delayed, so that the assumed situation cannot occur. No errors occur that should be judged full but not.

The following are system examples corresponding to the above method examples, and this embodiment can be implemented in cooperation with the above embodiments. The related technical details mentioned in the above embodiments are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the above-described embodiments.

The superconducting single-magnetic-flux sub-clock-domain crossing communication system based on the asynchronous FIFO comprises a register file, a read control circuit and a write control circuit;

the flag comparison circuit of the empty judgment circuit is provided with one more NOT gate, the write address flag is firstly inverted once before entering the nondestructive reading unit, the NOT gate clock is a write clock, and other circuits of the empty judgment circuit are the same as the full judgment circuit of the write control circuit.

The write module is configured to generate a write address and a write flag according to the write signal, and specifically: resetting the write flag and the write address according to the initialization signal, then increasing one write address every time the FIFO receives a write signal, and after increasing the specified times of the write address, negating the write flag and resetting the write address;

the reading module is used for generating a reading address and a reading mark, and specifically comprises the following steps: and resetting the read mark and the read address according to the initialization signal, wherein the read address is increased by one every time the FIFO receives a read signal, and the read mark is inverted and the read address is reset after the read address is increased by a specified number of times.

Claims

1. A superconducting single magnetic flux quantum clock domain crossing communication method based on asynchronous FIFO is characterized by comprising the following steps:

the address generator is composed of a plurality of D triggers, rtffl and a nondestructive reading unit, and is used for emptying all units in the address generator when a reset signal arrives, and inputting a pulse to the lowest bit D trigger, wherein the pulse shifts upwards by one bit every coming from one clock of the external writing circuit, the outputs of all the D triggers form a group of addresses when the clock arrives, wherein only the output of the D trigger originally containing the pulse is 1, the rest outputs are 0, then the pulse arrives at the highest bit D trigger, then the clock comes, a pulse is output to the rtffl and the emptying end of the nondestructive reading unit, the nondestructive reading unit is emptied, then if the odd number of pulses arrive at the rtffl, the rtffl outputs a pulse to the nondestructive reading unit, otherwise, the rtffl cannot output, when the pulse exists in the nondestructive reading unit, every clock comes, the nondestructive reading unit outputs a pulse, and the output of the address generator is the address output by all the D triggers and the address mark of the nondestructive reading unit;

the mark comparison circuit consists of a non-destructive reading unit and an exclusive-OR gate, wherein the input of the non-destructive reading unit is a reading address mark of the reading control circuit, the clock of the non-destructive reading unit is a writing clock, and the emptying circuit is a reading clock; the inputs of the exclusive-OR gate are respectively a write address mark and the output of the nondestructive reading unit, and the clock is a write clock; the read control circuit sends a read mark to the nondestructive read unit of the mark comparison circuit after generating a read mark, then reads the nondestructive read unit of the mark comparison circuit after a write clock arrives, and leads the clock of the exclusive-OR gate to arrive at the exclusive-OR gate after the input of the exclusive-OR gate arrives by controlling delay, and when the input of the exclusive-OR gate is different, the read-write address mark is different, output is generated;

the read control circuit consists of an address generation circuit, an address register, an arbitration circuit and a clock gating circuit;

the composition and working principle of the address generating circuit, the address register and the clock gating circuit of the read control circuit are the same as those of the address generating circuit, the address register and the clock gating circuit of the write control circuit;

3. The asynchronous FIFO based superconducting single flux quantum cross-clock domain communication method of claim 1,

the process of generating the write address and the write flag according to the write signal in the step 1 specifically comprises the following steps: resetting the write mark and the write address according to the initialization signal, then increasing one write address every time the FIFO receives a write signal, and after increasing the specified times of the write address, negating the write mark and resetting the write address;

4. The asynchronous FIFO-based superconducting single flux quantum cross-clock domain communication method of claim 1, wherein the write address and the read address both employ unique thermal coding.

5. A superconducting single flux sub-clock domain crossing communication system based on asynchronous FIFO, comprising:

6. The asynchronous FIFO-based superconducting single-flux sub-clock-domain-crossing communication system of claim 5, wherein the FIFO comprises a register file, a read control circuit, a write control circuit;

the address comparison circuit comprises a plurality of non-destructive reading units and a multi-layer fusion buffer, wherein the input of the non-destructive reading units is the reading address of the reading control circuit, the clock is the writing address of the writing control circuit, and the emptying signal is the reading clock transmitted by the control circuit; when the read-write addresses are equal, the read control circuit generates an address and then empties all the nondestructive read-out units in the address comparison circuit, then the read address is sent to all the nondestructive read-out units in the address comparison circuit, the write address generator sends the address to the clock circuits of all the nondestructive read-out units in the address comparison circuit after outputting a group of addresses, when the read-write addresses are equal, one nondestructive read-out unit in the address comparison circuit has both data and a clock, so that a pulse is output, and the pulse is output after the multilayer fusion buffer;

7. The asynchronous FIFO based superconducting single magnetic flux sub-clock domain communication system of claim 5,

8. The asynchronous FIFO based superconducting single flux sub-clock domain communication system of claim 5, wherein the write address and the read address are both thermally encoded individually.

9. A storage medium storing a program for executing the asynchronous FIFO based superconducting single flux quantum cross-clock domain communication method according to any one of claims 1 to 4.