JPH0535909B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a simulator, and particularly to a simulator that uses a semiconductor integrated circuit (hereinafter referred to as an IC) that is actually used in a system such as an LSI as a simulation model. Regarding the simulator.

[Conventional technology]

In the development of theoretical circuits, it has become common practice to perform logic simulations and test the logic before operating and testing the actual device in order to discover design and manufacturing errors. . However, as the scale of equipment increases, the problem is that it takes too much time to simulate a system that includes many LSIs, and it is becoming difficult to create a simulation model of the LSIs that will be used. It is. Therefore, in recent years, a method called "hardware modeling" has been adopted, in which the actual LSI is used as a simulation model. If you do it like this
There is no need to create a logic model inside the LSI, and simulation evaluation can be performed at a speed close to real time, making it possible to speed up the process. However, generally
Since LSI uses a dynamic logic circuit and has a complex internal state, it is not possible to step-execute the LSI in synchronization with the simulation itself. Therefore, a vector memory is provided to store the history of all input signals from the start of the simulation to the present, and each time an input change event occurs, this vector memory is read from the beginning and the input sequence is given to the LSI from the beginning and the state is Restoration is being done.

[Problem that the invention seeks to solve]

The conventional simulators mentioned above use hardware modeling techniques to supply the entire history to the IC from the beginning each time each input event arrives, so as the number of clocks to be simulated increases, it takes time to evaluate them. This has the disadvantage of deteriorating the overall performance.

An object of the present invention is to provide a simulator that eliminates such conventional drawbacks and performs high-speed processing.

[Means for solving problems]

The simulator of the present invention is a logic simulator that uses an IC as a simulation model.
To store the entire history of input signals of the IC from the start of simulation to the clock of the previous simulation target, and use the sweep clock to sweep out the entire history stored in the memory and supply it to the IC to reproduce the state of the IC up to that point. vector memory and IC
When an input signal change event comes from the main body of the logic simulator, the state set part adds the event to the vector memory, and when a signal from the simulation main body that starts simulation of the next clock to be simulated is input, it is swept to the vector memory. The process of starting the clock supply and reproducing up to the previous simulation target clock is performed in parallel with the simulation unit simulating the simulation target clock, and then changes the input signal to the IC coming from the simulation unit. The input signal change with the event state set added to the IC
It has a control section and an event output section that detects output changes corresponding to changes in the input signal of the IC and returns them as events to the simulator main body.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, one embodiment of the present invention is
It includes an IC 1, a vector memory 2, a control section 3, a setting section 4, an event output section 5, and a simulation main body 10. When the vector memory 2 receives the sweep clock 103, it outputs supply events 104 in order from the beginning of the memory, and when it finishes sweeping the last stored event, it ends 10.
Roll a 7. Further, the vector memory 2 is connected to the set section 4.
When a set event 102 is input from , the event is registered at the end of the memory. When the set section 4 receives an event 100 from the simulation main body 10, it outputs a set event 102. IC1 receives a supply event 104, performs a predetermined operation, and outputs an output 105. When the control circuit 3 receives a simulation clock start signal 101 from the simulation main body 10, it immediately starts supplying the sweep clock 103. When the sweep of the previous clock from the vector memory 2 is completed and the end 107 is returned, the control circuit 3 stops supplying the sweep clock 103, and the set section 4 issues a set event 102 to set the clock of the simulation in question. When an event is input, one sweep clock 103 is generated, a supply event 104 is output from the vector memory 2, and the IC 1 is caused to perform internal processing. When IC1 outputs the result output 105 after performing predetermined internal processing, the event output unit 5 outputs 1.
05 is sensed and returned to the simulator body 106 as a response event 106.

FIG. 2 shows an example of the configuration of the vector memory 2 of this embodiment. In FIG. 2, the vector memory 2 includes counters 20 and 21, a comparator 22, a multiplexer 23, a memory 24, and control circuits 25 and 26.
It has Counter 20 stores the number of vectors stored so far, and counter 21 indicates the current number of clocks that have been swept out. counter 21
is initialized when the clock start signal 101 is input, and advances the count each time the sweep clock 103 is input. The outputs 201 and 202 of each of the counters 20 and 21 are compared by a comparator 22 and outputs a termination signal 107 after one pause. When the control circuit 25 receives the event 102, it issues a set command 203, causes the multiplexer 23 to select the address 206 as the output 201, and writes it to the memory 24.
05 and increments the counter 20 by one. The control circuit 26 performs a read access 207 to the memory 24 every time the sweep clock 103 comes, and issues a supply event 104 as read data.

FIG. 3 is a time chart of simulation processing to show the difference in results between the simulator of the present invention and a conventional simulator. FIG. 3A shows the case of a conventional simulator. The line indicated by 30 is the processing of the simulator main body, and the shaded area is the part where the actual processing is performed. 31 is IC
This is the processing part for the simulator, and the main body of the simulator is the IC
Since the next process is performed after waiting for the previous process, the overall processing time takes longer. FIG. 3B shows the case of the simulator of the present invention, in which processing of the simulator main body and processing of the IC can be performed in parallel at the start of each clock. The double hatched area is the part that actually needs to be evaluated by the main unit in the relevant simulation clock, and the process of restoring the previous state can be performed simultaneously and independently from the processing of the simulation main unit, resulting in faster processing. Realized.

In this way, the simulator of this example is similar to the actual
In a logic simulator that uses an IC as a simulation model, the entire history of the input signal of IC1 is stored from the start of simulation to the clock of the previous simulation target, and the entire history stored in IC1 is swept out using the sweep-out clock.
a vector memory 2 for reproducing the previous state of the IC1; a state setting unit 4 for adding an event to the vector memory when a change event 100 of the input signal to the IC1 comes from the main unit 10 of the logic simulator; When a signal 101 to start simulation of the next clock to be simulated is input from the simulation main body 10, the clock 103 is flushed out to the event memory 2.
In parallel with the simulation main unit 10 simulating the clock to be simulated, the process of reproducing up to the previous clock to be simulated is performed. A control unit 3 supplies the input signal change 104 to which the state setting unit 4 added the change event 100 to the IC1, and an input signal change 105 of the IC1.
The simulator body 1 detects the output change corresponding to
Event output unit 5 that returns event 106 to 0
It consists of:

〔Effect of the invention〕

According to the present invention, as explained above, an IC such as an LSI that is actually used is used as a simulation model, and the process of reproducing the IC state necessary for each simulation cycle is performed with the simulator itself. It is possible to perform parallel operations simultaneously, and a high-speed simulator can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing the vector memory 2 of this embodiment, and FIG. 3 is a time chart of simulation processing to show the difference in effect between the simulator of the present invention and a conventional simulator. DESCRIPTION OF SYMBOLS 1... Semiconductor integrated circuit, 2... Vector memory, 3, 25, 26... Control circuit, 4... Set section, 5... Event output section, 10... Simulation main body, 20, 21... Counter, 22 ……
Comparator, 23...Multiplexer, 24...Memory.

Claims (1)

[Claims] 1. In a logic simulator that uses a semiconductor integrated circuit as a simulation model, the entire history of input signals of the semiconductor integrated circuit is stored from the start of simulation to the clock of the previous simulation target, and is stored by a sweep clock. a vector memory for reproducing the state of the semiconductor integrated circuit up to that point by extracting the entire history of the semiconductor integrated circuit; and a vector memory for reproducing the state of the semiconductor integrated circuit until then; When inputting a state setting unit that adds the event to the vector memory and a signal from the simulation main body to start simulation of the next simulation target clock, it starts supplying the sweep clock to the vector memory and continues the simulation up to the previous one. A process for reproducing up to the target clock is performed in parallel with the simulation of the target clock by the simulation main body, and then the change event of the input signal to the semiconductor integrated circuit coming from the simulation main body is set to the state. a control unit that supplies the input signal change added by the unit to the semiconductor integrated circuit; and an event output unit that detects an output change corresponding to the input signal change of the semiconductor integrated circuit and returns it as an event to the simulator main body. A simulator featuring