SU1386996A1 - Data channel simulator - Google Patents

Abstract

The invention relates to computing and can be used to simulate information packages. The process of setting up, monitoring and diagnosing digital device faults. The purpose of the invention is to reduce the hardware cost of the device. The goal is achieved in that the device containing the shift register 3, counter 7, pulse generator 5, synchronization block I, memory block 6, multiplexer 10, two elements AND 8 and 9, the element OR 4, adder 2 modulo two are entered, a buffer memory unit 12, a group of elements 11. The simulated information is formed by selectively recording in the buffer memory unit 12 a block of pseudo-random codes generated by the shift register 3 with feedback 2 in accordance with the characteristics stored in memory block 6 ti. The buffer memory unit 12 smooths the output information flow. 1 hp f-ly, 4 ill. 9 figure 1

Description

The invention relates to computing and can be used to simulate information signals at the inputs of digital devices during their autonomous tuning, performance testing and troubleshooting.

The purpose of the invention is to reduce the hardware cost of the device. FIG. 1 shows the functional scheme of the device; in fig. 2 - diagram of the synchronization unit; in fig. 3 - timing diagrams explaining the operation of the synchronization unit; in fig. 4 is a block circuit diagram, option.

The device for simulating information channels contains a synchronization unit 1, an adder 2 modulo two, a shift register 3, an OR 4 element, a pulse generator 5, a memory lok 6, a counter 7, the first 8 and the second AND elements, a multiplexer 10, a group of 11 And elements , block 12 of buffer memory (BZU) first 13 and second 14 inputs of clock pulses, information input 15, input 16 of the operation mode, address input 17, input 18 of the initial installation, input 19 of reading (data), information you) 20, the output 21 of the feature of filling the BZU 12, the outputs 22-25 of the synchronization unit 1 (Fig. 1).

The buffer memory unit 12 contains a memory 26, a multiplexer 27, a write address counter 28, a read address counter 29, a volume counter 30, and a decryptor 31 (Fig. 1).

The synchronization unit 1 contains pulse shapers 32-34 and the element OR 35 (FIG. 2).

The synchronization unit 1 (option) contains shift registers 36 and 37, elements AND 38 and 39, pulse generator 40, elements OR NOT 41 and 42, and element OR 43 (FIG. 4).

The device works as follows.

In the device, the formation of information signals for tunable and monitored objects is based on programmable sifting out of the initial sequence of pseudorandom codes (UCS) obtained using the pitch generator based on the register 3 and the adder 2 in feedback, code combinations that are forbidden for the controlled object. With the help of this programmable selection of UCS, a large number of output code sequences with different structures can be obtained.

Before the start of operation, a logical < 1 > signal input to input 18, the device is brought to its initial state. In this case, the counters 28-30 are nullified in the RAM 12, the initial code combination is entered into the register 3, and also the passage of pulses from the output of the generator 5 through the element 9 is allowed. The pulses from the output

element AND 9 is fed to the counting input of counter 7 and through the element OR 4 to the input of the record of block 6. In the initial installation process, the information input 15 constantly contains a logical signal “1. A unit is recorded in the cell of block 6, whose address is set on the counter 7, and on the falling edge of the write pulse the address in the meter 7 is modified. The duration of the initial setup signal at input 18 must satisfy the following condition:

,

where n is the number of cells in block 6;

f is the frequency of the pulses generated by the generator 5.

In this case, during the initial installation, units are written in all the cells of block 6.

five

After the initial setup, a selection program is loaded into block 6, which determines which code combinations, when simulating information packets, should be separated from the original UCS sequence. In addition, for each code of the n possible codes of the UCS sequence, generated by register 3 with adder 2, in block 6, one bit is allocated to the address that matches this code. The presence of units in this bit allows the proliferation of the corresponding pseudo-random code to the information outputs 20 of the device, and the presence of a zero blocks the issuance of this code. After the initial installation in all cells of block 6, the unit is skidded, which permits the passage of all

from the UCS generator codes to the information outputs 20. To remove some combinations from the output code sequence, in block 6, zeros are written to the addresses that match the codes to be deleted. For this purpose, an input signal 16 is supplied with a signal “О”, which sets the loading mode of the selection program and provides the connection of inputs 17 through multiplexer 10 to information inputs of counter 7, to information input 15 of output5.

logical signal "Oh, to address

Input 17 is a prohibited code that must be removed from the output sequence of the device, and input 14 is a tracking pulse.

Consider the operation of the device under the condition that the synchronization unit 1 is implemented, as shown in FIG. 2. Then the tracking impulse from input 14 passes through the OR element 35 to the input of the record of the counter 7 and enters the address from the input 17 into it. In the cell of block 6, the address of which is recorded in the counter 7, zero is entered. A similar operation is performed for the rest of the forbidden codes.

After the download of the selection program is completed, a logical signal "1" is applied to the input 16, which sets the mode for simulating information packages. Multiplexer 10 connects the outputs of shift register 3 to the information inputs of counter 7. At input 13, clock pulses are supplied to the first input of block 1 and to the synchronous input of register 3, which begins to form the sequence of the PSK. On the leading edge of each clock pulse, information is shifted in register 3 and another pseudo-random code appears at its outputs, which is fed to the information inputs of memory 26 and through multiplexer 10 to the information inputs of counter 7. On the falling edge of the clock pulse, driver 32 generates a pulse which arrives at the address input of the multiplexer 27 and the memory recording input 26. The multiplexer 27 connects the counter 28 to the address inputs of the memory 26. At the address stored in the counter 28, pseudo a partial code from the outputs of the register 3. A pulse from the output of the imaging unit 32 passes through the OR element 35 to the input of the record of the counter 7, into which the code from the outputs of the register 3 is written through the multiplexer 10. The logical signal "O at the output of the element OR 4 sets the data reading mode from the block 6. At the information output of block 6, the contents of the cell whose address is recorded in the counter 7 appears. The output signal of block 6 is fed to the input of element AND 8. In block 1, a pulse from the output of the former 32 is also fed to the input of the former 33, which is on the falling edge this and The pulse generates a pulse passing through the element AND 8 to the input of the modification of the address of the entry of the BZU 12, if the output of block 6 is set to a logical signal "1, i.e. if the outputs of the register 3 formed the allowed pseudo-random code. If the output of block 6 is set to a logical signal “Oh, i.e. At the outputs of register 3, a forbidden code is present, the passage of a pulse from shaper 33 through element 8 is blocked. With an allowed pseudo-random code, the pulse from the output of the element And 8 increases by one the contents of the counters 28 and 30.

Thus, for each clock pulse at input 13, register 3 with adder 2 generates a pseudo-random code that is stored in memory 26 independently of the selection program. However, the address of the record and the amount of stored information in the RAM 12 is modified only when the combinations, t. e. in the BZU 12, only the allowed pseudo-random codes remain.

After the accumulation of the block of allowed codes in BZU 12 at the output of the decoder 31

a logical "i" signal is generated. The decoder 31 generates a logical signal "1, if the contents of the counter 30 is greater than or equal to t, and outputs it to the output 21, the message

to the control object that an information block can be read from the device. The exchange of simulated information between the device and the control object is carried out in blocks of m words. Upon receipt

Q resolution for reading data, the control object outputs 19 packets of m sync signals. To synchronize the device and the control object, it is necessary that the clock pulses at the input 13 and the clock pulses at the input 19 are generated from

5 one clock frequency (for this purpose, the clock generator of the control object can be used). In this case, the operations of writing and reading data from the BZU 12 at the expense of block 1 are separated by time. When reading data from the device at the input of the record BZU 12 there is a logical signal "O. The memory 26 is in the read mode, and the multiplexer 27 connects the outputs of the counter 29 to the address inputs of the memory 26. At the outputs of the RAM 12, the code stored in it is set to the address generated by the counter 29. With the arrival of the sync pulse at the input 19, elements and 11 and at the information outputs 20 a code is read, read from the BZU 12. On the falling edge of the clock pulse

0, the contents of counter 29 are incremented by one and the contents of counter 30 are decremented by one. Ana.u., and the next code is read from the device.

At the end of the information block

5, the control object checks the state of the output 21. If the logical signal "1" is set at the output 21, reading from the device of the next data block starts. Otherwise, the object of control

Q goes into standby mode. When imitating the information of the LPU 12, the output information flow is smoothed. As a result of screening out forbidden combinations, an uneven information flow is generated from the UCS sequence, which in a number of cases cannot be used for input into monitored devices, while data outputs 20 are outputting data with a uniform frequency. The synchronization unit 1 (Fig. 4) has a more stable time ratio in comparison with the unit (Fig. 2), since it does not have pulse shapers, but it also requires a large amount of hardware.

The synchronization unit 1 (FIG. 4) operates as follows.

In the initial state, the logical "O" signals are set at inputs 13 and 14, therefore registers 36 and 37 are filled with zeros.

At the outputs of the elements OR-NOT 4 and 42 signals are formed logical "1. When a logical signal "1" arrives at input 13, a unit is recorded for the first digit of shift register 36, and a logical signal "O that closes the AND 38 element is set at the output of the OR-HE element 41. The recorded unit advances by clock pulses of the generator 40 register 36 shift. Signals are first formed at outputs 24 and 25, and then at output 22. The duration of the logical signal "1 at input 13 should be; ЗТ, where T is the pulse period at the output of generator 40. Similarly, when a logical signal is received," 1 at the input , 14, the signal is first generated at the output 24, and then at the output 23. The signal duration of the logical "1 at the input 14 should be.

Claims (2)

1. A device for simulating information channels containing a memory block whose information input is the information input of the device, a synchronization block whose first and second clock inputs are the first and second inputs of the device’s clock, the first and second elements AND, the first inputs which are connected respectively with the first output of the synchronization unit and the output of the pulse generator, the counter, the counting input and the recording input of which are connected respectively with the output of the second element And the second The output of the synchronization unit, the information input of the counter is connected to the output of the multiplexer, the first information input of which is connected to the output of the shift register, characterized in that, to reduce the hardware costs of the device, a modulo two is entered into it, OR, a block of buffer memory 40 and a group of elements AND, the output and the input of the modulo adder two are connected respectively to the information input and output of the shift register, a synchronous input connected to the first input of the clock pulses of the device, formation input and output of the buffer memory block 0 five 40 .g Here, respectively, with the shift register output and the first inputs of the AND elements of the group, the outputs of which form a group of information outputs of the device, the second inputs of the AND elements of the group are the input of the device and are connected to the read input of the buffer memory block, the output of the sign of filling is the output of the device clock pulses and the input of the modification of the address of the record and the input of the block of the buffer memory are connected respectively to the output of the first element I and the third output of the synchronization block, the fourth output is connected The first input and output of the element OR, the second input and output of which are connected respectively to the output of the second element AND and the recording input of the memory block, the address input and output connected respectively to the output of the counter and the second input of the first element AND the address input and the second information input of the multiplexer are respectively, the address input and the input for setting the device operation mode, the reset inputs of the shift register, the buffer memory block and the second input of the second element I are connected to the installation input of the device. 2. A device according to claim 1, characterized in that the buffer memory block comprises a memory, a multiplexer, a write address counter, a read address counter, a volume counter and a decoder, the information input and output of the memory being the same as the input and output of the block, the memory write input and the control input of the multiplexer form the block write input, the output and the first, second information inputs of the multiplexer are connected respectively to the memory address input and the outputs of the write address and reading address, the reset inputs of which and the reset input The volume counters are the reset input of the block, the counting inputs of the write address counter and the volume counter are input to the block write address, the count input of the read address counter and the subtracting volume counter input are the read input of the block, the volume counter output is connected to the decryptor input, the output of which is the output of the sign of filling the block. Phi2.2 13 1if 22 23 2 25 Editor A. Kozoriz Order 1223/48 Compiled by V. Vertlib Tehred I. VeresKorrektor M. Sharoshi Circulation 704Subscribe VNIIPI USSR State Committee for Inventions and Discoveries 1 13035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4 (D / g.Z. .//