CN100458715C - Device and method for monitoring handshake circuit - Google Patents
Device and method for monitoring handshake circuit Download PDFInfo
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- CN100458715C CN100458715C CNB2006101733664A CN200610173366A CN100458715C CN 100458715 C CN100458715 C CN 100458715C CN B2006101733664 A CNB2006101733664 A CN B2006101733664A CN 200610173366 A CN200610173366 A CN 200610173366A CN 100458715 C CN100458715 C CN 100458715C
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Abstract
A monitoring device of a handshake circuit is prepared for utilizing a counter to record effective time of each request signal, setting an error signal to record time that response is not occurred for ack signal on effective time of request signal in set time range and to record relevant waveform at certain time before and after error is occurred for accurately positioning error occurrence time of handshake circuit and for quickly finding error out.
Description
Technical field
The present invention relates to handshake circuit design, particularly a kind of handshake circuit monitoring device and method.
Technical background
Usually use handshake mechanism to coordinate both sides' data transfer operation in the digital circuit.Handshake mechanism adopts the formula of replying, and all serves as that high effectively situation is an example with request signal and answer signal below, and its ultimate principle is described.As shown in Figure 1, at first sent the request signal of a high level by originating end, i.e. request signal is notified the other side to ask to send or is begun to send data; And send the response impulse of a high level, i.e. ack signal under the responding terminal situation that ready or Data Receiving finishes at all; When originating end receives the ack signal pulse, immediately the request signal is pulled down and become low level, show end of conversation.Clk is a clock signal among the figure.
The phenomenon that common handshake circuit is made mistakes is that in the stipulated time after the request signal is drawn high, the ack signal can not be in time or no longer produced pulse signal forever, makes the request signal be suspended in high level after for a long time.
Main method of testing to this mistake of handshake mechanism is by oscillograph or logic analyser request signal and ack signal to be guided on the display at present, judges by the waveform of observing them whether handshake circuit is correct.
Above-mentioned monitoring method is more directly perceived, but in the very high occasion of frequency of shaking hands, and rising edge or their combination trigger condition by request signal or ack signal often are difficult to the accurately wrong moment of taking place of location, and then can't do further debugging.
Summary of the invention
In view of this, what the present invention need solve is exactly in the very high occasion of frequency of shaking hands, and rising edge or their combination trigger condition by request signal or ack signal are difficult to the accurately technical matters in the wrong moment of taking place of location.
In order to solve the problems of the technologies described above, the invention provides a kind of handshake circuit monitoring device, the request signal request signal that is used for monitoring handshake circuit effectively after, the mistake that answer signal ack signal fails in time to reply comprises: counter is used for the term of validity length of described request signal is counted, described counter begins counting after the request signal is effective, if the request invalidating signal, counter is with regard to zero clearing so, and the counter output valve is designated as req_counter; The rub-out signal generator, be used to produce the wrong error signal constantly that takes place of sign, if answer signal ack signal has responded the request signal in the setting-up time scope of request signal after effectively in n clock period, error invalidating signal so, n is a compare threshold; If the ack signal is not response slowly, more than or equal to the setting-up time scope during n clock period, the ack signal still is invalid at req_counter, and the error signal just becomes effectively so, and when the ack signal pulse arrived, it is invalid that the error signal just becomes.
Preferably, described rub-out signal generator is formed by comparer, phase inverter and with door, and described request signal is connected to counter, is connected to simultaneously and door; The output req_counter of described counter inputs to comparer, in store compare threshold n in the described comparer; Described ack signal is connected to phase inverter, and the output of described comparer, phase inverter and request signal all are connected to the input end with door, are output as the error signal with door; Described comparer is used for comparison req_counter signal and compare threshold n; Phase inverter is used for the negate of ack signal; With door be used for output and request signal with the output of comparer, phase inverter carry out " with " operation, to obtain the error signal; Described request, ack and error are effectively high, and counter begins counting after the request signal uprises, if the request invalidating signal, counter is with regard to zero clearing so, and counter output is designated as req_counter; If ack signal setting-up time scope after the request signal is drawn high has responded the request signal in n clock period, the output error signal of so described rub-out signal generator is low always; If the ack signal is not response slowly, during more than or equal to n, the ack signal still is low at req_counter, and the error signal just becomes high level so, and when the ack signal pulse arrived, the error signal just can be invalid.
Further, also comprise the signal storage module, as trigger condition, the value of the coherent signal of several clocks changes into waveform and preserves before the trigger collection condition with the rising edge of error signal for it.
Preferably, collection is more than or equal to the value of the coherent signal of n clock period.
Further, the described signal storage module storer that is oscillograph or logic analyser.
Further, comprise that also the counter compare threshold is provided with the unit, be used for obtaining threshold value n, produce circuit by counter threshold and realize, and counter threshold produces the output input of device as a comparison of circuit according to the signal relevant with the requirement of ack actual response time.
The present invention also provides a kind of handshake circuit monitoring method, may further comprise the steps:
100, begin counting, the invalid then counter O reset of request signal at the effective hour counter of request signal;
Wherein, request signal request signal, answer signal ack signal and rub-out signal error signal are effectively high, and counter begins counting after the request signal uprises, if the request invalidating signal, counter is with regard to zero clearing so, and counter output is designated as req_counter;
200, be high at request signal, count value is greater than setting value n simultaneously, and answer signal provides rub-out signal when invalid.
If the ack signal has responded the request signal in n clock of setting-up time scope after the request signal is drawn high, the output error signal of rub-out signal generator is low always so; If the ack signal is not response slowly, during greater than n, the ack signal still be low at req_counter, and the error signal just becomes high level so, and when the ack signal pulse arrived, error signal ability was invalid.
Further, also comprise step:
300, as trigger condition, the correlated signal values of several clocks before the trigger collection condition is in order to debugging with the rising edge of error signal.
Preferably, the value of the coherent signal of described several clocks of collection is specially the information of collection more than or equal to n clock period.
Further, can be according to requiring relevant signal to obtain threshold value n with the ack actual response time.
The present invention utilizes each effective time of request signal of a counter records, and the situation that an error signal record effective time ack of request signal signal in the setting-up time scope is set does not have response in time moment of taking place, and preserve the wrong generation waveform correlation of front and back certain hour constantly, take place constantly and the effect of searching mistake thereby realized quick and precisely locating the handshake circuit mistake.Monitoring device circuit of the present invention is simple, and overhead is little, and effect quick and precisely.The present invention is applicable to the occasion that the frequency of shaking hands is high.
Description of drawings
Fig. 1 is the signal sequence synoptic diagram of handshake mechanism;
Fig. 2 is apparatus of the present invention synoptic diagram;
Fig. 3 is the circuit diagram of an embodiment of apparatus of the present invention;
Fig. 4 is for using signal sequence synoptic diagram of the present invention;
Fig. 5 is the process flow diagram of the inventive method;
Fig. 6 is the further improved circuit diagram to the embodiment of the invention.
Embodiment
Below in conjunction with Figure of description apparatus and method of the present invention are described in detail.
At first explanation, apparatus of the present invention are the mistakes that are used for the observation circuit handshake circuit, so other circuit part that has comprised handshake circuit except apparatus of the present invention represents with basic circuit that in accompanying drawing 2,3 it also is not used in a certain circuit of true finger.
Setting request signal request signal, answer signal ack signal and rub-out signal error signal among the embodiment of described below device and method all is high useful signal.In actual applications, have the effective situation of promising other level of request signal and ack signal, can use device such as phase inverter circuit to be made adjusting slightly and can obtain corresponding observation circuit according to actual conditions.
Simple declaration handshake mechanism principle at first once more adopts and replys formula, is at first sent the request signal of a high level by originating end, i.e. request signal is notified the other side to ask to send or begun to send data; And response impulse of pull-up, i.e. ack signal under the responding terminal situation that ready or Data Receiving finishes at all; When originating end receives the ack signal pulse, immediately the request signal is pulled down, show end of conversation.
As shown in Figure 2, apparatus of the present invention comprise:
1) counter begins counting after the request signal uprises, if request signal step-down, counter is with regard to zero clearing so, and counter output is designated as req_counter;
2) rub-out signal generator is used to produce the error signal, if responded the request signal in the time range that the ack signal is set (for example, uprising n the clock in back) after the request signal is drawn high, the error signal is 0 always so; If the ack signal is not response slowly, during more than or equal to n, the ack signal still is 0 at req_counter, and the error signal just becomes high level so, and when the ack signal pulse arrived, the error signal just became 0 subsequently.Be essential condition that the error signal uprises be the request signal for high, the ack signal is low, req_counter is during more than or equal to n.
Further, apparatus of the present invention can also comprise signal storage module (not shown), with the rising edge of error signal as trigger condition, on oscillograph or logic analyser, gather the signal of several clocks, as n before the trigger condition or greater than the value of n clock coherent signal, change into waveform and preserve and get off to make things convenient for our further debugging.Described signal storage module can be the storer on oscillograph or the logic analyser.
As shown in Figure 3, be the circuit diagram of the embodiment of apparatus of the present invention.In this embodiment, the error signal generating circuit is formed by comparer, phase inverter and with door.The request signal is connected to counter, is connected to simultaneously and door, and the output req_counter of counter inputs to a comparer, and the time range of in store setting in the described comparer is designated as threshold value n; The ack signal is connected to a phase inverter.The output of described comparer, phase inverter and request signal all are connected to the input end with door.Comparer is used for the time range n of comparison req_counter signal and setting; Phase inverter is used for the negate of ack signal; With door be used for output and request signal with the output of comparer, phase inverter carry out " with " operation, to obtain the error signal.
As shown in Figure 4, be the sequential chart of each signal that apparatus of the present invention produced.As seen from the figure, when req_counter equaled n, the ack signal was low, not response, and at this moment the error signal becomes high level.When the ack signal pulse arrived, the error signal just became 0 subsequently afterwards.After the ack signal became low level, the request signal was a step-down, req_counter zero clearing at this moment.
The inventive method process flow diagram comprises the following steps: as shown in Figure 5
100 begin counting, the invalid then zero clearing of request signal when request signal is effective;
When request signal request signal is high, begin counting, in case that request signal becomes is low, then zero clearing when treating that the request signal is high, restarts counting, and counter value is designated as req_counter.
200 is high at request signal, and count value is greater than setting value n simultaneously, and answer signal provides rub-out signal when invalid;
Preestablish a threshold value n, if req_counter is effective less than n and ack signal, if promptly responded the request signal in time range n the clock that the ack signal is set after the request signal is drawn high, then error signal maintenance initial value is 0; If req_counter is more than or equal to n and ack invalidating signal, if promptly at req_counter during more than or equal to n, the ack signal slowly not response still be 0, the error signal just becomes high level so; When the ack signal pulse arrived, the error signal just became 0 subsequently.
Further, can also comprise following step:
300, as trigger condition, the correlated signal values of several clocks before the trigger collection condition is in order to debugging with rub-out signal.
Can be with described error signal as trigger condition, make oscillograph or logic analyser preserve the correlated signal values of several clocks before each error signal down, as can be for n or greater than the Wave data of the coherent signal of n clock, in order to debugging.Described coherent signal can comprise clk, request signal, ack signal and other signal etc.
The above embodiment of the present invention is specially adapted to periodically in the handshake mechanism, at this moment the moment of ack signal response more fixing, promptly threshold value n is more fixing, so can obtain the circuit of error signal easily by simple counting and numeric ratio.
Provide an example of using the basic circuit of said apparatus or method below.Supposing has two storeies in modules A inside, is used to receive the data segment from the B module.Each storer is deposited a data segment.Expired a data segment if certain storer is received, A just sends out the request signal and gives C, allows C take away, and another storer continues to receive new data segment simultaneously.If C gets the data segment that is over, C just sends out the ack signal and gives A so, tells the current storage data to be got sky.Because the data of coming from B are endlessly, so before data segment fills up second storer, C must in time take all data of first storer away, otherwise C does not also have enough time to take away the data of first storer, and the new data segment of coming from B will cover original data.Supposes that the data speed that B issues A is uniformly, be assumed to be m=5ms/, and the data number in each data segment is k that the time of filling up a storer from the data of B is 5*kms so.That is to say that when first storer filled up data, A sent out the request signal to C, C must fill up second storer at B, must send out the ack response signal to A in the stipulated time of 5*k ms just at once.If the data number k of each data segment is a fixed value, just belong to periodic handshake mechanism, compare threshold n is a fixed value so, and promptly n equals 5*k/ length cycle length.Above-mentioned example is periodic handshake mechanism, for acyclic handshake mechanism, if promptly ack signal response opportunity fixing, can come the n value is provided with according to the needs of the concrete condition on ack signal response opportunity so.Still utilizing between above-mentioned A, B, the C module and to transmit data conditions and illustrate that for example if the data number is indefinite in each data segment, promptly k value changes, is exactly acyclic handshake mechanism at this moment.In this case, C still need deposit back reading of data in the storer in a partial data section, and need run through data and send the ack signal before next data segment deposit another storer fully in.When we suppose that B issues the A data, also have two id signal start and end:start=1 to represent the head of a data segment, end=1 represents the end of a data segment.If after in first storer, depositing a partial data section in so, A can send out the request signal at once, here second storer begins to store next data segment, be that the start signal is effective, so before the end signal is effective, must have the ack signal to return to A, otherwise the data in first storer will be capped.So in this case, n is not a fixed value just, but relevant with the id signal start and the end of input, is specially n=(end significant instant-start significant instant)/cycle length length.
For above-mentioned aperiodic situation, as shown in Figure 6, can be provided with by in apparatus of the present invention, increasing counter threshold generation circuit threshold value n, the threshold value that its output is connected to comparer is preserved end.Circuit can be more flexible like this, and the scope of application is bigger, is not limited only in the periodic circuit.
The present invention can fast and effeciently locate the wrong moment that produces by observing the error signal, and it as trigger condition, and then is obtained the waveform of this many coherent signal of moment.In the higher occasion of the frequency of shaking hands, especially can easily locate the wrong moment of taking place, find the problem place by analyzing the coherent signal waveform at last.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of handshake circuit monitoring device, the request signal request signal that is used for monitoring handshake circuit effectively after, the mistake that answer signal ack signal fails in time to reply is characterized in that, comprising:
Counter is used for the term of validity length of described request signal is counted, and described counter begins counting after the request signal is effective, if the request invalidating signal, counter is with regard to zero clearing so, and the counter output valve is designated as req_counter;
The rub-out signal generator, be used to produce the wrong error signal constantly that takes place of sign, if answer signal ack signal has responded the request signal in the setting-up time scope of request signal after effectively in n clock period, error invalidating signal so, n is a compare threshold; If the ack signal is not response slowly, more than or equal to the setting-up time scope during n clock period, the ack signal still is invalid at req_counter, and the error signal just becomes effectively so, and when the ack signal pulse arrived, it is invalid that the error signal just becomes.
2, device according to claim 1 is characterized in that,
Described rub-out signal generator is formed by comparer, phase inverter and with door, and described request signal is connected to counter, is connected to simultaneously and door; The output req_counter of described counter inputs to comparer, in store compare threshold n in the described comparer; Described ack signal is connected to phase inverter, and the output of described comparer, phase inverter and request signal all are connected to the input end with door, are output as the error signal with door;
Described comparer is used for comparison req_counter signal and compare threshold n; Phase inverter is used for the negate of ack signal; With door be used for output and request signal with the output of comparer, phase inverter carry out " with " operation, to obtain the error signal;
Described request, ack and error are effectively high, and counter begins counting after the request signal uprises, if the request invalidating signal, counter is with regard to zero clearing so, and counter output is designated as req_counter; If ack signal setting-up time scope after the request signal is drawn high has responded the request signal in n clock period, the output error signal of so described rub-out signal generator is low always; If the ack signal is not response slowly, during more than or equal to n, the ack signal still is low at req_counter, and the error signal just becomes high level so, and when the ack signal pulse arrived, the error signal just can be invalid.
3, device according to claim 2 is characterized in that, also comprises the signal storage module, and as trigger condition, the value of the coherent signal of several clocks changes into waveform and preserves before the trigger collection condition with the rising edge of error signal for it.
4, device according to claim 3 is characterized in that, gathers the value more than or equal to the coherent signal of n clock period.
5, device according to claim 3 is characterized in that, described signal storage module is the storer of oscillograph or logic analyser.
6, according to any described device in the claim 1 to 5, it is characterized in that, comprise that also the counter compare threshold is provided with the unit, be used for obtaining threshold value n according to the signal relevant with the requirement of ack actual response time, produce circuit by counter threshold and realize, and counter threshold produces the output input of device as a comparison of circuit.
7, a kind of handshake circuit monitoring method is characterized in that, may further comprise the steps:
100, begin counting, the invalid then counter O reset of request signal at the effective hour counter of request signal;
Wherein, request signal request signal, answer signal ack signal and rub-out signal error signal are effectively high, and counter begins counting after the request signal uprises, if the request invalidating signal, counter is with regard to zero clearing so, and counter output is designated as req_counter;
200, be high at request signal, count value is greater than setting value n simultaneously, and answer signal provides rub-out signal when invalid;
If the ack signal has responded the request signal in n clock of setting-up time scope after the request signal is drawn high, the output error signal of rub-out signal generator is low always so; If the ack signal is not response slowly, during greater than n, the ack signal still be low at req_counter, and the error signal just becomes high level so, and when the ack signal pulse arrived, error signal ability was invalid.
8, method according to claim 7 is characterized in that, also comprises step:
300, as trigger condition, the correlated signal values of several clocks before the trigger collection condition is in order to debugging with the rising edge of error signal.
9, method according to claim 8 is characterized in that, the value of the coherent signal of described several clocks of collection is specially the information of collection more than or equal to n clock period.
10, according to any described method in the claim 7 to 9, it is characterized in that, can be according to requiring relevant signal to obtain threshold value n with the ack actual response time.
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| CNB2006101733664A CN100458715C (en) | 2006-12-30 | 2006-12-30 | Device and method for monitoring handshake circuit |
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| CNB2006101733664A CN100458715C (en) | 2006-12-30 | 2006-12-30 | Device and method for monitoring handshake circuit |
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| CN102591739B (en) * | 2012-01-06 | 2014-09-24 | 深圳市沛城电子科技有限公司 | Method and device for aligning serial synchronous communication data |
| US9810778B2 (en) * | 2015-09-14 | 2017-11-07 | Semiconductor Components Industries, Llc | Triggered-event signaling with digital error reporting |
| CN106569162B (en) * | 2016-10-17 | 2019-04-02 | 深圳市鼎阳科技有限公司 | A kind of the analog bandwidth measurement method and device of logic analyser probe |
| CN116486852A (en) * | 2022-01-14 | 2023-07-25 | 长鑫存储技术有限公司 | Clock circuit, clock alignment system and clock alignment method |
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| GB2135782A (en) * | 1983-02-28 | 1984-09-05 | United Technologies Corp | Oscillatory sensor failure monitor |
| CN1135058A (en) * | 1995-03-31 | 1996-11-06 | 富士通株式会社 | Information processing unit, device and method |
| US6633577B1 (en) * | 1997-03-26 | 2003-10-14 | Nec Corporation | Handshaking circuit for resolving contention on a transmission medium regardless of its length |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2135782A (en) * | 1983-02-28 | 1984-09-05 | United Technologies Corp | Oscillatory sensor failure monitor |
| CN1135058A (en) * | 1995-03-31 | 1996-11-06 | 富士通株式会社 | Information processing unit, device and method |
| US6633577B1 (en) * | 1997-03-26 | 2003-10-14 | Nec Corporation | Handshaking circuit for resolving contention on a transmission medium regardless of its length |
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| 计算机组成原理. 唐朔飞，59,63，高等教育出版社. 2002 |
| 计算机组成原理. 唐朔飞，59,63，高等教育出版社. 2002 * |
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