CN106230404B - Sequential control circuit - Google Patents
Sequential control circuit Download PDFInfo
- Publication number
- CN106230404B CN106230404B CN201610669404.9A CN201610669404A CN106230404B CN 106230404 B CN106230404 B CN 106230404B CN 201610669404 A CN201610669404 A CN 201610669404A CN 106230404 B CN106230404 B CN 106230404B
- Authority
- CN
- China
- Prior art keywords
- switching tube
- clock signal
- phase inverter
- output end
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/503—Resource availability
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Abstract
The present invention provides a kind of sequential control circuit, including sequentially connected, first clock signal generating device, second clock signal generating apparatus and third clock signal generating device, first clock signal generating device receives externally input initial clock signal, when initial clock signal enters rising edge, the triggering of first clock signal generating device generates the first clock signal, first duty cycle control module controls the duty ratio of the first clock signal, when the first clock signal enters failing edge, second clock signal generating apparatus generates second clock signal, the duty ratio of second duty cycle control module control second clock signal, when second clock signal enters failing edge, third clock signal generating device generates pulse clock signal.Entire sequential control circuit, different clock signals are all to have relationship with previous clock, are reacted to subsequent clock automatically up when the variation of previous clock, realize and carry out reasonable and effective management to timing.
Description
Technical field
The present invention relates to field of computer technology, more particularly to sequential control circuit.
Background technique
Sequential control circuit is used for the sequencing coordinated, control action (program or instruction) executes, and is widely used in
In computer field.By taking CAM RAM in computer as an example, CAM RAM be CAM (Content-addressable memorg, it is interior
Hold addressable memory) and RAM (random access memory, random access memory) combiner, CAMRAM usually needs
Cooperate and carrys out work.
CAM RAM is mainly used on the caching of cpu (Central Processing Unit, central processing unit), is cached
It is the very critical component in cpu storage system, its speed is usually consistent with the speed of cpu, there is caching
The ability of the access data of cpu is improved according to the allocation plan in time and space.It is therefore desirable to the timing plans to CAM RAM
Slightly do detailed research.
However, a kind of sequential control circuit there is no rationally and effectively manage to CAM RAM timing at present.
Summary of the invention
Based on this, it is necessary to rationally and effective for there is no a kind of sequential control circuit to carry out CAM RAM timing at present
The problem of management, provides a kind of sequential control circuit, realizes and rationally and effectively manage to CAM RAM timing.
A kind of sequential control circuit, including sequentially connected first clock signal generating device, second clock signal generate
Device and third clock signal generating device, the first clock signal generating device are built-in with the first duty cycle control module, the
Two clock signal generating devices are built-in with the second duty cycle control module；
First clock signal generating device receives externally input initial clock signal, when initial clock signal enters rising
Along when, the first clock signal generating device triggering generate the first clock signal, the first duty cycle control module control the first clock
The duty ratio of signal, when the first clock signal enters failing edge, second clock signal generating apparatus generates second clock signal,
Second duty cycle control module controls the duty ratio of second clock signal, when second clock signal enters failing edge, when third
Clock signal generating apparatus generates pulse clock signal.
Sequential control circuit of the present invention, including sequentially connected first clock signal generating device, second clock signal are raw
At device and third clock signal generating device, the first clock signal generating device receives externally input initial clock letter
Number, when initial clock signal enters rising edge, the triggering of the first clock signal generating device generates the first clock signal, and first accounts for
Sky controls the duty ratio of the first clock signal, when the first clock signal enters failing edge, second clock signal than control module
Generating means generate second clock signal, and the second duty cycle control module controls the duty ratio of second clock signal, when second
When clock signal enters failing edge, third clock signal generating device generates pulse clock signal.Entire sequential control circuit, it is different
Clock signal be all to have relationship with previous clock (clock signal received), when previous clock variation when it is automatic
It is reacted to subsequent clock (clock signal of output) up, this timing Adjusted Option closely facilitates, and not will cause volume
Outer timing waste is realized and carries out reasonable and effective management to timing.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the one of embodiment of sequential control circuit of the present invention；
Fig. 2 is the circuit theory schematic diagram of the one of embodiment of sequential control circuit of the present invention；
Fig. 3 is the structural schematic diagram of the one of application example of sequential control circuit of the present invention；
Fig. 4 is the circuit theory schematic diagram of the one of application example of sequential control circuit of the present invention；
Fig. 5 is the waveform diagram of output signal in the one of application example of sequential control circuit of the present invention.
Specific embodiment
Clock Control (clock control) module is clock (clock) signal for handling into, generates different phases
The clock of position, as CMP_CLK (comparison search clock signal), SAP_CLK (comparing sampled clock signal), SA_CLK are (sensitive to put
Big device clock pulses), can the phase precision of these clock directly influence circuit and work normally, while timing of the present invention
Control circuit also joined the effect that timing is adjustable and timing can track in Clock control circuit, so that circuit
It is easy to adjust out limiting frequency on silicon wafer (external input signal), so that performance greatly improves.In timing of the present invention
In control circuit, the first clock signal, second clock signal, third clock signal are in chronological sequence sequentially generated, the first clock
Signal and second clock signal all use clock self-contr ol circuit, and the first clock signal is only with the rising edge of initial clock signal
There is relationship, the duty ratio of initial clock signal is not required, therefore also only rise the requirement for having shake to clock, better than general
High level with clock control internal clocking.Second clock signal is directly controlled using the failing edge of the first clock signal
It generating, the benefit controlled in this way is that second clock signal can be and then generated when the first clock signal, which terminates, to be sampled,
Avoid additional timing expense.Third clock signal is sensitive to control by one burst pulse of failing edge generation of second clock signal
The work of amplifier.Here it is emphasized that when the pulse of the first clock signal adjustment, the timing of second clock signal
The pulse width of the first clock signal can be followed automatically mobile, in addition third clock signal is also that can directly track the first clock letter
Number and second clock signal pulse regulation and automatically adjust movement, so that the adjustment of timing be facilitated to achieve the purpose that high speed.
As shown in Figure 1, a kind of sequential control circuit, including sequentially connected first clock signal generating device 100, second
Clock signal generating device 200 and third clock signal generating device 300, the first clock signal generating device 100 are built-in with
First duty cycle control module 120, second clock signal generating apparatus 200 are built-in with the second duty cycle control module 220；
First clock signal generating device 100 receives externally input initial clock signal, when initial clock signal enters
When rising edge, the triggering of the first clock signal generating device 100 generates the first clock signal, the control of the first duty cycle control module 120
The duty ratio for making the first clock signal, when the first clock signal enters failing edge, second clock signal generating apparatus 200 is generated
Second clock signal, the second duty cycle control module 220 control the duty ratio of second clock signal, when second clock signal enters
When failing edge, third clock signal generating device 300 generates pulse clock signal.
Sequential control circuit of the present invention, including sequentially connected first clock signal generating device 100, second clock signal
Generating means 200 and third clock signal generating device 300, the first clock signal generating device 100 receive externally input
Initial clock signal, when initial clock signal enters rising edge, when the triggering of the first clock signal generating device 100 generates first
Clock signal, the first duty cycle control module 120 controls the duty ratio of the first clock signal, when the first clock signal enters failing edge
When, second clock signal generating apparatus 200 generates second clock signal, and the second duty cycle control module 220 controls second clock
The duty ratio of signal, when second clock signal enters failing edge, third clock signal generating device 300 generates pulse clock letter
Number.Entire sequential control circuit, different clock signals are all to have relationship with previous clock (clock signal received), when
Previous clock is reacted to subsequent clock (clock signal of output) up automatically when variation, this timing Adjusted Option
Closely facilitate, not will cause additional timing waste, realizes and reasonable and effective management is carried out to timing.
As shown in Fig. 2, in one of the embodiments, the first clock signal generating device 100 include first switch tube T1,
Second switch T2, third switch transistor T 3, the 4th switch transistor T 4, the first phase inverter I1, the second phase inverter I2, third phase inverter I3
And the 4th phase inverter I4；
The input terminal of first switch tube T1 connects external power supply, and the output end of first switch tube T1 is with second switch T2's
Input terminal connection, the output end of second switch T2 are connect with the input terminal of third switch transistor T 3, the output of third switch transistor T 3
End ground connection, the control terminal of first switch tube T1 connect with the output end of the first phase inverter I1, the control terminal of second switch T2 and
The input terminal of second phase inverter I2 connects, and the control terminal of second switch T2 receives initial clock signal, third switch transistor T 3
Control terminal connect with the output end of the second phase inverter I2, the input terminal of third phase inverter I3 is defeated with first switch tube T1 respectively
The connection of the input terminal of outlet and second switch T2, the control with the 4th switch transistor T 4 respectively of the output end of third phase inverter I3
End and the connection of the first duty cycle control module 120, the input terminal of the 4th switch transistor T 4 connect external power supply, the 4th switch transistor T 4
Output end connect respectively with the input terminal of the first duty cycle control module 120 and the 4th phase inverter I4, the 4th phase inverter I4
Output end connect respectively with the input terminal of second clock signal generating apparatus 200 and the first phase inverter I1.
When initial clock signal rising edge comes, since the control terminal of third switch transistor T 3 has odd number reverser, the
Turn-on time while two switch transistor Ts 2 have of short duration with third switch transistor T 3, first switch tube T1 and second switch T2 it
Between node potential drag down, the first clock signal is drawn high by subsequent three-level phase inverter, is made using the first phase inverter I1
First switch tube T1 conducting, finally drags down the first clock signal the pulse to form self circuit.
As shown in Fig. 2, the first duty cycle control module 120 includes the 5th switch transistor T 5, the in one of the embodiments,
Six switch transistor Ts 6, the 7th switch transistor T 7, the 8th switch transistor T 8, the 9th switch transistor T 9, the tenth switch transistor T 10, the 11st switching tube
T11 and the 12nd switch transistor T 12；
The input terminal of 5th switch transistor T 5, the input terminal of the 6th switch transistor T 6, the input terminal of the 7th switch transistor T 7 and
The input terminal of eight switch transistor Ts 8 is all connected with the output end of the 4th switch transistor T 4 and the input terminal of the 4th phase inverter I4, the 5th switching tube
The control terminal of T5 is connect with the output end of third phase inverter I3, the control of the control terminal, the 6th switch transistor T 6 of the 5th switch transistor T 5
The control terminal at end, the control terminal of the 7th switch transistor T 7 and the 8th switch transistor T 8 is sequentially connected, the output end of the 5th switch transistor T 5
It being connect with the input terminal of the 9th switch transistor T 9, the output end of the 6th switch transistor T 6 is connect with the input terminal of the tenth switch transistor T 10, the
The output end of seven switch transistor Ts 7 is connect with the input terminal of the 11st switch transistor T 11, the output end and the 12nd of the 8th switch transistor T 8
The input terminal of switch transistor T 12 connects, output end, the 11st switching tube of the output end of the 9th switch transistor T 9, the tenth switch transistor T 10
The output end of T11 and the output end of the 12nd switch transistor T 12 are grounded, the control terminal of the 9th switch transistor T 9, the tenth switching tube
The control terminal of the control terminal of T10, the control terminal of the 11st switch transistor T 11 and the 12nd switch transistor T 12 receives external control respectively
Signal processed.
9th switch transistor T 9, the tenth switch transistor T 10, the 11st switch transistor T 11 and the 12nd switch transistor T 12 receive outside
Signal is controlled, situation is on or turns off, specifically, it is defeated that chip difference can be controlled by external harmoniousness in practical applications
Signal is controlled out to the 9th switch transistor T 9, the tenth switch transistor T 10, the 11st switch transistor T 11 and the 12nd switch transistor T 12.By
There are two kinds of situations of conducting and shutdown in each switching tube, then the first duty cycle control module 120 has 4*4=16 kind combination feelings
Condition carrys out the driving capability of control switch pipe (the 4th switch transistor T 4) drop-down so as to freely adjust the pulse of the first clock signal
Width.
As shown in Fig. 2, the first clock signal generating device 100 further includes first capacitor C1 in one of the embodiments,
One end of first capacitor C1 is connect with the input terminal of the 4th phase inverter I4, the other end ground connection of first capacitor C1.
First capacitor C1 is to use the load for then simulating matched line (match line), so that entire sequential control circuit energy
Enough more rationally, timing control is accurately realized.
The second phase inverter I2 includes the odd number phase inverter monomer being sequentially connected in series in one of the embodiments,.
The number of phase inverter monomer will affect the delay duration of the second phase inverter I2 in second phase inverter I2, that is, change second
The number of phase inverter monomer can change the control terminal and third switch transistor T 3 that signal reaches second switch T2 in phase inverter I2
Control terminal between time difference, can also change the duration of second switch T2 Yu the of short duration conducting of third switch transistor T 3, because
This, can the quantity for needing to reasonably select phase inverter monomer in the second phase inverter I2 based on practical application scene (quantity is necessary
For odd number).It preferably, include 3 phase inverter monomers in the second phase inverter I2, such one side second switch T2 is opened with third
The duration for closing the of short duration conducting of pipe T3 can generate pulse that is complete and being captured by subsequent conditioning circuit, on the other hand not will cause timing wave
Take.
As shown in Fig. 2, second clock signal generating apparatus 200 includes the 13rd switching tube in one of the embodiments,
T13, the 14th switch transistor T 14, the 15th switch transistor T 15, sixteenmo close pipe T16, the 5th phase inverter I5, hex inverter
I6, the 7th phase inverter I7, the 8th phase inverter I8 and the 9th phase inverter I9；
The input terminal of 9th phase inverter I9 is connect with the first clock signal generating device 100, the output of the 9th phase inverter I9
It holds and is connect with the control terminal of the 14th switch, the input terminal of the 13rd switch transistor T 13 connects external power supply, the 13rd switching tube
The output end of T13 is connect with the input terminal of the 14th switch transistor T 14, the output end of the 14th switch transistor T 14 and the 15th switch
The input terminal of pipe T15 connects, the output end ground connection of the 15th switch transistor T 15, and the control terminal of the 13rd switch transistor T 13 is anti-with the 5th
The output end of phase device I5 connects, the control terminal of the 14th switch transistor T 14 respectively with the input terminal of hex inverter I6 and the 9th
The output end of phase inverter I9 connects, and the control terminal of the 15th switch transistor T 15 is connect with the output end of hex inverter I6, and the 7th is anti-
The input terminal of phase device I7 is connect with the output end of the 13rd switch transistor T 13 and 14 input terminal of the 14th switch transistor T respectively, and the 7th
The output end of phase inverter I7 closes the control terminal of pipe T16 with sixteenmo respectively and the second duty cycle control module 220 is connect, the
The input terminal that sixteenmo closes pipe T16 connects external power supply, and the output end that sixteenmo closes pipe T16 is controlled with the second duty ratio respectively
The connection of the input terminal of module 220 and the 8th phase inverter I8, the output end of the 8th phase inverter I8 are raw with third clock signal respectively
It is connected at the input terminal of device 300 and the 5th phase inverter I5.
When first clock signal rising edge comes, since the 9th phase inverter I9 exists, it is input to the 14th switch transistor T 14
Signal is failing edge, when the first clock signal failing edge comes, since the 9th phase inverter I9 exists, is input to the 14th and opens
The signal of pass is rising edge.In simple terms, second clock signal generating apparatus 200 generates the mechanism and first of second clock signal
The mechanism that clock signal generating device 100 generates the first clock signal is identical, i.e., ought be input to the signal of the 14th switch transistor T 14
When for rising edge, since the control terminal of the 15th switch transistor T 15 has odd number reverser, the 14th switch transistor T 14 and the 15th
Turn-on time while switch transistor T 15 has of short duration, the node between the 13rd switch transistor T 13 and the 14th switch transistor T 14
Current potential drags down, and second clock signal is drawn high by subsequent three-level phase inverter, makes the 13rd to open using the 5th phase inverter I5
Pipe T13 conducting is closed, finally second clock signal is dragged down the pulse to form self circuit.
As shown in Fig. 2, the second duty cycle control module 220 includes the 17th switching tube in one of the embodiments,
T17, eighteenmo close pipe T18, the 19th switch transistor T 19, the 20th switch transistor T 20, the 21st switch transistor T the 21, the 20th
Two switch transistor Ts 22, the 23rd switch transistor T 23 and the 24th switch transistor T 24；
Input terminal, the eighteenmo of 17th switch transistor T 17 close the input of the input terminal, the 19th switch transistor T 19 of pipe T18
End and the 20th switch transistor T 20 input be all connected with sixteenmo pass pipe T16 output end and the 8th phase inverter I8 it is defeated
Enter end, the control terminal of the 17th switch transistor T 17 is connect with the output end of the 7th phase inverter I7, the control of the 17th switch transistor T 17
Control terminal, the control terminal of the 19th switch transistor T 19 and the control terminal of the 20th switch transistor T 20 of pipe T18 is closed at end, eighteenmo
It is sequentially connected, the output end of the 17th switch transistor T 17 is connect with the input terminal of the 21st switch transistor T 21, and eighteenmo closes pipe
The output end of T18 is connect with the input terminal of the 22nd switch transistor T 22, the output end and the 23rd of the 19th switch transistor T 19
The input terminal of switch transistor T 23 connects, and the output end of the 20th switch transistor T 20 is connect with the input terminal of the 24th switch transistor T 24,
The output end of 21st switch transistor T 21, the output end of the 22nd switch transistor T 22, the 23rd switch transistor T 23 output end
And the 24th the output end of switch transistor T 24 be grounded, the control terminal of the 21st switch transistor T 21, the 22nd switching tube
The control terminal of the control terminal of T22, the control terminal of the 23rd switch transistor T 23 and the 24th switch transistor T 24 receives outer respectively
Portion controls signal.
In simple terms, the second duty cycle control module 220 is identical as the structure of the first duty cycle control module 120, i.e., and
21 switch transistor Ts 21, the 22nd switch transistor T 22, the 23rd switch transistor T 23 and the 24th switch transistor T 24 receive
External control signal is on or turns off situation, specifically, can control chip point by external harmoniousness in practical applications
The 21st switch transistor T 21, the 22nd switch transistor T 22, the 23rd switch transistor T 23 and second are not output control signals to
14 switch transistor Ts 24 (patch silicon wafer).Since each switching tube has two kinds of situations of conducting and shutdown, then the second duty ratio controls mould
Block 220 have 4*4=16 kind combined situation come the driving capability of control switch pipe (sixteenmo close pipe T16) drop-down so as to
Freely adjust the pulse width of second clock signal.
As shown in Fig. 2, second clock signal generating apparatus 200 further includes the second capacitor C2 in one of the embodiments,
One end of second capacitor C2 is connect with the input terminal of the 8th phase inverter I8, the other end ground connection of the second capacitor C2.
Second capacitor C2 is loaded for simulating at bit line (bit line), so that entire sequential control circuit can be closed more
Reason accurately realizes timing control.
Hex inverter I6 includes the odd number phase inverter monomer being sequentially connected in series in one of the embodiments,.
Hex inverter I6 is similar with the second phase inverter I2 structure, and details are not described herein.
As shown in Fig. 2, third clock signal generating device 300 includes the tenth phase inverter in one of the embodiments,
I10, the 11st phase inverter I11 and and logic module, the input terminal of the tenth phase inverter I10 and second clock signal generating apparatus
200 connections, the output end of the tenth phase inverter I10 respectively with the input terminal of the 11st phase inverter I11 and with logic module the
The connection of one input terminal, the output end of the 11st phase inverter I11 are connect with the second input terminal with logic module.
With logic module can for door, with the first input end of logic module directly receives the tenth phase inverter I10 export
Signal, the tenth phase inverter I10 output signal also pass through the 11st phase inverter I11 delay after is input to and logic module
Second input terminal, since signal can generate delay in the 11st phase inverter I11, with the first input end of logic module and second
It is poor that the time of input terminal input signal can have a certain time, generates burst pulse wave with logic module in this way.
The 11st phase inverter I11 includes sequentially connected odd number phase inverter monomer in one of the embodiments,.
11st phase inverter I11 is similar with the second phase inverter I2 and hex inverter I6 structure, and phase inverter is arranged inside
Number will affect signal delay, finally will affect third clock signal generating device 300 output narrow-band impulse pulse it is wide
Degree.
It, below will be with for the technical solution and its bring effect for further explaining in detail sequential control circuit of the present invention
Timing control is carried out to CAM RAM, the first clock signal is CMP_CLK, second clock signal is SAP_CLK, third clock letter
Number for for SA_CLK, and the waveform diagram (Fig. 5) of Fig. 3, Fig. 4 and generation is combined, is described in detail.
As shown in figure 3, timing spent by the part CAM is that CMP_CLK is raised, search line (search row) is sent
Into CAM array (cam array), ML (match line, matched line) is exported more afterwards, ML is then sampled by SAP_CLK
Whether match, if matching starts to send out WLpulse (word line pulse), is opened after BL or BLN (bit line) discharges to a certain extent
SA_CLK is opened, start to work reads data to sense amplifier (search amplifier).The purpose of sequential control circuit of the present invention
These timing times are exactly allowed to control more reasonable, relatively reliable and higher operating rate.Clock control part is this hair
Bright key.
As shown in figure 4, CMP_CLK in sequential control circuit of the present invention, SAP_CLK, SA_CLK is in chronological sequence sequentially produced
Raw, CMP_CLK and SAP_CLK use clock self-contr ol circuit, and CMP_CLK only has relationship with the rising edge of CLK, to CLK
Duty ratio do not require, therefore also only clock risen have the requirement of shake, controlled better than traditional high level with clock
Internal clocking processed.SAP_CLK directly controls generation using the failing edge of CMP_CLK, and the benefit controlled in this way is to work as CMP_CLK
And then end can generate SAP_CLK when can sample, avoid additional timing expense.SA_CLK by SAP_CLK decline
The work of sense amplifier is controlled along a burst pulse is generated.
C_ml is the load for simulating match line, and S0<3:0>can (in above-mentioned<3:0>, 0~3 be respectively referred to 16 kinds of combinations
Generation different preset pulse wavelength) carry out the driving capability of control switch pipe drop-down so as to freely adjust the pulse of CMP_CLK
Width.C_bl is the load for simulating bit line, the driving capability that S1<3:0>can have 16 kinds of combinations to carry out the drop-down of control switch pipe
SAP_CLK is adjusted so as to facilitate.Here it is emphasized that when the pulse of CMP_CLK adjustment, the timing of SAP_CLK
The pulse width of CMP_CLK can be followed automatically mobile, in addition SA_CLK is also the arteries and veins that can directly track CMP_CLK and SAP_CLK
It reconstitutes section and automatically adjusts movement, so that the adjustment of timing be facilitated to achieve the purpose that high speed.
The process that specific pulse generates be it is such, when CLK rising edge comes, since there are three anti-for the control terminal of N1
To device, turn-on time while N0 and N1 have of short duration drags down the node potential between P0 and N0, anti-by subsequent three-level
CMP_CLK is drawn high to device, is connected using a reverser P0, finally CMP_CLK is dragged down to form self circuit
Pulse.The mechanism that SAP_CLK is generated is the same as the identical of CMP_CLK.SA_CLK is the group passed through by the failing edge of SAP_CLK such as Fig. 4
It is logical to generate.
It is illustrated in figure 5 the waveform diagram that sequence circuit of the present invention generates, different clock is to have relationship with previous,
It is reacted to subsequent clock automatically up when the variation of previous clock, this timing Adjusted Option closely facilitates,
Not will cause additional timing waste, on silicon wafer we can be found as long as adjustment S0<3:0>and S1<3:0>one it is most suitable
Timing strategy circuit is worked in most fast frequency, while also have reasonable allowance.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (8)
1. a kind of sequential control circuit, which is characterized in that including sequentially connected first clock signal generating device, second clock
Signal generating apparatus and third clock signal generating device, first clock signal generating device are built-in with the first duty ratio
Control module, the second clock signal generating apparatus are built-in with the second duty cycle control module；
First clock signal generating device receives externally input initial clock signal, when the initial clock signal enters
When rising edge, the first clock signal generating device triggering generates the first clock signal, first duty cycle control module
The duty ratio for controlling the first clock signal, when first clock signal enters failing edge, the second clock signal is generated
Device generates second clock signal, and second duty cycle control module controls the duty ratio of the second clock signal, works as institute
When stating second clock signal and entering failing edge, the third clock signal generating device generates pulse clock signal.
2. sequential control circuit according to claim 1, which is characterized in that first clock signal generating device includes
First switch tube, second switch, third switching tube, the 4th switching tube, the first phase inverter, the second phase inverter, third phase inverter
And the 4th phase inverter；
The input terminal of the first switch tube connects external power supply, the output end of the first switch tube and the second switch
Input terminal connection, the output end of the second switch connect with the input terminal of the third switching tube, and the third switchs
The output end of pipe is grounded, and the control terminal of the first switch tube is connect with the output end of first phase inverter, and described second opens
The control terminal for closing pipe is connect with the input terminal of second phase inverter, and the control terminal reception of the second switch is described initial
Clock signal, the control terminal of the third switching tube are connect with the output end of second phase inverter, the third phase inverter
Input terminal is connect with the input terminal of the output end of the first switch tube and the second switch respectively, the third reverse phase
The output end of device is connect with the control terminal of the 4th switching tube and first duty cycle control module respectively, and the described 4th
The input terminal of switching tube connects external power supply, the output end of the 4th switching tube respectively with first duty cycle control module
And the input terminal connection of the 4th phase inverter, the output end of the 4th phase inverter are raw with the second clock signal respectively
It is connected at the input terminal of device and first phase inverter；First duty cycle control module includes the 5th switching tube, the
Six switching tubes, the 7th switching tube, the 8th switching tube, the 9th switching tube, the tenth switching tube, the 11st switching tube and the 12nd are opened
Guan Guan；The input terminal of 5th switching tube, the input terminal of the 6th switching tube, the input terminal of the 7th switching tube and
The input terminal of 8th switching tube connects with the input terminal of the output end of the 4th switching tube and the 4th phase inverter
It connecing, the control terminal of the 5th switching tube is connect with the output end of the third phase inverter, the control terminal of the 5th switching tube,
Control terminal, the control terminal of the 7th switching tube and the control terminal of the 8th switching tube of 6th switching tube successively connect
It connects, the output end of the 5th switching tube is connect with the input terminal of the 9th switching tube, the output end of the 6th switching tube
It is connect with the input terminal of the tenth switching tube, the output end of the 7th switching tube and the input terminal of the 11st switching tube
Connection, the output end of the 8th switching tube connect with the input terminal of the 12nd switching tube, the 9th switching tube it is defeated
Outlet, the output end of the tenth switching tube, the output end of the 11st switching tube and the 12nd switching tube it is defeated
Outlet is grounded, the control of the control terminal, the control terminal, the 11st switching tube of the tenth switching tube of the 9th switching tube
The control terminal of end processed and the 12nd switching tube receives external control signal respectively.
3. sequential control circuit according to claim 2, which is characterized in that first clock signal generating device also wraps
Include first capacitor, one end of the first capacitor is connect with the input terminal of the 4th phase inverter, the first capacitor it is another
End ground connection.
4. sequential control circuit according to claim 2, which is characterized in that second phase inverter includes being sequentially connected in series
Odd number phase inverter monomer.
5. sequential control circuit according to claim 1, which is characterized in that the second clock signal generating apparatus includes
13rd switching tube, the 14th switching tube, the 15th switching tube, sixteenmo close pipe, the 5th phase inverter, hex inverter, the
Seven phase inverters, the 8th phase inverter and the 9th phase inverter；
The input terminal of 9th phase inverter is connect with first clock signal generating device, the output of the 9th phase inverter
It holds and is connect with the control terminal of the 14th switch, the input terminal connection external power supply of the 13rd switching tube, the described tenth
The output end of three switching tubes is connect with the input terminal of the 14th switching tube, the output end of the 14th switching tube with it is described
The input terminal of 15th switching tube connects, the output end ground connection of the 15th switching tube, the control of the 13rd switching tube
End connect with the output end of the 5th phase inverter, the control terminal of the 14th switching tube respectively with the hex inverter
The connection of the output end of input terminal and the 9th phase inverter, the control terminal of the 15th switching tube and the hex inverter
Output end connection, the input terminal of the 7th phase inverter output end and the described tenth with the 13rd switching tube respectively
The input terminals of four switching tubes connects, the output end of the 7th phase inverter closed respectively with the sixteenmo pipe control terminal and
The second duty cycle control module connection, the input terminal that the sixteenmo closes pipe connect external power supply, the sixteenmo
The output end for closing pipe is connect with the input terminal of second duty cycle control module and the 8th phase inverter respectively, and described the
The output end of eight phase inverters is connect with the input terminal of the third clock signal generating device and the 5th phase inverter respectively；
Second duty cycle control module includes the 17th switching tube, eighteenmo pass pipe, the 19th switching tube, the 20th switch
Pipe, the 21st switching tube, the 22nd switching tube, the 23rd switching tube and the 24th switching tube；Described 17th
The input terminal of switching tube, the eighteenmo close the input terminal and described second of the input terminal of pipe, the 19th switching tube
The input terminal of output end and the 8th phase inverter that the input of ten switching tubes closes pipe with the sixteenmo is connect, described
The control terminal of 17th switching tube is connect with the output end of the 7th phase inverter, the control terminal of the 17th switching tube, institute
State eighteenmo close the control terminal of the control terminal of pipe, the control terminal of the 19th switching tube and the 20th switching tube according to
The output end of secondary connection, the 17th switching tube is connect with the input terminal of the 21st switching tube, the eighteenmo
The output end for closing pipe is connect with the input terminal of the 22nd switching tube, the output end of the 19th switching tube and described the
The input terminal of 23 switching tubes connects, the output end of the 20th switching tube and the input terminal of the 24th switching tube
Connection, output end, the 23rd switching tube of the output end of the 21st switching tube, the 22nd switching tube
Output end and the output end of the 24th switching tube be grounded, it is the control terminal of the 21st switching tube, described
The control of the control terminal of 22nd switching tube, the control terminal of the 23rd switching tube and the 24th switching tube
End receives external control signal respectively.
6. sequential control circuit according to claim 5, which is characterized in that the second clock signal generating apparatus also wraps
Include the second capacitor, one end of second capacitor is connect with the input terminal of the 8th phase inverter, second capacitor it is another
End ground connection.
7. sequential control circuit according to claim 1, which is characterized in that the third clock signal generating device includes
Tenth phase inverter, the 11st phase inverter and believe with logic module, the input terminal of the tenth phase inverter and the second clock
The connection of number generating means, the output end of the tenth phase inverter respectively with the input terminal of the 11st phase inverter and it is described with
The first input end of logic module connects, the output end of the 11st phase inverter and second input terminal with logic module
Connection.
8. sequential control circuit according to claim 7, which is characterized in that the 11st phase inverter includes being sequentially connected
Odd number phase inverter monomer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610669404.9A CN106230404B (en) | 2016-08-12 | 2016-08-12 | Sequential control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610669404.9A CN106230404B (en) | 2016-08-12 | 2016-08-12 | Sequential control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106230404A CN106230404A (en) | 2016-12-14 |
| CN106230404B true CN106230404B (en) | 2019-04-19 |
Family
ID=57548184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610669404.9A Active CN106230404B (en) | 2016-08-12 | 2016-08-12 | Sequential control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106230404B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111123140A (en) | 2018-11-01 | 2020-05-08 | 台达电子企业管理（上海）有限公司 | Time-sharing wave recording method |
| CN111813729A (en) * | 2020-07-22 | 2020-10-23 | 曾洁 | Data processing system and method based on flexible circuit board |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1521585A (en) * | 2003-02-13 | 2004-08-18 | 松下电器产业株式会社 | Clock control in sequential circuit for low-power operation and circuit conversion to low-power seqential circuit |
| CN203457123U (en) * | 2011-12-29 | 2014-02-26 | 英特尔公司 | Apparatus and system for clock arrangement |
| CN103684698A (en) * | 2013-12-30 | 2014-03-26 | 龙芯中科技术有限公司 | Method and device for processing data signal |
| CN105763193A (en) * | 2016-02-14 | 2016-07-13 | 中国电子科技集团公司第二十四研究所 | Clock circuit used for high-speed high-precision SHA-less pipelined analog-to-digital converter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006217171A (en) * | 2005-02-02 | 2006-08-17 | Sanyo Electric Co Ltd | Clock extracting circuit |
-
2016
- 2016-08-12 CN CN201610669404.9A patent/CN106230404B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1521585A (en) * | 2003-02-13 | 2004-08-18 | 松下电器产业株式会社 | Clock control in sequential circuit for low-power operation and circuit conversion to low-power seqential circuit |
| CN203457123U (en) * | 2011-12-29 | 2014-02-26 | 英特尔公司 | Apparatus and system for clock arrangement |
| CN103684698A (en) * | 2013-12-30 | 2014-03-26 | 龙芯中科技术有限公司 | Method and device for processing data signal |
| CN105763193A (en) * | 2016-02-14 | 2016-07-13 | 中国电子科技集团公司第二十四研究所 | Clock circuit used for high-speed high-precision SHA-less pipelined analog-to-digital converter |
Non-Patent Citations (1)
| Title |
|---|
| 一种优化低电压SRAM灵敏放大器时序的4T双复制位线延迟技术;叶亚东等;《微电子学与计算机》;20150305;第32卷(第3期);第28-35页 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106230404A (en) | 2016-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1168358B1 (en) | Refresh-type memory with zero write recovery time and no maximum cycle time | |
| EP0045063B1 (en) | Memory device | |
| US8441873B2 (en) | Memory devices and methods of operating memory | |
| CN101483061B (en) | Semiconductor memory device and data processing system including the semiconductor memory device | |
| US11016525B1 (en) | Clock control circuit and clock control method | |
| US7558131B2 (en) | NAND system with a data write frequency greater than a command-and-address-load frequency | |
| CN106230404B (en) | Sequential control circuit | |
| US9870812B2 (en) | Memory system with timing overlap mode for activate and precharge operations | |
| US20050068810A1 (en) | Random access memory with post-amble data strobe signal noise rejection | |
| KR102636444B1 (en) | Precharge control device and system including the same | |
| CN105702296B (en) | A kind of single-particle reinforces the user register state capture circuit of FPGA | |
| TWI533135B (en) | Methods for accessing memory and controlling access of memory, memory device and memory controller | |
| CN1692451A (en) | Semiconductor memory device and method for controlling semiconductor memory device | |
| CN102496389B (en) | Read sequential control circuit | |
| JP2015079552A (en) | Semiconductor storage device | |
| US9183904B2 (en) | Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path | |
| CN103440881A (en) | Content addressable memory system, addressing method and addressing device | |
| CN114155895A (en) | Electronic device for controlling power supply | |
| CN1328646C (en) | Semiconductor device containing changeable detdcting circuit and its starting method | |
| WO2001075623A3 (en) | Zero-latency-zero bus turnaround synchronous flash memory | |
| US6574164B2 (en) | tRCD margin | |
| JP2908776B2 (en) | Write recovery guarantee circuit for memory device and operation signal control method | |
| CN103514934B (en) | Address transition signal detection circuit | |
| WO2024108775A1 (en) | Signal generation circuit, storage system and method | |
| CN101908366A (en) | Automatic timing control method for multi-port storage by single-port storage unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| CB02 | Change of applicant information |
Address after: 412200, Liling City, Hunan Province ceramic science and Technology Industrial Park B District Applicant after: Hunan Hengmao tech Limited by Share Ltd Address before: 412200, Liling City, Hunan Province ceramic science and Technology Industrial Park B District Applicant before: Liling Hengmao Electronics Technology Co., Ltd. |
|
| COR | Change of bibliographic data | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |