CN106230404A - Sequential control circuit - Google Patents
Sequential control circuit Download PDFInfo
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- CN106230404A CN106230404A CN201610669404.9A CN201610669404A CN106230404A CN 106230404 A CN106230404 A CN 106230404A CN 201610669404 A CN201610669404 A CN 201610669404A CN 106230404 A CN106230404 A CN 106230404A
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- switching tube
- clock signal
- input
- outfan
- phase inverter
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/503—Resource availability
Abstract
The present invention provides a kind of sequential control circuit, including be sequentially connected with, first clock signal generating device, second clock signal generating apparatus and the 3rd clock signal generating device, first clock signal generating device receives the initial clock signal of outside input, when initial clock signal enters rising edge, first clock signal generating device triggers and generates the first clock signal, first duty cycle control module controls the dutycycle of the first clock signal, when the first clock signal enters trailing edge, second clock signal generating apparatus generates second clock signal, second duty cycle control module controls the dutycycle of second clock signal, when second clock signal enters trailing edge, 3rd clock signal generating device generates pulse clock signal.Whole sequential control circuit, different clock signals is all with previous clock has relation, is automatically reacted to clock below up, it is achieved carry out reasonable to sequential and effectively manage when previous clock changes when.
Description
Technical field
The present invention relates to field of computer technology, particularly relate to sequential control circuit.
Background technology
Sequential control circuit is used for the sequencing coordinated, control action (program or instruction) performs, and is widely used in
In computer realm.As a example by the RAM of CAM in computer, CAM RAM be CAM (Content-addressable memorg, interior
Hold addressable memory) and the combiner of RAM (random access memory, random access memory), CAMRAM generally needs
Coordinate to come work.
CAM RAM is mainly used on the caching of cpu (Central Processing Unit, central processing unit), caching
Being the very critical component in the middle of cpu storage system, its speed is typically, with the speed of cpu is consistent, had caching the most permissible
Allocative decision according to time and space improves the ability of the access data of cpu.It is therefore desirable to the sequential plan to CAM RAM
Slightly do detailed research.
But, there is no a kind of sequential control circuit at present and CAM RAM sequential is carried out reasonable and effectively manages.
Summary of the invention
Based on this, it is necessary to for there is no at present a kind of sequential control circuit CAM RAM sequential is carried out reasonable and effective
The problem of management, it is provided that a kind of sequential control circuit, it is achieved CAM RAM sequential is carried out reasonable and effectively manages.
A kind of sequential control circuit, generates including the first clock signal generating device being sequentially connected with, second clock signal
Device and the 3rd clock signal generating device, the first clock signal generating device is built-in with the first duty cycle control module, the
Two clock signal generating devices are built-in with the second duty cycle control module；
First clock signal generating device receives the initial clock signal of outside input, rises when initial clock signal enters
Along time, first clock signal generating device trigger generate the first clock signal, the first duty cycle control module controls the first clock
The dutycycle of signal, when the first clock signal enters trailing edge, second clock signal generating apparatus generates second clock signal,
Second duty cycle control module controls the dutycycle of second clock signal, when second clock signal enters trailing edge, when the 3rd
Clock signal generating apparatus generates pulse clock signal.
Sequential control circuit of the present invention, including the first clock signal generating device being sequentially connected with, the life of second clock signal
Device and the 3rd clock signal generating device, the first clock signal generating device is become to receive the initial clock letter of outside input
Number, when initial clock signal enters rising edge, the first clock signal generating device triggers and generates the first clock signal, and first accounts for
The empty dutycycle controlling the first clock signal than control module, when the first clock signal enters trailing edge, second clock signal
Generating means generates second clock signal, and the second duty cycle control module controls the dutycycle of second clock signal, when second
When clock signal enters trailing edge, the 3rd clock signal generating device generates pulse clock signal.Whole sequential control circuit, different
Clock signal be all with previous clock (clock signal received) has relation, automatic when previous clock changes when
Being reacted to clock (clock signal of output) below up, this sequential Adjusted Option closely facilitates, and does not results in volume
Outer sequential waste, it is achieved sequential is carried out reasonable and effectively manages.
Accompanying drawing explanation
Fig. 1 is the structural representation of one of them embodiment of sequential control circuit of the present invention；
Fig. 2 is the circuit theory schematic diagram of one of them embodiment of sequential control circuit of the present invention；
Fig. 3 is the structural representation of one of them application example of sequential control circuit of the present invention；
Fig. 4 is the circuit theory schematic diagram of one of them application example of sequential control circuit of the present invention；
Fig. 5 is the waveform diagram of output signal in one of them application example of sequential control circuit of the present invention.
Detailed description of the invention
Clock Control (clock control) module is used to clock (clock) signal processed into, produces not homophase
The clock of position, as CMP_CLK (comparison search clock signal), SAP_CLK (comparing sampled clock signal), SA_CLK (sensitive are put
Big device clock pulses), can the phase place precision of these clock directly influence circuit and normally work, sequential the most of the present invention
It is adjustable that control circuit also adds sequential in Clock control circuit, and the effect that sequential can be followed the tracks of so that circuit
Silicon chip (external input signal) is easy to adjust limiting frequency, so that performance is greatly improved.In sequential of the present invention
In control circuit, the first clock signal, second clock signal, the 3rd clock signal in chronological sequence order produces, the first clock
Signal and second clock signal all use clock self-contr ol circuit, and the first clock signal is only with the rising edge of initial clock signal
There is relation, the dutycycle not requirement to initial clock signal, the most only clock is risen and have the requirement of shake, be better than general
The high level with clock control internal clocking.Second clock signal directly utilizes the trailing edge of the first clock signal and controls
Producing, the benefit so controlled is can and then to produce second clock signal when the first clock signal terminates to sample,
Avoid extra sequential expense.3rd clock signal is produced a burst pulse by the trailing edge of second clock signal and controls sensitive
The work of amplifier.Here it is emphasized that when the first clock signal pulse adjust time, the sequential of second clock signal
Can automatically follow the pulse width of the first clock signal to move, other 3rd clock signal is also directly to follow the tracks of the first clock letter
Number and the pulse regulation of second clock signal and be automatically adjusted movement, thus facilitate the adjustment of sequential to reach purpose at a high speed.
As it is shown in figure 1, a kind of sequential control circuit, including the first clock signal generating device 100, second being sequentially connected with
Clock signal generating device 200 and the 3rd clock signal generating device 300, the first clock signal generating device 100 is built-in with
First duty cycle control module 120, second clock signal generating apparatus 200 is built-in with the second duty cycle control module 220；
First clock signal generating device 100 receives the initial clock signal of outside input, when initial clock signal enters
During rising edge, the first clock signal generating device 100 triggers and generates the first clock signal, and the first duty cycle control module 120 is controlled
Making the dutycycle of the first clock signal, when the first clock signal enters trailing edge, second clock signal generating apparatus 200 generates
Second clock signal, the second duty cycle control module 220 controls the dutycycle of second clock signal, when second clock signal enters
During trailing edge, the 3rd clock signal generating device 300 generates pulse clock signal.
Sequential control circuit of the present invention, including the first clock signal generating device 100 being sequentially connected with, second clock signal
Generating means 200 and the 3rd clock signal generating device 300, the first clock signal generating device 100 receives outside input
Initial clock signal, when initial clock signal enters rising edge, the first clock signal generating device 100 triggers when generating first
Clock signal, the first duty cycle control module 120 controls the dutycycle of the first clock signal, when the first clock signal enters trailing edge
Time, second clock signal generating apparatus 200 generates second clock signal, and the second duty cycle control module 220 controls second clock
The dutycycle of signal, when second clock signal enters trailing edge, the 3rd clock signal generating device 300 generates pulse clock letter
Number.Whole sequential control circuit, different clock signals is all with previous clock (clock signal received) has relation, when
Automatically clock (clock signal of output) below it is reacted to up, this sequential Adjusted Option when of the change of previous clock
Closely facilitate, do not result in extra sequential waste, it is achieved carry out reasonable to sequential and effectively manage.
As in figure 2 it is shown, wherein in an embodiment, the first clock signal generating device 100 include the first switch transistor T 1,
Second switch pipe T2, the 3rd switch transistor T the 3, the 4th switch transistor T the 4, first phase inverter I1, the second phase inverter I2, the 3rd phase inverter I3
And the 4th phase inverter I4；
The input of the first switch transistor T 1 connects external power source, and the outfan of the first switch transistor T 1 is with second switch pipe T2's
Input connects, and the outfan of second switch pipe T2 and the input of the 3rd switch transistor T 3 connect, the output of the 3rd switch transistor T 3
End ground connection, the outfan controlling end and the first phase inverter I1 of the first switch transistor T 1 connects, the control end of second switch pipe T2 and
The input of the second phase inverter I2 connects, and the control end of second switch pipe T2 receives initial clock signal, the 3rd switch transistor T 3
The outfan connection controlling end and the second phase inverter I2, the input of the 3rd phase inverter I3 defeated with the first switch transistor T 1 respectively
The input going out end and second switch pipe T2 connects, the outfan of the 3rd phase inverter I3 respectively with the control of the 4th switch transistor T 4
End and the first duty cycle control module 120 connect, and the input of the 4th switch transistor T 4 connects external power source, the 4th switch transistor T 4
Outfan input with the first duty cycle control module 120 and the 4th phase inverter I4 respectively be connected, the 4th phase inverter I4
Outfan input with second clock signal generating apparatus 200 and the first phase inverter I1 respectively be connected.
The when that initial clock signal rising edge coming, owing to the control end of the 3rd switch transistor T 3 has odd number reverser, the
Two switch transistor T 2 and the 3rd switch transistor T 3 have of short duration while ON time, the first switch transistor T 1 and second switch pipe T2 it
Between node potential drag down, the first clock signal drawn high by three grades of phase inverters through below, then makes through the first phase inverter I1
First switch transistor T 1 turns on, and finally the first clock signal is dragged down the pulse forming a self-loop.
As in figure 2 it is shown, wherein in an embodiment, the first duty cycle control module 120 include the 5th switch transistor T 5,
Six switch transistor T the 6, the 7th switch transistor T the 7, the 8th switch transistor T the 8, the 9th switch transistor T the 9, the tenth switch transistor T the 10, the 11st switching tubes
T11 and twelvemo close pipe T12；
The input of the 5th switch transistor T 5, the input of the 6th switch transistor T 6, the input of the 7th switch transistor T 7 and
The input of eight switch transistor T 8 is all connected with outfan and the input of the 4th phase inverter I4 of the 4th switch transistor T 4, the 5th switching tube
The outfan controlling end and the 3rd phase inverter I3 of T5 connects, control end, the control of the 6th switch transistor T 6 of the 5th switch transistor T 5
End, the control end controlling end and the 8th switch transistor T 8 of the 7th switch transistor T 7 are sequentially connected with, the outfan of the 5th switch transistor T 5
Being connected with the input of the 9th switch transistor T 9, the outfan of the 6th switch transistor T 6 and the input of the tenth switch transistor T 10 connect, the
The outfan of seven switch transistor T 7 and the input of the 11st switch transistor T 11 connect, the outfan and the 12nd of the 8th switch transistor T 8
The input of switch transistor T 12 connects, the outfan of the 9th switch transistor T 9, the outfan of the tenth switch transistor T 10, the 11st switching tube
The outfan of T11 and twelvemo close the equal ground connection of outfan of pipe T12, the control end of the 9th switch transistor T 9, the tenth switching tube
The control end controlling end, the control end of the 11st switch transistor T 11 and twelvemo pass pipe T12 of T10 receives outside control respectively
Signal processed.
9th switch transistor T the 9, the tenth switch transistor T the 10, the 11st switch transistor T 11 and twelvemo are closed pipe T12 and are received outside
Control signal, is on or shutoff situation, specifically, and in actual applications can be the most defeated by external harmoniousness control chip
Go out to control signal to the 9th switch transistor T the 9, the tenth switch transistor T the 10, the 11st switch transistor T 11 and twelvemo closes pipe T12.By
Have conducting in each switching tube and turn off two kinds of situations, then the first duty cycle control module 120 has 4*4=16 kind combination feelings
Condition controls switching tube (the 4th switch transistor T 4) drop-down driving force such that it is able to freely regulate the pulse of the first clock signal
Width.
As in figure 2 it is shown, wherein in an embodiment, the first clock signal generating device 100 also includes the first electric capacity C1,
One end of first electric capacity C1 is connected with the input of the 4th phase inverter I4, the other end ground connection of the first electric capacity C1.
First electric capacity C1 is the load used and then simulate matched line (match line), so that whole sequential control circuit energy
Enough more rationally, accurately realize sequencing contro.
Wherein in an embodiment, the second phase inverter I2 includes the odd number phase inverter monomer being sequentially connected in series.
In second phase inverter I2, the number of phase inverter monomer can affect the delay duration of the second phase inverter I2, i.e. changes second
In phase inverter I2, the number of phase inverter monomer can change control end and the 3rd switch transistor T 3 of signal arrival second switch pipe T2
The time difference controlled between end, the most just can change second switch pipe T2 and the duration of the 3rd of short duration conducting of switch transistor T 3, because of
This, (quantity is necessary based on actual application scenarios can to need rationally to select the quantity of phase inverter monomer in the second phase inverter I2
For odd number).Preferably, the second phase inverter I2 includes 3 phase inverter monomers, and so on the one hand second switch pipe T2 and the 3rd opens
The duration closing the of short duration conducting of pipe T3 can produce pulse that is complete and that caught by subsequent conditioning circuit, does not on the other hand result in sequential wave
Take.
As in figure 2 it is shown, wherein in an embodiment, second clock signal generating apparatus 200 includes the 13rd switching tube
T13, the 14th switch transistor T the 14, the 15th switch transistor T 15, sixteenmo close pipe T16, the 5th phase inverter I5, hex inverter
I6, the 7th phase inverter I7, the 8th phase inverter I8 and the 9th phase inverter I9；
Input and first clock signal generating device 100 of the 9th phase inverter I9 connect, the output of the 9th phase inverter I9
Holding the control end with the 14th switch to be connected, the input of the 13rd switch transistor T 13 connects external power source, the 13rd switching tube
The outfan of T13 and the input of the 14th switch transistor T 14 connect, the outfan of the 14th switch transistor T 14 and the 15th switch
The input of pipe T15 connects, the output head grounding of the 15th switch transistor T 15, the control end of the 13rd switch transistor T 13 and the 5th anti-
The outfan of phase device I5 connects, the 14th switch transistor T 14 control end respectively with the input and the 9th of hex inverter I6
The outfan of phase inverter I9 connects, and the outfan controlling end and hex inverter I6 of the 15th switch transistor T 15 connects, and the 7th is anti-
The input of phase device I7 is connected with outfan and the 14th switch transistor T 14 input of the 13rd switch transistor T 13 respectively, and the 7th
The outfan of phase inverter I7 is connected with control end and second duty cycle control module 220 of sixteenmo pass pipe T16 respectively, the
Sixteenmo close pipe T16 input connect external power source, sixteenmo close pipe T16 outfan respectively with the second Duty ratio control
The input of module 220 and the 8th phase inverter I8 connects, and the outfan of the 8th phase inverter I8 is raw with the 3rd clock signal respectively
The input becoming device 300 and the 5th phase inverter I5 connects.
The when that first clock signal rising edge coming, owing to the 9th phase inverter I9 exists, input is to the 14th switch transistor T 14
Signal is trailing edge, and when the first clock signal trailing edge comes when, owing to the 9th phase inverter I9 exists, input to the 14th is opened
The signal closed is rising edge.In simple terms, second clock signal generating apparatus 200 produces the mechanism and first of second clock signal
The mechanism that clock signal generating device 100 produces the first clock signal is identical, i.e. when the signal of input to the 14th switch transistor T 14
During for rising edge, owing to the control end of the 15th switch transistor T 15 has odd number reverser, the 14th switch transistor T 14 and the 15th
Switch transistor T 15 have of short duration while ON time, the node between the 13rd switch transistor T the 13 and the 14th switch transistor T 14
Current potential drags down, and second clock signal drawn high by three grades of phase inverters through below, then makes the 13rd to open through the 5th phase inverter I5
Close pipe T13 conducting, finally second clock signal is dragged down the pulse forming a self-loop.
As in figure 2 it is shown, wherein in an embodiment, the second duty cycle control module 220 includes the 17th switching tube
T17, eighteenmo close pipe T18, the 19th switch transistor T the 19, the 20th switch transistor T the 20, the 21st switch transistor T the 21, the 20th
Two switch transistor T the 22, the 23rd switch transistor T the 23 and the 24th switch transistor T 24；
The input of the 17th switch transistor T 17, eighteenmo close the input of pipe T18, the input of the 19th switch transistor T 19
The input of end and the 20th switch transistor T 20 is all connected with sixteenmo and closes the outfan of pipe T16 and the defeated of the 8th phase inverter I8
Entering end, the outfan controlling end and the 7th phase inverter I7 of the 17th switch transistor T 17 connects, the control of the 17th switch transistor T 17
End, eighteenmo close the control end of pipe T18, the control end of the 19th switch transistor T 19 and the control end of the 20th switch transistor T 20
Being sequentially connected with, the outfan of the 17th switch transistor T 17 and the input of the 21st switch transistor T 21 connect, and eighteenmo closes pipe
The outfan of T18 and the second twelvemo are closed the input of pipe T22 and are connected, the outfan and the 23rd of the 19th switch transistor T 19
The input of switch transistor T 23 connects, and the outfan of the 20th switch transistor T 20 and the input of the 24th switch transistor T 24 connect,
The outfan of the 21st switch transistor T 21, the second twelvemo close the outfan of pipe T22, the outfan of the 23rd switch transistor T 23
And the 24th equal ground connection of outfan of switch transistor T 24, the control end of the 21st switch transistor T 21, the second twelvemo close pipe
Outside the control end controlling end, the control end of the 23rd switch transistor T 23 and the 24th switch transistor T 24 of T22 receives respectively
Portion's control signal.
In simple terms, the second duty cycle control module 220 is identical with the structure of the first duty cycle control module 120, and i.e.
21 switch transistor T the 21, second twelvemos close pipe T22, the 23rd switch transistor T the 23 and the 24th switch transistor T 24 receives
External control signal, is on or shutoff situation, specifically, can be divided by external harmoniousness control chip in actual applications
Do not output control signals to the 21st switch transistor T the 21, second twelvemo and close pipe T22, the 23rd switch transistor T 23 and second
14 switch transistor T 24 (patch silicon chip).Owing to each switching tube has conducting and turns off two kinds of situations, then the second Duty ratio control mould
Block 220 have 4*4=16 kind combined situation to control switching tube (sixteenmo close pipe T16) drop-down driving force such that it is able to
Freely regulate the pulse width of second clock signal.
As in figure 2 it is shown, wherein in an embodiment, second clock signal generating apparatus 200 also includes the second electric capacity C2,
One end of second electric capacity C2 is connected with the input of the 8th phase inverter I8, the other end ground connection of the second electric capacity C2.
Second electric capacity C2 loads at bit line (bit line) for simulation, so that whole sequential control circuit can more close
Manage, accurately realize sequencing contro.
Wherein in an embodiment, hex inverter I6 includes the odd number phase inverter monomer being sequentially connected in series.
Hex inverter I6 and the second phase inverter I2 structure are similar, do not repeat them here.
As in figure 2 it is shown, wherein in an embodiment, the 3rd clock signal generating device 300 includes the tenth phase inverter
I10, the 11st phase inverter I11 and and logic module, the input of the tenth phase inverter I10 and second clock signal generating apparatus
200 connect, the outfan of the tenth phase inverter I10 respectively with the input of the 11st phase inverter I11 and with the of logic module
One input connects, and the outfan of the 11st phase inverter I11 is connected with the second input with logic module.
Can be and door to directly receive the tenth phase inverter I10 output with the first input end of logic module with logic module
Signal, the tenth phase inverter I10 output signal also after the 11st phase inverter I11 time delay input to logic module
Second input, owing to signal can produce time delay in the 11st phase inverter I11, with the first input end and second of logic module
It is poor to there is certain time in the time of input input signal, so produces burst pulse ripple with logic module.
Wherein in an embodiment, the 11st phase inverter I11 includes the odd number phase inverter monomer being sequentially connected with.
11st phase inverter I11 and the second phase inverter I2 and hex inverter I6 structure are similar to, and arrange phase inverter in it
Number can affect signal lag, eventually affect the pulse width of narrow-band impulse of the 3rd clock signal generating device 300 output
Degree.
For the technical scheme further explaining in detail sequential control circuit of the present invention and the effect brought thereof, below will be with
CAM RAM carries out sequencing contro, and the first clock signal is CMP_CLK, second clock signal is SAP_CLK, the 3rd clock letter
As a example by number being SA_CLK, and combine the oscillogram (Fig. 5) of Fig. 3, Fig. 4 and generation, be described in detail.
Rising as it is shown on figure 3, the sequential spent by CAM part is CMP_CLK, search line (search row) send
Enter CAM array (cam array), export ML (match line, matched line) more afterwards, then sample ML by SAP_CLK
Whether mate, if coupling starts to send WLpulse (word line pulse), open after BL or BLN (bit line) discharges into a certain degree
Open SA_CLK, sense amplifier (search amplifier) to start working reading data.The purpose of sequential control circuit of the present invention
It is exactly to allow these sequential time control more rationally, relatively reliable and higher operating rate.Clock control part is this
Bright key.
As shown in Figure 4, CMP_CLK in sequential control circuit of the present invention, SAP_CLK, SA_CLK in chronological sequence order is produced
Raw, CMP_CLK and SAP_CLK uses clock self-contr ol circuit, and CMP_CLK only has relation, to CLK with the rising edge of CLK
Dutycycle not requirement, the most only clock is risen and has the requirement of shake, be better than traditional high level with clock and control
Internal clocking processed.SAP_CLK directly utilizes the trailing edge of CMP_CLK and controls to produce, and the benefit so controlled is to work as CMP_CLK
Can and then produce SAP_CLK when end can be sampled, avoid extra sequential expense.SA_CLK is by the decline of SAP_CLK
The work of sense amplifier is controlled along one burst pulse of generation.
C_ml is the load of simulation match line, S0<3:0>can (in above-mentioned<3:0>, 0～3 refer to respectively with 16 kinds of combinations
The generation different pulse wavelength preset) control the drop-down driving force of switching tube such that it is able to freely regulate the pulse of CMP_CLK
Width.C_bl is the load of simulation bit line, S1<3:0>can there be 16 kinds of combinations to control the driving force that switching tube is drop-down
Such that it is able to convenient regulation SAP_CLK.Here it is emphasized that when CMP_CLK pulse adjust time, the sequential of SAP_CLK
Can automatically follow the pulse width of CMP_CLK to move, additionally SA_CLK is also the arteries and veins that can directly follow the tracks of CMP_CLK and SAP_CLK
Reconstitute joint and be automatically adjusted movement, thus facilitate the adjustment of sequential to reach purpose at a high speed.
The process of concrete pulses generation is such, the when that CLK rising edge coming, owing to the control end of N1 has three instead
To device, N0 Yu N1 have of short duration while ON time, the node potential between P0 and N0 is dragged down, anti-through three grades below
To device, CMP_CLK is drawn high, then turn on through a reverser P0, finally CMP_CLK is dragged down and form a self-loop
Pulse.Identical with CMP_CLK of mechanism that SAP_CLK produces.SA_CLK is through such as the group of Fig. 4 by the trailing edge of SAP_CLK
Logical produce.
Being illustrated in figure 5 the oscillogram that sequence circuit of the present invention produces, different clock is to have relation with previous,
Automatically being reacted to clock below up when previous clock changes when, this sequential Adjusted Option closely facilitates,
Do not result in the waste of extra sequential, as long as we adjust S0<3:0 on silicon chip>and S1<3:0>just can find one most suitable
Timing strategy make circuit can be operated in the fastest frequency, also there is rational allowance simultaneously.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed, but also
Can not therefore be construed as limiting the scope of the patent.It should be pointed out that, come for those of ordinary skill in the art
Saying, without departing from the inventive concept of the premise, it is also possible to make some deformation and improvement, these broadly fall into the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a sequential control circuit, it is characterised in that include the first clock signal generating device, the second clock being sequentially connected with
Signal generating apparatus and the 3rd clock signal generating device, described first clock signal generating device is built-in with the first dutycycle
Control module, described second clock signal generating apparatus is built-in with the second duty cycle control module；
Described first clock signal generating device receives the initial clock signal of outside input, when described initial clock signal enters
During rising edge, described first clock signal generating device triggers and generates the first clock signal, described first duty cycle control module
Controlling the dutycycle of the first clock signal, when described first clock signal enters trailing edge, described second clock signal generates
Device generates second clock signal, and described second duty cycle control module controls the dutycycle of described second clock signal, works as institute
When stating second clock signal entrance trailing edge, described 3rd clock signal generating device generates pulse clock signal.
Sequential control circuit the most according to claim 1, it is characterised in that described first clock signal generating device includes
First switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the first phase inverter, the second phase inverter, the 3rd phase inverter
And the 4th phase inverter；
The input of described first switching tube connects external power source, the outfan of described first switching tube and described second switch pipe
Input connect, the outfan of described second switch pipe is connected with the input of described 3rd switching tube, described 3rd switch
The output head grounding of pipe, the end that controls of described first switching tube is connected with the outfan of described first phase inverter, and described second opens
The end that controls closing pipe is connected with the input of described second phase inverter, and the control end reception of described second switch pipe is described initially
Clock signal, the end that controls of described 3rd switching tube is connected with the outfan of described second phase inverter, described 3rd phase inverter
Input input with the outfan of described first switching tube and described second switch pipe respectively is connected, described 3rd anti-phase
The outfan of device is connected with control end and described first duty cycle control module of described 4th switching tube respectively, and the described 4th
The input of switching tube connects external power source, the outfan of described 4th switching tube respectively with described first duty cycle control module
And the input of described 4th phase inverter connects, the outfan of described 4th phase inverter is raw with described second clock signal respectively
The input becoming device and described first phase inverter connects.
Sequential control circuit the most according to claim 2, it is characterised in that described first duty cycle control module includes
Five switching tubes, the 6th switching tube, the 7th switching tube, the 8th switching tube, the 9th switching tube, the tenth switching tube, the 11st switching tube
And twelvemo pass pipe；
The input of described 5th switching tube, the input of described 6th switching tube, the input of described 7th switching tube and
The input of described 8th switching tube all connects with the outfan of described 4th switching tube and the input of described 4th phase inverter
Connecing, the end that controls of described 5th switching tube is connected with the outfan of described 3rd phase inverter, the control end of described 5th switching tube,
The control end controlling end, the control end of described 7th switching tube and described 8th switching tube of described 6th switching tube connects successively
Connecing, the outfan of described 5th switching tube is connected with the input of described 9th switching tube, the outfan of described 6th switching tube
It is connected with the input of described tenth switching tube, the outfan of described 7th switching tube and the input of described 11st switching tube
Connecting, the input of the outfan of described 8th switching tube and described twelvemo pass pipe is connected, described 9th switching tube defeated
Go out end, the outfan of described tenth switching tube, the outfan of described 11st switching tube and described twelvemo and close the defeated of pipe
Go out to hold equal ground connection, the control end, the control of described 11st switching tube that control end, described tenth switching tube of described 9th switching tube
End processed and described twelvemo are closed the control end of pipe and are received external control signal respectively.
Sequential control circuit the most according to claim 2, it is characterised in that described first clock signal generating device also wraps
Including the first electric capacity, one end of described first electric capacity is connected with the input of described 4th phase inverter, another of described first electric capacity
End ground connection.
Sequential control circuit the most according to claim 2, it is characterised in that described second phase inverter includes being sequentially connected in series
Odd number phase inverter monomer.
Sequential control circuit the most according to claim 1, it is characterised in that described second clock signal generating apparatus includes
13rd switching tube, the 14th switching tube, the 15th switching tube, sixteenmo close pipe, the 5th phase inverter, hex inverter, the
Seven phase inverters, the 8th phase inverter and the 9th phase inverter；
The input of described 9th phase inverter is connected with described first clock signal generating device, the output of described 9th phase inverter
The control end with described 14th switch is held to be connected, the input connection external power source of described 13rd switching tube, the described tenth
The outfan of three switching tubes is connected with the input of described 14th switching tube, and the outfan of described 14th switching tube is with described
The input of the 15th switching tube connects, the output head grounding of described 15th switching tube, the control of described 13rd switching tube
End be connected with the outfan of described 5th phase inverter, described 14th switching tube control end respectively with described hex inverter
The outfan of input and described 9th phase inverter connects, the control end of described 15th switching tube and described hex inverter
Outfan connect, the input of described 7th phase inverter respectively with the outfan and the described tenth of described 13rd switching tube
The input of four switching tubes connects, the outfan of described 7th phase inverter close with described sixteenmo respectively pipe control end and
Described second duty cycle control module connects, and described sixteenmo closes the input of pipe and connects external power source, described sixteenmo
The outfan input with described second duty cycle control module and described 8th phase inverter respectively closing pipe is connected, and described the
The outfan of eight phase inverters input with described 3rd clock signal generating device and described 5th phase inverter respectively is connected.
Sequential control circuit the most according to claim 6, it is characterised in that described second duty cycle control module includes
17 switching tubes, eighteenmo close pipe, the 19th switching tube, the 20th switching tube, the 21st switching tube, the second twelvemo pass
Pipe, the 23rd switching tube and the 24th switching tube；
The input of described 17th switching tube, described eighteenmo close the input of pipe, the input of described 19th switching tube
The input of end and described 20th switching tube all with the described sixteenmo pass outfan of pipe and described 8th phase inverter
Input connects, and the end that controls of described 17th switching tube is connected with the outfan of described 7th phase inverter, and the described 17th opens
Close pipe controls end, control end, the control end and the described 20th of described 19th switching tube of described eighteenmo pass pipe
The control end of switching tube is sequentially connected with, and the outfan of described 17th switching tube connects with the input of described 21st switching tube
Connecing, the input of outfan and described second twelvemo pass pipe that described eighteenmo closes pipe is connected, described 19th switching tube
Outfan be connected with the input of described 23rd switching tube, the outfan and the described 20th of described 20th switching tube
The input of four switching tubes connects, and the outfan of described 21st switching tube, described second twelvemo close the outfan of pipe, institute
State outfan and the equal ground connection of outfan of described 24th switching tube of the 23rd switching tube, described 21st switch
The control end of pipe, described second twelvemo close control end, the control end and described second of described 23rd switching tube of pipe
The control end of 14 switching tubes receives external control signal respectively.
Sequential control circuit the most according to claim 6, it is characterised in that described second clock signal generating apparatus also wraps
Including the second electric capacity, one end of described second electric capacity is connected with the input of described 8th phase inverter, another of described second electric capacity
End ground connection.
Sequential control circuit the most according to claim 1, it is characterised in that described 3rd clock signal generating device includes
Tenth phase inverter, the 11st phase inverter and and logic module, the input of described tenth phase inverter and described second clock letter
Number generating means connects, the outfan of described tenth phase inverter respectively with the input of described 11st phase inverter and described with
The first input end of logic module connects, the outfan of described 11st phase inverter and described the second input with logic module
Connect.
Sequential control circuit the most according to claim 9, it is characterised in that described 11st phase inverter includes connecting successively
The odd number phase inverter monomer connect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610669404.9A CN106230404B (en) | 2016-08-12 | 2016-08-12 | Sequential control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610669404.9A CN106230404B (en) | 2016-08-12 | 2016-08-12 | Sequential control circuit |
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| Publication Number | Publication Date |
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| CN106230404A true CN106230404A (en) | 2016-12-14 |
| CN106230404B CN106230404B (en) | 2019-04-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610669404.9A Active CN106230404B (en) | 2016-08-12 | 2016-08-12 | Sequential control circuit |
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| Publication number | Publication date |
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| CN106230404B (en) | 2019-04-19 |
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