CN205899288U - Positive system is repaiied in time delay of data signal border - Google Patents
Positive system is repaiied in time delay of data signal border Download PDFInfo
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- CN205899288U CN205899288U CN201620077114.0U CN201620077114U CN205899288U CN 205899288 U CN205899288 U CN 205899288U CN 201620077114 U CN201620077114 U CN 201620077114U CN 205899288 U CN205899288 U CN 205899288U
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Abstract
The utility model discloses a positive system is repaiied in time delay of data signal border, the system is in the circuit of digital communication receiving terminal, pass through logic circuit, programmable logic device or software programming method, including rising edge collection module among messenger's receiving terminal main control chip, falling edge collection module, high frequency counter module, frame synchronising signal detection module, the module is revised in the time delay, thereby to the rising edge time delay and change revise of the inconsistent high level hold time who leads to of falling edge time delay with low level hold time that produces during through relaying or buffer circuit by digital communication in -process level signal. The utility model discloses can recovery system hardware to the level hold time distortion of digital signal transmission in -process, general in various digital level signal transmission occasion, the lowering system is to hardware transmission speed's requirement, and has reduced the hardware cost and the design degree of difficulty.
Description
Technical field
This utility model is related to digital processing field, particularly to a kind of digital signal edge time delay update the system.
Background technology
In digital signal communication, due to the ardware feature of isolation circuit or repeat circuit, level signal in communication process
The rising edge time delay phenomenon inconsistent with trailing edge time delay can be produced during by relaying or isolation circuit, so that signal high level is maintained
Time is held time with low level and changes, and then leads to distorted signals.
, typically can increase in base resistance two ends parallel connection speed-up capacitor in current industry taking Npn triode drive circuit as a example
Plus audion charging rate, accelerate rising edge speed；In the indirect diode of base stage and colelctor electrode, audion is made to cannot be introduced into satisfying
And area, thus accelerate trailing edge speed.
But the effect of this kind of method, it is confined to the correct selection of the capacitive reactance of speed-up capacitor and the impedance of resistance, and
It is only capable of improving time delay and cannot thoroughly repair it is impossible to solve signal frequency is higher, receiving terminal is to edge sensitive or to dutycycle
This kind of distortion occurring in sensitive application scenarios.And this kind of method is it is impossible to solve to exist for the design of audion physical characteristics
Non- triode device constitutes this kind of distortion occurring in isolation circuit or the application scenarios of repeat circuit.
Utility model content
The purpose of this utility model is to overcome the shortcoming of prior art and deficiency, provides one kind to be based on software programming technique
, do not increase hardware cost, digital signal edge time delay update the system.
The purpose of this utility model is achieved through the following technical solutions:
A kind of digital signal edge time delay update the system, including transmitting terminal main control chip, repeat circuit, receiving terminal master control core
Piece；
Defined in digital data transmission agreement between described receiving terminal main control chip and described transmitting terminal main control chip
One frame synchronization head comprising feature identification information and time delay correction.
Described receiving terminal main control chip includes:
Input signal rising edge acquisition module and input signal trailing edge acquisition module, gather the rising of input signal respectively
Edge and trailing edge, and it is sent to counter module；
Counter module, counts to the time interval between described signal edge, and count value is sent to frame synchronization
Signal detection module；
Frame synchronizing signal detection module, the described count value being specified according to described digital data transmission agreement and receiving,
Judge whether described frame synchronization head arrives, when described frame synchronization head characteristic information is detected, according to described digital data transmission
The time delay correction in frame synchronization head is extracted in the definition of agreement, and is sent to time delay correcting module；
Time delay correcting module, the described time delay correction according to receiving is modified to described input signal, makes signal
Rising edge and trailing edge time delay equal, make the waveform shape of revised signal and described transmitting terminal main control chip output letter
Number waveform shape consistent.
Described receiving terminal main control chip is PLD or single-chip microcomputer.
Described input signal rising edge acquisition module, input signal trailing edge acquisition module and counter module are high in frequency
System clock in frequency input signal twice drives lower work.
The described input signal rising edge acquisition module and input signal trailing edge acquisition module level shape to input signal
State is sensitive, judges when signal edge arrives by the change or maintenance of incoming signal level state.
It is that double counterses work independently inside described counter module, described double counterses distinguish the upper of corresponding digital signals
Rise edge and trailing edge work.
Described digital data transmission agreement, defines described frame synchronization head being spaced apart with level saltus step twice wherein comprising
The signal of 1.5 times of described digital signal bit period is as feature identification information.
Digital signal encoding described in described digital data transmission protocol definition is NRZ, i.e. the one of described digital signal
In bit period, signal saltus step represents 1, and signal is constant to represent 0；Define first bit period of described frame synchronization head, signal
Saltus step, is spaced 1.5 bit periods, second saltus step of signal, then is spaced 1 bit period, signal third time saltus step, then is spaced
1 bit period, the 4th saltus step of signal, then it is spaced 1.5 bit periods, and the 5th saltus step of signal, frame synchronization head terminates；Wherein,
The saltus step of two minor tick 1 bit period carries time delay correction.
Described time delay correcting module, is that n level cascade chronotron adds n circuit-switched data selector structure；Described time delay correcting module
In parameter n be the time delay size that should revise.
This utility model compared with prior art, has the advantage that and beneficial effect:
1st, this utility model reduces the complexity of design hardware, reduces the hardware to repeat circuit or isolation circuit
The requirement of transmission speed, as long as receiving terminal input signal has the above-mentioned rising edge time delay feature different from trailing edge time delay, all
This utility model institute extracting method can be applied to be modified, be common to various digital signal level transmission occasions, and this practicality is new
Type can automatic detection judge the size of difference and the symbol of rising edge and trailing edge time delay, thus that repairs that level holds time is abnormal
Become, make designer need not pay close attention to this details.
2nd, circuit digital signal maximum speed of the present utility model is applied to be limited to the high frequency clock of receiving terminal main control chip
Speed, and this high frequency clock speed determines receiving terminal data throughout, enables the maximum speed of whole system to reach master control core
The maximum speed that piece is supported, without being confined to isolation circuit or repeat circuit, solves in the system of high speed, transmission electricity
The restriction to system speed for the road.
Brief description
Fig. 1 is the structured flowchart of time delay update the system in digital signal edge described in the utility model.
Fig. 2 is the design principle figure of described system embodiment 1,2,3.
Fig. 3 is the frame synchronization head waveform diagram of described system embodiment 1,4.
Fig. 4 is the cascade time delay schematic diagram of chronotron in described system embodiment 1,2,3,4.
Fig. 5 is the frame synchronization head waveform diagram in described system embodiment 2.
Fig. 6 is the frame synchronization head waveform diagram in described system embodiment 3.
Fig. 7 is the design principle figure of described system embodiment 4.
Specific embodiment
With reference to embodiment and accompanying drawing, this utility model is described in further detail, but enforcement of the present utility model
Mode not limited to this.
Embodiment 1:
As shown in Fig. 2 the digital signal edge time delay update the system of the present embodiment, using fpga as receiving terminal master control core
Piece, fpga includes rising edge acquisition module, trailing edge acquisition module, enumerator a, timer b, frame synchronizing signal detection module,
Data selector, XOR gate, comparator, subtractor, chronotron.
This system adopts NRZ transmission data, and level change represents 1, and level is constant to represent 0, and system clock adopts
38.4mhz, signal frequency 4.8mhz (bit rate 9.6mbps), the pulse respective frequencies of 1.5 times of pulsewidths described in host-host protocol
3.2mhz (1/4.8mhz*1.5=1/3.2mhz).The frame synchronization head of data is by the half period (1/3.2mhz*1/ of a 3.2mhz
2*1000=156.25ns), the complete period (1/4.8mhz*1000=208.33ns) of a 4.8mhz, the half of a 3.2mhz
The special sequence of cycle composition, by the interval between equidirectional signal edge twice, receiving terminal identifies that the identity of synchronous head is special
Levy, by interval calculation correction size and the correction direction on edge between the signal edge of different directions.
So that first effective bit of synchronous head is as trailing edge as a example, as shown in figure 3, receiving terminal identifies the flow process of synchronous head
For: trailing edge interval 260.42ns (156.25+208.33/2=260.42) twice is first detected, then detect one
The rising edge of 208.33ns count value, finally detects the trailing edge being spaced 260.42ns away from last time trailing edge, completes synchronization.
Above-mentioned rising edge acquisition module receives repeat circuit or the signal of isolation circuit transmission, in the rising of system clock
Along sampling, it is height in signal level, a upper sampling period signal level is low sampling period output high level, other times are defeated
Go out low level；Trailing edge acquisition module receives repeat circuit or the signal of isolation circuit transmission, adopts in the rising edge of system clock
Sample, is low in signal level, and a upper sampling period signal level is high sampling period output high level, and other times output is low
Level, NRZ signal is changed into two pulse signals.
Enumerator a does plus a counting in the rising edge of system clock, resets in the rising edge of rising edge acquisition module output,
In the rising edge output momentary count value of trailing edge acquisition module output, that is, rising edge is to the time interval of trailing edge, to data
Selector；Enumerator b does plus a counting in the rising edge of system clock, resets in the rising edge of trailing edge acquisition module output,
In the rising edge output momentary count value of rising edge acquisition module output, that is, trailing edge is to the time interval of rising edge, to data
Selector.
After frame synchronizing signal detection module detects the special sequence of 3.2mhz, export to chronotron module and enable signal,
Start-up study device module；Simultaneously to data selector export selection signal, be 0 represent synchronous head end position be trailing edge, data select
Select the data of device gated counter b；Representing synchronous head end position for 1 is rising edge, the data of data selector gates enumerator a；
This selection signal exports to XOR gate simultaneously, in order to be modified the judgement in direction.
Comparator module compares the output valve of data selector and count value k corresponding to pulsewidth of 4.8mhz square-wave signal
Size, subtractor calculates data selector output valve and deducts the absolute value of k, k=38.6mhz/4.8mhz*1/ in the present embodiment
2-1=3；When receiving end signal input is undistorted, the time interval=trailing edge of rising edge to trailing edge to rising edge when
Between interval=1/4.8mhz=8*1/38.4mhz, now subtractor be output as 0, comparator is output as 0, and chronotron is not to reception
End input signal is revised；When receiving end signal rising edge time delay is not equal to trailing edge time delay, subtractor is output as the two and prolongs
When difference, rising edge time delay is more than trailing edge time delay, and synchronous head end position is when being trailing edge, comparator output 1, rising edge time delay
More than trailing edge time delay, and when synchronous head end position is rising edge, comparator output 0, trailing edge time delay is more than rising edge time delay, and
When synchronous head end position is rising edge, comparator output 1, trailing edge time delay is more than rising edge time delay, and synchronous head end position is to decline
Along when, comparator output 0.
Chronotron adopts the structure of trigger cascade, as shown in figure 4, setting the operation result of subtractor as m (0 < m < n), when
The enable of frame synchronizing signal detection module output effectively, and during XOR gate output 0, does m level to receiving terminal input signal trailing edge
Trigger time delay, during rising edge, all triggers put 1；And during XOR gate output 1, m level is done to receiving terminal input signal rising edge
Trigger time delay, all trigger resets during trailing edge；When enabling invalid, chronotron output 0.
Finally chronotron output waveform is transferred to Subordinate module, completes to revise.
Embodiment 2:
As shown in Fig. 2 the digital signal edge time delay update the system of the present embodiment, using fpga as receiving terminal master control core
Piece, fpga includes rising edge acquisition module, trailing edge acquisition module, enumerator a, timer b, frame synchronizing signal detection module,
Data selector, XOR gate, comparator, subtractor, chronotron.
This system adopts NRZ transmission data, and level change represents 1, and level is constant to represent 0, and system clock adopts
153.6mhz, signal frequency 4.8mhz (bit rate 9.6mbps), the pulse respective frequencies of 1.5 times of pulsewidths described in host-host protocol
3.2mhz (1/4.8mhz*1.5=1/3.2mhz).The frame synchronization head of data is by the half period (1/3.2mhz*1/ of a 3.2mhz
2*1000=156.25ns), the complete period (1/4.8mhz*1000=208.33ns) of a 4.8mhz, the half of a 3.2mhz
The special sequence of cycle composition, by the interval between equidirectional signal edge twice, receiving terminal identifies that the identity of synchronous head is special
Levy, by interval calculation correction size and the correction direction on edge between the signal edge of different directions.
So that first effective bit of synchronous head is as trailing edge as a example, as shown in figure 5, receiving terminal identifies the flow process of synchronous head
For: trailing edge interval 260.42ns (156.25+208.33/2=260.42) twice is first detected, then detect one
The rising edge of 208.33ns count value, finally detects the trailing edge being spaced 260.42ns away from last time trailing edge, completes synchronization.
Above-mentioned rising edge acquisition module receives repeat circuit or the signal of isolation circuit transmission, in the rising of system clock
Along sampling, it is height in signal level, a upper sampling period signal level is low sampling period output high level, other times are defeated
Go out low level；Trailing edge acquisition module receives repeat circuit or the signal of isolation circuit transmission, adopts in the rising edge of system clock
Sample, is low in signal level, and a upper sampling period signal level is high sampling period output high level, and other times output is low
Level, NRZ signal is changed into two pulse signals.
Enumerator a does plus a counting in the rising edge of system clock, resets in the rising edge of rising edge acquisition module output,
In the rising edge output momentary count value of trailing edge acquisition module output, that is, rising edge is to the time interval of trailing edge, to data
Selector；Enumerator b does plus a counting in the rising edge of system clock, resets in the rising edge of trailing edge acquisition module output,
In the rising edge output momentary count value of rising edge acquisition module output, that is, trailing edge is to the time interval of rising edge, to data
Selector.
After frame synchronizing signal detection module detects the special sequence of 3.2mhz, export to chronotron module and enable signal,
Start-up study device module；Simultaneously to data selector export selection signal, be 0 represent synchronous head end position be trailing edge, data select
Select the data of device gated counter b；Representing synchronous head end position for 1 is rising edge, the data of data selector gates enumerator a；
This selection signal exports to XOR gate simultaneously, in order to be modified the judgement in direction.
Comparator module compares the output valve of data selector and count value k corresponding to pulsewidth of 4.8mhz square-wave signal
Size, subtractor calculates data selector output valve and deducts the absolute value of k, k=153.6mhz/4.8mhz* in the present embodiment
1/2-1=15；When receiving end signal input is undistorted, the time interval=trailing edge of rising edge to trailing edge is to rising edge
Time interval=1/4.8mhz=32*1/153.6mhz, now subtractor be output as 0, comparator is output as 0, and chronotron is not right
Receiving terminal input signal is revised；When receiving end signal rising edge time delay is not equal to trailing edge time delay, subtractor is output as two
The difference of person's time delay, rising edge time delay is more than trailing edge time delay, and when synchronous head end position is trailing edge, comparator output 1, rising edge
Time delay is more than trailing edge time delay, and when synchronous head end position is rising edge, comparator output 0, trailing edge time delay is prolonged more than rising edge
When, and when synchronous head end position is rising edge, comparator output 1, trailing edge time delay is more than rising edge time delay, and synchronous head end position is
During trailing edge, comparator output 0.
Chronotron adopts the structure of trigger cascade, as shown in figure 4, setting the operation result of subtractor as m (0 < m < n), when
The enable of frame synchronizing signal detection module output effectively, and during XOR gate output 0, does m level to receiving terminal input signal trailing edge
Trigger time delay, during rising edge, all triggers put 1；And during XOR gate output 1, m level is done to receiving terminal input signal rising edge
Trigger time delay, all trigger resets during trailing edge；When enabling invalid, chronotron output 0.
Finally chronotron output waveform is transferred to Subordinate module, completes to revise.
Embodiment 3:
As shown in Fig. 2 the digital signal edge time delay update the system of the present embodiment, using fpga as receiving terminal master control core
Piece, fpga includes rising edge acquisition module, trailing edge acquisition module, enumerator a, timer b, frame synchronizing signal detection module,
Data selector, XOR gate, comparator, subtractor, chronotron.
This system adopts NRZ transmission data, and level change represents 1, and level is constant to represent 0, and system clock adopts
38.4mhz, signal frequency 4.8mhz (bit rate 9.6mbps), the pulse respective frequencies of 0.5 times of pulsewidth described in host-host protocol
9.6mhz (1/4.8mhz*0.5=1/9.6mhz).The frame synchronization head of data is by the half period (1/9.6mhz*1/ of a 9.6mhz
2*1000=52.08ns), the complete period (1/4.8mhz*1000=208.33ns) of a 4.8mhz, the half cycle of a 9.6mhz
The special sequence of phase composition, receiving terminal identifies the identity characteristic of synchronous head by the interval between equidirectional signal edge twice,
By interval calculation correction size and the correction direction on edge between the signal edge of different directions.
So that first effective bit of synchronous head is as trailing edge as a example, as shown in fig. 6, receiving terminal identifies the flow process of synchronous head
For: trailing edge interval 156.25ns (52.08+208.33/2=156.25) twice is first detected, then detect one
The rising edge of 208.33ns count value, finally detects the trailing edge being spaced 156.25ns away from last time trailing edge, completes synchronization.
Above-mentioned rising edge acquisition module receives repeat circuit or the signal of isolation circuit transmission, in the rising of system clock
Along sampling, it is height in signal level, a upper sampling period signal level is low sampling period output high level, other times are defeated
Go out low level；Trailing edge acquisition module receives repeat circuit or the signal of isolation circuit transmission, adopts in the rising edge of system clock
Sample, is low in signal level, and a upper sampling period signal level is high sampling period output high level, and other times output is low
Level, NRZ signal is changed into two pulse signals.
Enumerator a does plus a counting in the rising edge of system clock, resets in the rising edge of rising edge acquisition module output,
In the rising edge output momentary count value of trailing edge acquisition module output, that is, rising edge is to the time interval of trailing edge, to data
Selector；Enumerator b does plus a counting in the rising edge of system clock, resets in the rising edge of trailing edge acquisition module output,
In the rising edge output momentary count value of rising edge acquisition module output, that is, trailing edge is to the time interval of rising edge, to data
Selector.
After frame synchronizing signal detection module detects the special sequence of 9.6mhz, export to chronotron module and enable signal,
Start-up study device module；Simultaneously to data selector export selection signal, be 0 represent synchronous head end position be trailing edge, data select
Select the data of device gated counter b；Representing synchronous head end position for 1 is rising edge, the data of data selector gates enumerator a；
This selection signal exports to XOR gate simultaneously, in order to be modified the judgement in direction.
Comparator module compares the output valve of data selector and count value k corresponding to pulsewidth of 4.8mhz square-wave signal
Size, subtractor calculates data selector output valve and deducts the absolute value of k, k=38.6mhz/4.8mhz*1/ in the present embodiment
2-1=3；When receiving end signal input is undistorted, the time interval=trailing edge of rising edge to trailing edge to rising edge when
Between interval=1/4.8mhz=8*1/38.4mhz, now subtractor be output as 0, comparator is output as 0, and chronotron is not to reception
End input signal is revised；When receiving end signal rising edge time delay is not equal to trailing edge time delay, subtractor is output as the two and prolongs
When difference, rising edge time delay is more than trailing edge time delay, and synchronous head end position is when being trailing edge, comparator output 1, rising edge time delay
More than trailing edge time delay, and when synchronous head end position is rising edge, comparator output 0, trailing edge time delay is more than rising edge time delay, and
When synchronous head end position is rising edge, comparator output 1, trailing edge time delay is more than rising edge time delay, and synchronous head end position is to decline
Along when, comparator output 0.
Chronotron adopts the structure of trigger cascade, as shown in figure 4, setting the operation result of subtractor as m (0 < m < n), when
The enable of frame synchronizing signal detection module output effectively, and during XOR gate output 0, does m level to receiving terminal input signal trailing edge
Trigger time delay, during rising edge, all triggers put 1；And during XOR gate output 1, m level is done to receiving terminal input signal rising edge
Trigger time delay, all trigger resets during trailing edge；When enabling invalid, chronotron output 0.
Finally chronotron output waveform is transferred to Subordinate module, completes to revise.
Embodiment 4:
As shown in fig. 7, the digital signal edge time delay update the system of the present embodiment, using fpga as receiving terminal master control core
Piece, fpga includes rising edge acquisition module, trailing edge acquisition module, counter module, OR gate, trigger, adder, frame synchronization
Signal detection module, XOR gate, comparator, subtractor, chronotron.
This system adopts NRZ transmission data, and level change represents 1, and level is constant to represent 0, and system clock adopts
38.4mhz, signal frequency 4.8mhz (bit rate 9.6mbps), the pulse respective frequencies of 1.5 times of pulsewidths described in host-host protocol
3.2mhz (1/4.8mhz*1.5=1/3.2mhz).The frame synchronization head of data is by the half period (1/3.2mhz*1/ of a 3.2mhz
2*1000=156.25ns), the complete period (1/4.8mhz*1000=208.33ns) of a 4.8mhz, the half of a 3.2mhz
The special sequence of cycle composition, by the interval between equidirectional signal edge twice, receiving terminal identifies that the identity of synchronous head is special
Levy, by interval calculation correction size and the correction direction on edge between the signal edge of different directions.
So that first effective bit of synchronous head is as trailing edge as a example, as shown in figure 3, receiving terminal identifies the flow process of synchronous head
For: trailing edge interval 260.42ns (156.25+208.33/2=260.42) twice is first detected, then detect one
The rising edge of 208.33ns count value, finally detects the trailing edge being spaced 260.42ns away from last time trailing edge, completes synchronization.
Above-mentioned rising edge acquisition module receives repeat circuit or the signal of isolation circuit transmission, in the rising of system clock
Along sampling, it is height in signal level, a upper sampling period signal level is low sampling period output high level, other times are defeated
Go out low level；Trailing edge acquisition module receives repeat circuit or the signal of isolation circuit transmission, adopts in the rising edge of system clock
Sample, is low in signal level, and a upper sampling period signal level is high sampling period output high level, and other times output is low
Level, NRZ signal is changed into two pulse signals.
Above-mentioned counter module does plus a counting in the rising edge of system clock, adopts in rising edge acquisition module or trailing edge
Count value is latched into the outfan of this module by the rising edge of collection module output, and resets immediately；Above-mentioned trigger is in rising edge
Acquisition module or trailing edge acquisition module output rising edge triggering, with counter module cooperation, deposit a front count value with
Just calculate.
Adjacent count value twice is added by adder Module, and sends result to frame synchronizing signal detection module；Cause
Rising edge and trailing edge for digital signal are always alternately present, so, count value each time all represents different directions
Time interval between signal edge, and adjacent count value is added the time interval then representing between equidirectional signal edge.
Frame synchronizing signal detection module, according to equidirectional signal along time interval size detection to 3.2mhz special sequence
Row, export to chronotron module and enable signal, start-up study device module；One last position representing synchronous head of output is to rise simultaneously
Edge or the signal of trailing edge, in order to be modified the judgement in direction.
Comparator module compares the count value of flip/flops latch and count value k corresponding to pulsewidth of 4.8mhz square-wave signal
Size, the count value that subtractor calculates flip/flops latch deducts the absolute value of k, k=38.6mhz/4.8mhz* in the present embodiment
1/2-1=3；When receiving end signal input is undistorted, the time interval=trailing edge of rising edge to trailing edge is to rising edge
Time interval=1/4.8mhz=8*1/38.4mhz, now subtractor be output as 0, comparator is output as 0, and chronotron does not dock
Receiving end input signal is revised；When receiving end signal rising edge time delay is not equal to trailing edge time delay, subtractor is output as the two
The difference of time delay, rising edge time delay is more than trailing edge time delay, and when synchronous head end position is trailing edge, comparator output 1, rising edge prolongs
When be more than trailing edge time delay, and synchronous head end position is when being rising edge, comparator output 0, and trailing edge time delay is more than rising edge time delay,
And synchronous head end position is when being rising edge, comparator output 1, under trailing edge time delay is more than rising edge time delay, and synchronous head end position is
Fall along when, comparator output 0.
The relative size of known rising edge time delay and trailing edge time delay and synchronous head end position are rising edge or trailing edge
State, through XOR, you can obtain target and the size of time delay correction.
Chronotron adopts the structure of trigger cascade, as shown in figure 4, setting the operation result of subtractor as m (0 < m < n), when
The enable of frame synchronizing signal detection module output effectively, and during XOR gate output 0, does m level to receiving terminal input signal trailing edge
Trigger time delay, during rising edge, all triggers put 1；And during XOR gate output 1, m level is done to receiving terminal input signal rising edge
Trigger time delay, all trigger resets during trailing edge；When enabling invalid, chronotron output 0.
Finally chronotron output waveform is transferred to Subordinate module, completes to revise.
Above-described embodiment be this utility model preferably embodiment, but embodiment of the present utility model be not subject to above-mentioned
The restriction of embodiment, other any without departing from the change made under spirit of the present utility model and principle, modify, replace
Generation, combination, simplification, all should be equivalent substitute mode, are included within protection domain of the present utility model.
Claims (4)
1. a kind of digital signal edge time delay update the system, including the transmission terminal circuit, repeat circuit and the reception that are linked in sequence
Terminal circuit；Defined in the described digital data transmission agreement sending between terminal circuit and described receiving terminal circuit, one comprises spy
Levy the frame synchronization head of identification information and time delay correction it is characterised in that: described receiving terminal circuit includes: defeated for Real-time Collection
Enter the input signal edge acquisition module on signal edge, be used for the time interval between the described signal edge receiving is carried out
The counter module that counts, for judge whether to receive the frame synchronizing signal detection module of frame synchronization head and being used for revise defeated
Enter the time delay correcting module of signal, described input signal edge acquisition module, counter module, frame synchronizing signal detection module and
Time delay correcting module is linked in sequence, and described input signal edge acquisition module, counter module are also connected with time delay correcting module；
Described time delay correcting module includes n level delay circuit data selector, and every grade of delay circuit is all connected with data selector.
2. time delay update the system in digital signal edge according to claim 1 it is characterised in that: described receiving terminal circuit is
PLD or single-chip microcomputer.
3. time delay update the system in digital signal edge according to claim 1 it is characterised in that: described counter module is
Including the double counterses of enumerator a and enumerator b, described enumerator a and enumerator b works independently and is all connected to frame synchronization letter
Number detection module.
4. time delay update the system in digital signal edge according to claim 1 it is characterised in that: described every grade of delay circuit
Including comparator, subtractor, XOR gate and chronotron, described stronger and subtractor is connected with data selector, described comparison
Connected by XOR gate between device and chronotron, described subtractor is directly connected with chronotron.
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Cited By (2)
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| CN107943205A (en) * | 2017-12-15 | 2018-04-20 | 四川长虹电器股份有限公司 | DDR can calculate the circuit and method of clock cycle in comprehensive physical layer with delay chain |
| CN109932995A (en) * | 2017-12-18 | 2019-06-25 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107943205A (en) * | 2017-12-15 | 2018-04-20 | 四川长虹电器股份有限公司 | DDR can calculate the circuit and method of clock cycle in comprehensive physical layer with delay chain |
| CN107943205B (en) * | 2017-12-15 | 2020-12-29 | 四川长虹电器股份有限公司 | Circuit and method for calculating clock period by using delay chain in DDR (double data rate) comprehensive physical layer |
| CN109932995A (en) * | 2017-12-18 | 2019-06-25 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
| CN109932995B (en) * | 2017-12-18 | 2021-06-15 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
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