CN107943205A - DDR can calculate the circuit and method of clock cycle in comprehensive physical layer with delay chain - Google Patents
DDR can calculate the circuit and method of clock cycle in comprehensive physical layer with delay chain Download PDFInfo
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Abstract
The present invention relates to the technology that DDR can calculate the clock cycle in comprehensive physical layer with delay chain.The purpose of the present invention is can measure the automatic and high-precision clock cycle to input clock, to meet to measure the flexibility of clock under different process, the circuit and method of clock cycle can be calculated in comprehensive physical layer with delay chain by proposing a kind of DDR, its drip irrigation device is：First clock after the first clock phase detected register and second clock phase-detection register by obtaining the first output signal；Second clock after the 3rd clock phase detected register and the 4th clock phase detected register by obtaining the second output signal；The length of delay that master delay chain is set is adjusted, makes the rising edge of input clock and the rising edge alignment of second clock, the value for making the first output signal is 1, and the value of second clock signal is 0, at this time master delay chain and secondary delay chain locking input clock；The length of delay of master delay chain after adjustment and secondary delay chain reality is added to obtain the final clock cycle.
Description
Technical field
The present invention relates to delay chain survey clock cycle technology, more particularly to DDR can be in comprehensive physical layer with delay chain meter
Calculate the technology of clock cycle.
Background technology
Nowadays, memory species is varied, but double data rate (DDR) memory still occupies leading position, in order to handle
The up to data flow of 2Gb/s, the DDR physical layers of a stability and high efficiency are necessary.If DDR physical layers are the physics that can be integrated
Layer, then can be to bring huge flexibility for design, because component delays chain that can be important in comprehensive physical layer is with RTL
The form of code is present among design, this allows for delay circuit and can be used among the circuit of kinds of processes.DDR clocks
There are multiple clock frequencies such as 533Mhz, 667Mhz, 800Mhz, then delay chain can automatic measurement clock just become one
The problem of important.
The content of the invention
The object of the present invention is to provide circuit and the side that a kind of DDR can calculate the clock cycle in comprehensive physical layer with delay chain
Method, can measure the automatic and high-precision clock cycle to input clock, when being measured with satisfaction under different process
The flexibility of clock.
The present invention solves its technical problem, and the technical solution of use is：When DDR can be calculated in comprehensive physical layer with delay chain
The circuit in clock cycle, including input clock, it is characterised in that further include master delay chain, secondary delay chain, the detection of the first clock phase
Register, second clock phase-detection register, the 3rd clock phase detected register and the 4th clock phase detected register,
Clock end of the input clock respectively with first to fourth clock phase detected register is connected, input clock and master delay chain
Input terminal connection, the output terminal of master delay chain is connected with the input terminal of pair delay chain, the output terminal of secondary delay chain and when the 3rd
The signal end connection of clock phase-detection register, the output terminal of the 3rd clock phase detected register and the 4th clock phase detect
The signal end connection of register, the signal of the output terminal of the 4th clock phase detected register export signal, master delay for second
The output terminal of chain is connected with the signal end of the first clock phase detected register, the output terminal of the first clock phase detected register
It is connected with the signal end of second clock phase-detection register, the output signal of the output terminal of second clock phase-detection register
For the first output signal.
Specifically, the length of delay that the master delay chain is set at least covers the half period of input clock.
Further, the master delay chain includes 128 grades of delay devices.
Specifically, the input clock is minimum clock skew.
Yet further, the length of delay that the secondary delay chain is set is at least across the clock of input clock along metastable state.
Specifically, the secondary delay chain includes 8 grades of delay devices.
The method that DDR can calculate the clock cycle in comprehensive physical layer with delay chain, can use applied to DDR in comprehensive physical layer
Delay chain calculates the circuit of clock cycle, it is characterised in that comprises the following steps：
Step 1, input clock after master delay chain by obtaining the first clock；
Step 2, the first clock after secondary delay chain by obtaining second clock；
Step 3, the first clock after the first clock phase detected register and second clock phase-detection register by obtaining
To the first output signal；
Step 4, second clock after the 3rd clock phase detected register and the 4th clock phase detected register by obtaining
To the second output signal；
The length of delay that step 5, adjustment master delay chain are set, makes the rising edge of input clock and the rising edge pair of second clock
Together, so that the value of the first output signal is 1, the value of second clock signal is 0, and master delay chain and secondary delay chain locking are defeated at this time
Enter clock；
Step 6, with the length of delay of secondary delay chain reality be added the length of delay of master delay chain reality after adjustment to obtain finally
Clock cycle.
Specifically, in rapid 1, the master delay chain includes 128 grades of delay devices.
Further, in step 2, the pair delay chain includes 8 grades of delay devices.
Specifically, in step 5, if the length of delay that length of delay and secondary delay chain that master delay chain is set are set covers enough
Whole cycle, then master delay chain is in complete period pattern, at this time the reality of the length of delay of master delay chain reality and secondary delay chain
Length of delay and be exactly input clock whole cycle；If the frequency of input clock is low to the delay for setting master delay chain
The length of delay that value and secondary delay chain are set cannot cover whole cycle, cause the first output signal and the second output signal not to expire
The value that foot first exports signal is 1, and the value of the second output signal is 0, and at this time, master delay chain can be automatically switched to half period mould
Formula, in such a mode, master delay chain lock input clock when second clock reaches the half period of input clock, and master prolongs at this time
The length of delay of slow chain reality and pair delay chain actual length of delay and 2 times be exactly input clock whole cycle；If
The length of delay that the low length of delay set to master delay chain of clock frequency and secondary delay chain are set can not sample half period, then will be main
Delay chain set length of delay be adjusted to maximum, this pattern is called saturation mode, in this case input clock speed compared with
Slowly, other delay chains can just measure the cycle of input clock according to default setting.
The invention has the advantages that the electricity of clock cycle can be calculated in comprehensive physical layer with delay chain by above-mentioned DDR
Road and method, can adapt to the input clock of various frequencies automatically, improve DDR can comprehensive physical layer flexibility, measure at the same time
The circuit of clock can be used among the circuit of kinds of processes.
Brief description of the drawings
Fig. 1 is that DDR of the present invention can be in comprehensive physical layer with the circuit structure diagram of delay chain calculating clock cycle.
Wherein, DLM is main delay chain, and DLR is secondary delay chain, and FF1-0 is the first clock phase detected register, FF1-1
For second clock phase-detection register, FF2-0 is the 3rd clock phase detected register, and FF2-1 examines for the 4th clock phase
Register is surveyed, IN1 is the input terminal of main delay chain, and OUT1 is the output terminal of main delay chain, and IN2 is the input terminal of secondary delay chain,
OUT2 is the output terminal of secondary delay chain, and D1 is the signal end of the first clock phase detected register, and Q1 examines for the first clock phase
The output terminal of register is surveyed, CLK1 is the clock end of the first clock phase detected register, and D2 posts for second clock phase-detection
The signal end of storage, Q2 are the output terminal of second clock phase-detection register, and CLK2 is second clock phase-detection register
Clock end, D3 be the 3rd clock phase detected register signal end, Q3 be the 3rd clock phase detected register output
End, CLK3 be the 3rd clock phase detected register clock end, D4 be the 4th clock phase detected register signal end, Q4
For the output terminal of the 4th clock phase detected register, CLK4 is the clock end of the 4th clock phase detected register.
Embodiment
With reference to the accompanying drawings and embodiments, detailed description of the present invention technical solution.
DDR of the present invention can be prolonged in comprehensive physical layer with the circuit of delay chain calculating clock cycle by input clock, master
Slow chain, secondary delay chain, the first clock phase detected register, second clock phase-detection register, the detection of the 3rd clock phase
Register and the 4th clock phase detected register composition, its circuit structure diagram referring to Fig. 1, wherein, input clock is respectively with the
The clock end connection of one to the 4th clock phase detected register, input clock are connected with the input terminal of master delay chain, master delay
The output terminal of chain is connected with the input terminal of secondary delay chain, the letter of the output terminal of secondary delay chain and the 3rd clock phase detected register
Number end connection, the output terminal of the 3rd clock phase detected register is connected with the signal end of the 4th clock phase detected register,
The signal of the output terminal of 4th clock phase detected register is the second output signal, the output terminal of master delay chain and the first clock
The signal end connection of phase-detection register, output terminal and the second clock phase-detection of the first clock phase detected register are posted
The signal end connection of storage, the output signal of the output terminal of second clock phase-detection register is the first output signal.
The method that DDR can calculate the clock cycle in comprehensive physical layer with delay chain, can use applied to DDR in comprehensive physical layer
Delay chain calculates the circuit of clock cycle, comprises the steps of：
Step 1, input clock after master delay chain by obtaining the first clock；
Step 2, the first clock after secondary delay chain by obtaining second clock；
Step 3, the first clock after the first clock phase detected register and second clock phase-detection register by obtaining
To the first output signal；
Step 4, second clock after the 3rd clock phase detected register and the 4th clock phase detected register by obtaining
To the second output signal；
The length of delay that step 5, adjustment master delay chain are set, makes the rising edge of input clock and the rising edge pair of second clock
Together, so that the value of the first output signal is 1, the value of second clock signal is 0, and master delay chain and secondary delay chain locking are defeated at this time
Enter clock；
Step 6, with the length of delay of secondary delay chain reality be added the length of delay of master delay chain reality after adjustment to obtain finally
Clock cycle.
Embodiment
DDR of the embodiment of the present invention can calculate the circuit of clock cycle in comprehensive physical layer with delay chain, including input clock,
Master delay chain, secondary delay chain, the first clock phase detected register, second clock phase-detection register, the 3rd clock phase
Detected register and the 4th clock phase detected register, wherein, input clock is detected with first to fourth clock phase respectively
The clock end connection of register, input clock are connected with the input terminal of master delay chain, the output terminal of master delay chain and secondary delay chain
Input terminal connection, the output terminal of secondary delay chain is connected with the signal end of the 3rd clock phase detected register, the 3rd clock phase
The output terminal of position detected register is connected with the signal end of the 4th clock phase detected register, the detection deposit of the 4th clock phase
The signal of the output terminal of device is the signal of the second output signal, the output terminal of master delay chain and the first clock phase detected register
End connection, the output terminal of the first clock phase detected register are connected with the signal end of second clock phase-detection register, the
The output signal of the output terminal of two clock phase detected registers is the first output signal.
In foregoing circuit, the length of delay that master delay chain is set at least covers the half period of input clock；Master delay chain is excellent
Selection of land include can 128 grades of delay devices, can according to be actually needed freely set；Input clock is minimum clock skew；It is secondary
The length of delay that delay chain is set at least across input clock clock along metastable state；Secondary delay chain preferably may include 8 grades of delays
Device, can also freely set according to being actually needed.
The method that DDR can calculate the clock cycle in comprehensive physical layer with delay chain, can use applied to DDR in comprehensive physical layer
Delay chain calculates the circuit of clock cycle, comprises the following steps：
Step 1, input clock after master delay chain by obtaining the first clock, it is preferable that master delay chain may include that 128 grades are prolonged
Slow device；
Step 2, the first clock after secondary delay chain by obtaining second clock, it is preferable that secondary delay chain may include 8 grades of delays
Device；
Step 3, the first clock after the first clock phase detected register and second clock phase-detection register by obtaining
To the first output signal；
Step 4, second clock after the 3rd clock phase detected register and the 4th clock phase detected register by obtaining
To the second output signal；
The length of delay that step 5, adjustment master delay chain are set, makes the rising edge of input clock and the rising edge pair of second clock
Together, so that the value of the first output signal is 1, the value of second clock signal is 0, and master delay chain and secondary delay chain locking are defeated at this time
Enter clock；
Step 6, with the length of delay of secondary delay chain reality be added the length of delay of master delay chain reality after adjustment to obtain finally
Clock cycle.
In the above method, in step 5, if the length of delay that length of delay and secondary delay chain that master delay chain is set are set is enough
Cover whole cycle, then master delay chain is in complete period pattern, at this time the length of delay of master delay chain reality and secondary delay chain
Whole cycle that is actual length of delay and being exactly input clock；If the frequency of input clock it is low to make master delay chain set
The length of delay that length of delay and secondary delay chain are set cannot cover whole cycle, cause the first output signal and second export signal without
Method meets that the value of the first output signal is 1, and the value of the second output signal is 0, and at this time, master delay chain can be automatically switched to the half period
Pattern, in such a mode, master delay chain lock input clock when second clock reaches the half period of input clock, lead at this time
The length of delay of delay chain reality and secondary delay chain actual length of delay and 2 times be exactly input clock whole cycle；Such as
The length of delay that the low length of delay set to master delay chain of fruit clock frequency and secondary delay chain are set can not sample half period, then will
The length of delay that master delay chain is set is adjusted to maximum, and this pattern is called saturation mode, in this case input clock speed
Relatively slow, other delay chains can just measure the cycle of input clock according to default setting.
Claims (10)
1.DDR can calculate the circuit of clock cycle, including input clock in comprehensive physical layer with delay chain, it is characterised in that also
Including master delay chain, secondary delay chain, the first clock phase detected register, second clock phase-detection register, the 3rd clock
Phase-detection register and the 4th clock phase detected register, the input clock are examined with first to fourth clock phase respectively
The clock end connection of register is surveyed, input clock is connected with the input terminal of master delay chain, and the output terminal of master delay chain postpones with secondary
The input terminal connection of chain, the output terminal of secondary delay chain are connected with the signal end of the 3rd clock phase detected register, the 3rd clock
The output terminal of phase-detection register is connected with the signal end of the 4th clock phase detected register, and the detection of the 4th clock phase is posted
The signal of the output terminal of storage is the letter of the second output signal, the output terminal of master delay chain and the first clock phase detected register
Number end connection, the output terminal of the first clock phase detected register is connected with the signal end of second clock phase-detection register,
The output signal of the output terminal of second clock phase-detection register is the first output signal.
2. DDR according to claim 1 can calculate the circuit of clock cycle in comprehensive physical layer with delay chain, its feature exists
In the length of delay that the master delay chain is set at least covers the half period of input clock.
3. DDR according to claim 2 can calculate the circuit of clock cycle in comprehensive physical layer with delay chain, its feature exists
In the master delay chain includes 128 grades of delay devices.
4. DDR according to claim 1 can calculate the circuit of clock cycle in comprehensive physical layer with delay chain, its feature exists
In the input clock is minimum clock skew.
5. DDR according to claim 1 can calculate the circuit of clock cycle in comprehensive physical layer with delay chain, its feature exists
In, the length of delay that the pair delay chain is set at least across input clock clock along metastable state.
6. DDR according to claim 5 can calculate the circuit of clock cycle in comprehensive physical layer with delay chain, its feature exists
In the pair delay chain includes 8 grades of delay devices.
The method that 7.DDR can calculate the clock cycle in comprehensive physical layer with delay chain, applied to claim 1-6 any one institute
The DDR stated can calculate the circuit of clock cycle in comprehensive physical layer with delay chain, it is characterised in that comprise the following steps：
Step 1, input clock after master delay chain by obtaining the first clock；
Step 2, the first clock after secondary delay chain by obtaining second clock；
Step 3, the first clock are by obtaining after the first clock phase detected register and second clock phase-detection register
One output signal；
Step 4, second clock are by obtaining after the 3rd clock phase detected register and the 4th clock phase detected register
Two output signals；
The length of delay that step 5, adjustment master delay chain are set, makes the rising edge of input clock and the rising edge alignment of second clock,
So that the value of the first output signal is 1, the value of second clock signal is 0, at this time master delay chain and secondary delay chain locking input
Clock；
Step 6, when the length of delay of master delay chain reality after adjustment being added with the length of delay of secondary delay chain reality obtain final
The clock cycle.
8. the method that DDR according to claim 7 can calculate the clock cycle in comprehensive physical layer with delay chain, its feature exist
In in step 1, the master delay chain includes 128 grades of delay devices.
9. the method that DDR according to claim 7 can calculate the clock cycle in comprehensive physical layer with delay chain, its feature exist
In in step 2, the pair delay chain includes 8 grades of delay devices.
10. the method that DDR according to claim 7 can calculate the clock cycle in comprehensive physical layer with delay chain, its feature
It is, in step 5, if the length of delay that length of delay and secondary delay chain that master delay chain is set are set covers whole cycle enough,
So master delay chain is in complete period pattern, at this time the length of delay of master delay chain reality and the actual length of delay of secondary delay chain
It is exactly the whole cycle of input clock；Postpone if the frequency of input clock is low to the length of delay for setting master delay chain and pair
The length of delay that chain is set cannot cover whole cycle, cause the first output signal and the second output signal can not meet the first output
The value of signal is 1, and the value of the second output signal is 0, and at this time, master delay chain can be automatically switched to half cycle mode, in this pattern
Under, master delay chain locks input clock when second clock reaches the half period of input clock, and master delay chain is actual at this time
Length of delay and secondary delay chain actual length of delay and 2 times be exactly input clock whole cycle；If clock frequency is low
The length of delay that the length of delay and secondary delay chain set to master delay chain is set can not sample half period, then set master delay chain
Length of delay be adjusted to maximum, this pattern is called saturation mode, and input clock speed is slower in this case, other delay
Chain can just measure the cycle of input clock according to default setting.
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