KR100911895B1 - Register controled delay locked loop circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register controlled delay locked loop (DLL) capable of performing a stable delay operation. The present invention relates to a normal mode for performing delay shifting operations in units of delay units, and a delay group, including a plurality of delay units. A register-controlled delay locked loop that supports a fast mode for performing a delay shifting operation, comprising: a phase comparator for comparing phases of a source clock and a feedback clock, and sequentially activating a delay shifting update period in response to the source clock; A control pulse generator for generating a first timing pulse, a second timing pulse, and a third timing pulse; and a mode control unit for generating a mode control signal according to a comparison result of the phase comparator in response to the first timing pulse. And the normal mode in response to the second timing pulse and the mode control signal. A delay shift controller for outputting a normal mode delay shift control signal for controlling an operation, and outputting a fast mode delay shift control signal for controlling the fast mode operation in response to the third timing pulse and the mode control signal; A phase delay unit for delay shifting the phase of the internal clock in units of a delay unit in response to a mode delay shift control signal, and delay shifting the phase of the internal clock in units of a delay group in response to the fast mode delay shift control signal; and A register controlled delay locked loop (DLL) is provided having a delay replication model unit for receiving an output signal of a phase delay unit and outputting the output signal as the feedback clock by reflecting an actual delay condition of the internal clock path.

Register-controlled delay locked loop circuit, fast mode, normal mode

Description

Register-controlled delay locked loop circuit {REGISTER CONTROLED DELAY LOCKED LOOP CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor designs, and more particularly, to a delay locked loop circuit (DLL), and more particularly, to a register controlled delay locked loop circuit (DLL) capable of performing a stable delay operation. will be.

Synchronous semiconductor memory devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) transfer data with external devices using an internal clock synchronized with an external clock input from an external device such as a memory controller (CTRL).

This is because the temporal synchronization between the external clock and the data output from the memory is very important to the stable data transfer between the memory and the memory controller.

At this time, the data output from the memory is output in synchronization with the internal clock. When the internal clock is initially applied to the memory, the internal clock is applied in synchronization with the external clock. When it is output, it is output out of sync with external clock.

Therefore, for stable transmission of data output from the memory, the delayed internal clock is accurately positioned at the edge or center of the external clock applied by the memory controller while passing through each component in the memory transmitting the data. The risk is to compensate the internal clock time with the internal clock so that the internal and external clocks are synchronized.

Clock synchronizing circuits that perform this role include a phase locked loop (PLL) circuit and a delay locked loop circuit (DLL) circuit.

Of these, when the frequency of the external clock and the internal clock are different from each other, the frequency lock function should be used. Therefore, a phase locked loop (PLL) is used. However, when the frequency of the external clock is the same as the frequency of the internal clock, a delayed fixed loop circuit (DLL) that can be implemented in a relatively small area is mainly used compared to the phase locked loop (PLL).

That is, in the case of the semiconductor memory device, since the frequency used is the same, the delay locked loop circuit DLL is mainly used as the clock synchronization circuit.

Among them, the semiconductor memory device has a register for storing a fixed delay value, and when the power is turned off, the fixed delay value is stored in the register, and when the power is applied again, the internal clock is fixed by loading the fixed delay value stored in the register. In this case, the clock synchronization operation can be performed when the phase difference between the internal clock and the external clock is relatively small during the initial operation of the semiconductor memory device, and the delay of the register according to the phase difference between the internal clock and the external clock even after the initial operation. Register controlled delayed loop (Register Controlled DLL) circuits are most widely used to reduce the time it takes for the internal and external clocks to synchronize by varying the range of fluctuation.

1 is a block diagram showing a register controlled delay locked loop circuit (DLL) according to the prior art.

Referring to FIG. 1, a block diagram showing a register controlled delay locked loop circuit (DLL) according to the prior art has the following configuration.

First, the register-controlled delay locked loop circuit (DLL) according to the related art shown in FIG. 1 includes a normal mode for performing delay shifting operations in units of delay units, and a delay group including a plurality of delay units. It is a register controlled delay locked loop (DLL) that supports fast mode to perform an operation.

The configuration is described on the premise of this. The phase comparators 100R and 100F for comparing the phases of the source clocks refclk and the feedback clocks fbclkr and fbclkf, and the control clocks synchronized with the source clocks refclk contclk The control pulse generator 110 for generating the first timing pulse PULSE_2 and the second timing pulse PULSE_3 sequentially activated at each delay shifting update period, and the first timing pulse PULSE_2. Mode control signals 120R and 120F for generating mode control signals FM_END, lock_state, FM_END_F, and lock_statef according to the comparison results (fine, coarse, FM_pdout, finef, coarsef, and FM_pdoutf) of the phase comparator. Normal mode delay shift control signals (frclk_sl, ffclk_sl) and fast mode operation for controlling the normal mode operation in response to the fast mode control signals FM_END, FM_ENDF among the PULSE_3 and the mode control signals FM_END, lock_state, FM_END_F, and lock_statef. Article The delay shift control units 130R and 130F for outputting the fast mode delay shift control signals fastr_sl and fastf_sl, and the source clock refclk and the control clock in response to the normal mode delay shift control signals frclk_sl and ffclk_sl. Delay shifts the phases of the internal clocks (clkin1 and clkin2) in synchronization with the delay unit, and delays the phases of the internal clocks (clkin1 and clkin2) in units of delay groups in response to the fast mode delay shift control signals (fastr_sl and fastf_sl). The shifted phase delay units 140R and 140F and the output clocks mixout_r and mixout_f of the phase delay units 140R and 140F are input and output as feedback clocks fbclkr and fbclkf reflecting actual delay conditions of the internal clock path. Delay replica model units 150R and 150F.

In addition, the clock buffer unit 180B and the clock enable signal for buffering the external clock CLK to generate a source clock refclk, a control clock contclk, and an internal clock clkin1 and clkin2 whose phases are synchronized. The clock buffer unit in response to a signal containing power inversion mode (ckeb_com) and a power down mode information of a mode register set (MRS) and a signal containing precharge information The power down mode control unit 180A for controlling the operation of the 180B, the delayed fixed loop circuit DLL reset signal dll_resetb, and the delayed locked loop DLL deactivation signal dis_dll input from the outside of the semiconductor memory device. In response to the delay locked loop (DLL) control unit 190 for generating a reset signal (reset) for controlling the operation of the delay locked loop circuit (DLL), and the output clocks (mixout_r, mixout_f) of the phase delay units (140R, 140F). Invert the phase of either (mixout_r or mixout_f) mixout_f) to output the rising inner clock rising_clk corresponding to the rising edge of the external clock CLK and the falling inner clock falling_clk corresponding to the falling edge of the external clock CLK. The pre-duty compensator 160A for outputting the duty ratio, the duty compensator 160B for correcting the duty ratio of the output clocks (rising_clk, falling_clk) of the pre-duty compensator 160A in the locked state, and the duty A delay locked loop circuit (DLL) driver 170 for outputting the delay locked loop output clocks (irclkdll and ifclkdll) driving the output clocks ifbclkr and ifbclkf of the correction unit 160B to the output driver of the semiconductor memory device is further provided. Equipped.

At this time, the battery duty correction unit 160A and the duty correction unit 160B exist between the phase delay units 140R and 140F and the delayed replication model units 150R and 150F, so that the battery duty correction unit 160A has a phase delay. Output clocks (mixout_r, mixout_f) of the units 140R and 140F are output as rising internal clocks (rising_clk) and falling internal clocks (falling_clk) with different names, and the duty compensation unit 160B is again connected with the rising internal clocks (rising_clk). In spite of receiving the falling internal clock (falling_clk) and outputting it as clocks of other names (ifbclkr, ifbclkf), in the above-described configuration, the output clocks (mixout_r, mixout_f) of the phase delay units 140R and 140F are delayed replication model units. It has been described that 150R and 150F are input and output feedback clocks fbclkr and fbclkf. That is, the battery duty correction unit 160A and the duty correction unit 160B are described as if there is no reason. The part you want to trouble with It is because one will, more reason will be described while describing the invention part.

The operation thereof will be described based on the configuration of the register-controlled delayed fixed loop circuit DLL according to the related art described above.

First, the above-described register controlled delay locked loop (DLL) has a duty ratio of 50 to 50 of the clock outputted through the dual-loop (DLL) delay driver (170) driver 170. In order to ensure that the rising edge is determined corresponding to the rising edge of the rising clock of the outer clock CLK and the rising edge of the rising inner clock CLK and the falling edge of the outer clock CLK, the rising edge is determined. The method of using the falling internal clock (falling_clk), or the delay locked loop circuit (DLL) using the single-loop method using only the clock corresponding to the rising edge of the external clock (CLK). The operation is similar to that of a register controlled delay locked loop (DLL) using a general dual loop.

That is, the mode control units 120R and 120F, the phase comparators 100R and 100F, the delay shift control units 130R and 130F, the phase delay units 140R and 140F, and the delay replication model units 150R and 150F have the same circuit configuration. Blocks 100R, 120R, 130R, 140R, 150R for adjusting the phase of the rising inner clock (rising_clk) and blocks 100F, 120F, 130F, 140F, for adjusting the phase of the falling inner clock (falling_clk); 150F).

Here, the blocks 100R, 120R, 130R, 140R, and 150R for adjusting the phase of the rising internal clock (rising_clk) may have a rising edge of the rising internal clock (rising_clk) and a rising edge of the source clock (refclk) even before the locked state. Adjust the phase of the rising internal clock (rising_clk) to be synchronized, and adjust the phase of the rising internal clock (rising_clk) so that the rising edge of the rising internal clock (rising_clk) and the rising edge of the source clock (refclk) are synchronized even after the locked state. The reason for this is to make the locking state before the locking state and to compensate for the variation of the phase of the rising clock (rising_clk) after the locking state due to the fluctuation of the power supply voltage or noise applied from the outside of the semiconductor memory device.

Also, the blocks 100F, 120F, 130F, 140F, and 150F for adjusting the phase of the falling internal clock fall_clk have a rising edge of the falling internal clock falling_clk and a rising edge of the source clock refclk before the locked state. Adjusts the phase of the falling internal clock (falling_clk) to be synchronized, but only some (130F, 140F) operate after the locked state and do not operate the rest (100F, 120F, 150F) after locking, to create a locked state before the locked state. After the locked state, since the duty is corrected by the duty compensator 160B and the phase of the falling internal clock falling_clk is changed, the output of the delayed fixed loop (DLL) driver 170 is changed. Does not affect.

For reference, in the general dual-loop register controlled delay locked loop (DLL), the locked state includes both the rising edge of the source clock (refclk) and the rising internal clock (rising_clk) and the rising edge of the falling internal clock (falling_clk). This means a synchronized state-within a certain margin of error.

FIG. 2 is a circuit diagram illustrating in detail a delay shift control unit among the components of a register controlled delay locked loop (DLL) according to the related art shown in FIG.

For reference, in the delay shift controllers 130R and 130F, the block 130R for the rising internal clock (rising_clk) and the block 130F for the falling internal clock (falling_clk) have the same configuration. Only block 130R for rising_clk) is shown.

Referring to FIG. 2, the delay shift control units 130R and 130F of the components of the register-controlled delayed fixed loop circuit DLL according to the related art are the second timing pulse PULSE_3 output from the control pulse generator 100. In response to the normal mode delay shift control signal generators 132R and 132F for generating a normal mode delay shift control signal frclk_sl in response to the normal mode operation, and a second timing output from the control pulse generator 100. The fast mode delay shift control signal generators 134R and 134F are configured to generate the fast mode delay shift control signal fast_sl for controlling the fast mode operation in response to the pulse PULSE_3.

Here, the normal mode delay shift control signal generators 132R and 132F receive the fast mode control signals FM_END and FM_ENDF among the second timing pulses PULSE_3 and the mode control signals FM_END, lock_state, FM_END_F, and lock_statef. And an inverter INV2 for receiving an output NAND gate NAND1 and an output signal of the NAND gate NAND1 and outputting the output signal as a normal mode delay shift control signal frclk_sl.

The fast mode delay shift control signal generators 134R and 134F receive and output the fast mode control signals FM_END and FM_ENDF among the mode control signals FM_END, lock_state, FM_END_F, and lock_statef. And a NAND gate NAND2 that receives an output signal of the second timing pulse PULSE_3 and the first inverter INV1 and an output signal of the NAND gate NAND2, and receives a fast mode delay shift control signal fast_sl. And a second inverter (INV3) output as

That is, the delay shift control units 130R and 130F among the components of the register-controlled delayed fixed loop circuit DLL according to the related art are fast mode control signals FM_END and FM_ENDF among the mode control signals FM_END, lock_state, FM_END_F, and lock_statef. ) Outputs the normal mode delay shift control signal frclk_sl in response to the second timing pulse PULSE_3 when the logic is 'high' (high) and fast among the mode control signals FM_END, lock_state, FM_END_F, lock_statef. When the mode control signals FM_END and FM_ENDF are deactivated to a logic 'low', the fast mode delay shift control signal fast_sl is output in response to the second timing pulse PULSE_3.

For reference, the configuration of the delay shift controllers 130R and 130F shown in FIG. 2 is only a configuration necessary to derive the problems of the prior art-a configuration for generating a signal capable of selecting fast mode and normal mode operation. will be. Thus, the actual circuit is much more complicated than the diagram shown in FIG.

However, when the normal mode delay shift control signal frclk_sl and the fast mode delay shift control signal fast_sl are output in response to the second timing pulse PULSE_3, the following problem may occur.

FIG. 3 is a timing diagram illustrating operations of a mode control unit and a delay shift control unit among the components of the register-controlled delay locked loop (DLL) according to the related art shown in FIG. 1.

Referring to FIG. 3, in the register-controlled delayed fixed loop circuit DLL according to the related art, the mode control signals FM_END, lock_state, FM_END_F, which are generated in response to the first timing pulse PULSE_2 in the mode controllers 120R and 120F, may be used. Delay shift controller when the timing at which the fast mode control signals FM_END and FM_ENDF transition from logic 'low' to logic 'high' among the lock_statef overlaps with a section where the second timing pulse PULSE_3 is activated. The normal mode delay shift control signal frclk_sl and the fast mode delay shift control signal fast_sl, which are toggled in response to the second timing pulse PULSE_3 at 130R and 103F but should not be toggled at the same time, are simultaneously toggled. It can be seen that occurs.

In detail, the mode control units 120R and 120F correspond to the signals (fine, course, and FM_pdout) output from the phase comparators 100R and 100F, and the mode control signals FM_END, lock_state, FM_END_F, and lock_statef in the fast mode state. ), The fast mode control signals FM_END and FM_ENDF are kept in a logic 'low' inactive state. Similarly, when the fast mode is terminated and the normal mode is entered, the fast mode control signals FM_END and FM_ENDF are transferred from the logic 'low' state to the logic 'high' state and the logic 'high' (high). Maintain state.

In addition, when the fast mode control signals FM_END and FM_ENDF are logic 'low' in the fast mode, the fast mode delay shift control signal fast_sl is toggled in response to the second timing pulse PULSE_3. At this time, the normal mode delay shift control signal frclk_sl is not toggled (①).

Similarly, when the fast mode control signals FM_END and FM_ENDF are in the normal mode state as logic 'high', the normal mode delay shift control signal frclk_sl is toggled in response to the second timing pulse PULSE_3. At this time, the fast mode delay shift control signal fast_sl is not toggled (2).

In this way, the fast mode control signals FM_END and FM_ENDF defining the boundary between the fast mode and the normal mode are configured to be logic 'high' in a logic 'low' state in response to toggling of the first timing pulse PULSE_2. High).

By the way, ideally, the logic level transition time of the fast mode control signals FM_END and FM_ENDF and the starting point of the toggling of the first timing pulse PULSE_2 should be exactly the same. The logic of the fast mode control signals FM_END and FM_ENDF is slightly later than the starting point of the toggling of the first timing pulse PULSE_2 since there is a time required to perform the operation in which the logic levels of the mode control signals FM_END and FM_ENDF transition. A level transition occurs (③).

At this time, since the period in which the first timing pulse PULSE_2 and the second timing pulse PULSE_3 remain active is equal to the value obtained by dividing the TCK of the external clock CLK in half, the frequency of the external clock CLK is relatively high. In the case where the TCK value of the external clock CLK is relatively high and the activation period of the first timing pulse PULSE_2 is relatively long, it is slightly later than the starting point of toggling of the first timing pulse PULSE_2 as described above. Even when the logic levels of the fast mode control signals FM_END and FM_ENDF are transitioned, it is difficult for the logic level transition of the fast mode control signals FM_END and FM_ENDF to occur within the activation period of the second timing pulse PULSE_3.

However, when the frequency of the external clock CLK is relatively high and the TCK value of the external clock CLK is relatively small and the activation period of the first timing pulse PULSE_2 is relatively short, the first timing pulse as described above. When the logic level transition of the fast mode control signals FM_END and FM_ENDF occurs when the logic level of the fast mode control signals FM_END and FM_ENDF transitions slightly later than the starting point of the toggling of PULSE_2), the second timing pulse is generated. It enters the activation section of (PULSE_3).

When the logic level transition of the fast mode control signals FM_END and FM_ENDF occurs within the activation period of the second timing pulse PULSE_3, the logic level transition of the fast mode control signals FM_END and FM_ENDF occurs. If the second timing pulse PULSE_3 is not activated, the fast mode delay shift control signal fast_sl is toggled (④), and the logic level transition of the fast mode control signals FM_END and FM_ENDF has occurred. In the state before the pulse PULSE_3 is inactivated, the normal mode delay shift control signal frclk_sl is toggled (5). That is, when the second timing pulse PULSE_3 toggles once, a problem occurs in which both the fast mode delay shift control signal fast_sl and the normal mode delay shift control signal frclk_sl are toggled.

Therefore, in the phase delay units 140R and 140F, which actually delay the internal clocks clkin1 and clkin2, the delay shifting unit of the delay group unit is performed according to the fast mode, or the delay unit unit delay unit according to the normal mode. Since it is not known exactly whether to perform the shifting operation, a problem occurs that causes a malfunction of the register-controlled delay locked loop (DLL).

In addition, since the frequency of the external clock CLK input to the register-controlled delayed fixed loop circuit DLL is increasing, the probability of occurrence of the problem as described above becomes more and more.

The present invention is limited to solve the problems of the prior art as described above, and an object thereof is to provide a register controlled delay locked loop circuit (DLL) capable of switching a stable delay operation mode even when an external clock of high frequency is input.

According to an aspect of the present invention for achieving the above technical problem, a normal mode for performing a delay shifting unit of the delay unit, and a delay group-including a plurality of delay units-fast performing the delay shifting unit of the unit 1. A register controlled delay locked loop supporting mode, comprising: phase comparison means for comparing phases of a source clock and a feedback clock; Control pulse generation means for generating a first timing pulse, a second timing pulse, and a third timing pulse sequentially activated in response to the source clock in response to a delay shifting update period; Mode control means for generating a mode control signal according to a comparison result of the phase comparing means in response to the first timing pulse; Outputting a normal mode delay shift control signal for controlling the normal mode operation in response to the second timing pulse and the mode control signal, and controlling the fast mode operation in response to the third timing pulse and the mode control signal Delay shift control means for outputting a fast mode delay shift control signal; A phase delay means for delay shifting the phase of the internal clock in units of delay units in response to the normal mode delay shift control signal and delay shifting the phase of the internal clock in units of delay groups in response to the fast mode delay shift control signals; ; And a delay replication model means for receiving the output signal of the phase delay means and outputting the feedback signal reflecting the actual delay condition of the internal clock path as the feedback clock.

In addition, according to another aspect of the present invention for achieving the above technical problem, the normal mode for performing a delay shifting unit of the delay unit, and a delay group-including a plurality of delay units-perform a delay shifting unit 1. A register controlled delay locked loop supporting fast mode, comprising: phase comparison means for comparing phases of a source clock and a feedback clock; Control pulse generation means for generating a first timing pulse, a second timing pulse, and a third timing pulse sequentially activated in response to the source clock in response to a delay shifting update period; Mode control means for generating a mode control signal according to a comparison result of the phase comparing means in response to the first timing pulse; Outputting a fast mode delay shift control signal for controlling the fast mode operation in response to the second timing pulse and the mode control signal, and controlling the normal mode operation in response to the third timing pulse and the mode control signal Delay shift control means for outputting a normal mode delay shift control signal; Phase delay means for delay shifting the phase of the internal clock in units of a delay unit in response to the normal mode delay shift control signal and delay shifting the phase of the internal clock in units of a delay group in response to the fast mode delay shift control signal; And a delay replication model means for receiving the output signal of the phase delay means and outputting the feedback signal reflecting the actual delay condition of the internal clock path as the feedback clock.

According to the present invention, even when the frequency of the external clock CLK, which is externally inputted to the register-controlled delayed fixed loop circuit DLL, is increased to decrease the TCK value, the pulses are different from each other in the fast mode and the normal mode. There is an effect that can prevent the signal controlling the driving from being activated at the same time. This has the effect of preventing the malfunction of the register controlled delay lock loop (DLL).

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

4 is a block diagram showing a register controlled delay locked loop circuit (DLL) according to an embodiment of the present invention.

Referring to FIG. 4, it can be seen that the register controlled delay locked loop DLL according to the embodiment of the present invention has a configuration similar to that of the register controlled delay locked loop according to the related art shown in FIG. 1.

Accordingly, the register-controlled delay locked loop (DLL) according to an embodiment of the present invention also performs a normal mode for performing delay shifting operations in units of delay units, and a delay group including a plurality of delay units. A register controlled delay locked loop (DLL) that supports fast mode.

In detail, the configuration includes phase comparison units 400R and 400F for comparing phases of the source clocks refclk and the feedback clocks fbclkr and fbclkf, and a control clock contclk synchronized with the source clocks refclk. The control pulse generator 410 for generating the first timing pulse PULSE_2, the second timing pulse PULSE_3, and the third timing pulse PULSE_4 sequentially activated in response to the delay shifting update period in response thereto, and the first timing. Mode control units 420R and 420F for generating mode control signals FM_END, lock_state, FM_END_F and lock_statef according to the comparison results (fine, coarse, FM_pdout, finef, coarsef, and FM_pdoutf) in response to the pulse PULSE_2. And a normal mode delay shift control signal frclk_sl for controlling the normal mode operation in response to the fast mode control signals FM_END and FM_ENDF among the second timing pulses PULSE_3 and the mode control signals FM_END, lock_state, FM_END_F, and lock_statef. ffclk_sl) Fast mode delay shift control signal (fastr_sl, fastf_sl) that controls fast mode operation in response to the fast mode control signals FM_END, FM_ENDF among the timing pulses PULSE_4 and the mode control signals FM_END, lock_state, FM_END_F, and lock_statef. Phases of the internal clocks clkin1 and clkin2 synchronized with the source clock refclk and the control clock contclk in response to the delay shift control units 430R and 430F for outputting the signal and the normal mode delay shift control signals frclk_sl and ffclk_sl. Delay shifts in units of delay units, and phase shift units 440R and 440F for delay shifting the phases of the internal clocks clkin1 and clkin2 in units of delay groups in response to the fast mode delay shift control signals fastr_sl and fastf_sl. To output the output clocks (mixout_r, mixout_f) of the phase delay units 440R and 440F and output them as feedback clocks fbclkr and fbclkf reflecting the actual delay condition of the internal clock path. And a delayed replica model unit (450R, 450F).

In addition, the clock buffer unit 480B and the clock enable signal for buffering the external clock CLK to generate a source clock refclk, control clock contclk, and internal clocks clkin1 and clkin2 whose phases are synchronized. The clock buffer unit in response to a signal containing power inversion mode (ckeb_com) and a power down mode information of a mode register set (MRS) and a signal containing precharge information Responding to a power down mode control unit 480A for controlling the operation of the 480B, a delayed fixed loop circuit (DLL) reset signal (dll_resetb) and a delayed fixed loop (DLL) deactivation signal (dis_dll) input from an external semiconductor memory device. Output delays (mixout_r, mixout_f) of the delay locked loop control unit 490 and the phase delay units 440R and 440F for generating a reset signal reset for controlling the operation of the delay locked loop circuit DLL. Invert the phase of either (mixout_r or mixout_f) mixout_f) to output the falling inner clock rising_clk corresponding to the rising edge of the outer clock CLK and the falling inner clock falling_clk corresponding to the falling edge of the external clock CLK. A pre-duty compensator 460A for outputting the C), a duty compensator 460B for correcting the duty ratio of the output clocks (rising_clk, falling_clk) of the pre-duty compensator 460A in the locked state, and The delay locked loop (DLL) driver 470 for outputting the delay locked loop output clocks (irclkdll and ifclkdll) driving the output clocks (ifbclkr and ifbclkf) of the duty compensator 460B to the output driver of the semiconductor memory device. It is further provided.

At this time, the battery duty compensator 460A and the duty compensator 460B exist between the phase delay parts 440R and 440F and the delayed replica model parts 450R and 450F, so that the battery duty compensator 460A is in phase delay. The output clocks mixout_r and mixout_f of the units 440R and 440F are output as rising internal clocks (rising_clk) and falling internal clocks (falling_clk) with different names, and the delayed replication model units 450R and 450F are further provided with rising internal clocks ( Despite receiving rising_clk) and the falling internal clock (falling_clk) and outputting them as clocks of other names (ifbclkr and ifbclkf), the above-described configuration delays the output clocks (mixout_r and mixout_f) of the phase delay units 440R and 440F. The replica model units 450R and 450F are input to output feedback clocks fbclkr and fbclkf. Since the normal mode and the fast mode operation to be described in the present invention are before the locked state, the output clock (rising_clk) of the battery duty compensator 460A in the normal mode and the fast mode operation to be described in the present invention for the following reasons. This is because the output clocks ifbclkr and ifbclkf of the falling_clk and the duty cycle correction unit 460B are the same as the output clocks mixout_r and mixout_f of the phase delay units 440R and 440F.

First, the pre-duty compensator 460A always inverts the phase of one of the clocks (mainly mixout_f) of the output clocks mixout_r and mixout_f of the phase delay units 440R and 440F. The operation for the duty correction operation of the correction unit 460B is meaningless in the operation before the locked state. In addition, the clock whose phase is inverted and the clock which is not inverted are simply the rising edges to the falling edges, and the falling edges to the rising edges, but the frequency or the level thereof are not changed.

The duty correction unit 460B bypasses the input clocks (rising_clk and falling_clk) in the fast mode and the normal mode, which are the blocks that operate after the locked state, and are in the fast mode and the normal mode.

Therefore, in the fast mode and the normal mode, the output clocks mixout_r and mixout_f of the phase delay units 440R and 440F and the output clocks fbclkr and fbclkf of the duty compensation unit 460B are the same clock. Assume it is assumed. Of course, the operation of the register-controlled delay locked loop (DLL) is completely different after the locked state, and since the changed operation is already known, the operation after the locked state will not be described.

Looking at the difference between the register-controlled delayed fixed loop circuit (DLL) according to the embodiment of the present invention described above and the register-controlled delayed fixed loop circuit (DLL) according to the prior art shown in Figure 1, a register according to an embodiment of the present invention The third timing pulse PULSE_4 is further generated by the control pulse generator 410 among the components of the controlled delay locked loop circuit DLL, and the third timing pulse further generated by the delay shift controller 430R. PULSE_4) is used to generate the fast mode delay shift control signals frclk_sl and ffclk_sl. The difference is as follows.

First, although the control pulse generator 410 has not been described in the related art, a plurality of pulses have been generated in the related art. Multiple pulses were sequentially activated once per delay shifting period, with each pulse being input into a component of a register controlled delay locked loop (DLL) and used to control its operation.

However, when the operation of the register-controlled delayed fixed loop circuit (DLL) according to a plurality of pulses are all explained, the contents thereof become too large. Only three pulses (PULSE_2, PULSE_3, PULSE_4) have been described.

For reference, a plurality of pulses generated by the control pulse generator 410 will be described below.

First, the control pulse generation unit 410 generates eight pulses of the 0th through 7th pulses (PULSE_1, PULSE_2, PULSE_3, PULSE_4, PULSE_5, PULSE_6, PULSE_7, and PULSE_8) before the locked state. Control the operation of (DLL). That is, eight pulses are activated once in a predetermined order per delay shifting period.

After the locked state, the 0 th to 10 th pulses PULSE_1, PULSE_2, PULSE_3, PULSE_4, PULSE_5, PULSE_6, PULSE_7, PULSE_8, PULSE_9, PULSE_10, and PULSE_11 are generated to operate the register-controlled delayed fixed loop circuit (DLL). To control. That is, eleven pulses are activated once in a predetermined order per delay shifting period.

If the use of the generated pulse is described with an example, it can be defined as shown in Table 1.

For reference, in Table 1, all of the 0 th to 10 th pulses (PULSE_1, PULSE_2, PULSE_3, PULSE_4, PULSE_5, PULSE_6, PULSE_7, PULSE_8, PULSE_9, PULSE_10, and PULSE_11) were described. That is, the eighth to tenth pulses PULSE_9, PULSE_10, and PULSE_11 in the table 1 are not used before the locked state but are used immediately after entering the locked state.

As summarized in Table 1, a plurality of pulses generated by the control pulse generator 410 are used. Of course, each pulse use described in Table 1 is described as an example, and thus the use may be changed by the designer even if the pulse is not used or the pulse is used. However, in the general register control type delay locked loop (DLL), it operates as shown in the prior art in the contents of Table 1.

In addition, the details of operations of the pulses, namely, the first to third pulses PULSE_2, PULSE_3, and PULSE_4, which are to be a problem in the present invention, are described in detail in Table 1 as follows.

First, the first pulse PULSE_2 is input to the mode controllers 420R and 420F in the operation of the prior art and the present invention and used to generate the mode control signals FM_END, lock_state, FM_END_F, and lock_statef. That is, when the mode control signals FM_END, lock_state, FM_END_F, and lock_statef first pulse PULSE_2 toggles, they are activated or deactivated.

In the prior art, the second pulse PULSE_3 is input to the mode controllers 120R and 120F and used to generate the normal mode delay shift control signals frclk_sl and ffclk_sl and the fast mode delay shift control signals fastr_sl and fastf_sl. do. That is, the normal mode delay shift control signals frclk_sl and ffclk_sl and the fast mode delay shift control signals fastr_sl and fastf_sl are toggled in response to toggling of the second pulse PULSE_3.

However, in the present invention, the second pulse PULSE_3 is input to the mode controllers 420R and 420F and used to generate the normal mode delay shift control signals frclk_sl and ffclk_sl.

Further, in the prior art, the third pulse PULSE_4 was generated but was not actually used.

However, in the present invention, the third pulse PULSE_4 is input to the mode controllers 420R and 420F and used to generate the fast mode delay shift control signals fastr_sl and fastf_sl.

That is, in the present invention, the normal mode delay shift control signals frclk_sl and ffclk_sl are generated in response to the second pulse PULSE_3, and the fast mode delay shift control signals fastr_sl and fastf_sl are generated in response to the third pulse PULSE_4. In this case, the time points at which the normal mode delay shift control signals frclk_sl and ffclk_sl and the fast mode delay shift control signals fastr_sl and fastf_sl are generated are different from each other.

FIG. 5 is a detailed circuit diagram illustrating a delay shift controller among components of a register controlled delay locked loop (DLL) according to an exemplary embodiment of the present invention illustrated in FIG. 4.

For reference, in the delay shift controllers 430R and 430F, the block 430R for the rising internal clock (rising_clk) and the block 430F for the falling internal clock (falling_clk) have the same configuration. Only block 430R for rising_clk) is shown.

Referring to FIG. 5, the delay shift control units 430R and 430F of the components of the register-controlled delay locked loop circuit DLL according to the embodiment of the present invention may output a second timing pulse output from the control pulse generator 410. The normal mode delay shift control signal generators 432R and 432F for generating the normal mode delay shift control signals frclk_sl and ffclk_sl for controlling the normal mode operation in response to PULSE_3, and the third timing pulse PULSE_4. In response, fast mode delay shift control signal generators 434R and 434F are configured to generate fast mode delay shift control signals fastr_sl and fastf_sl for controlling the fast mode operation.

Here, the normal mode delay shift control signal generators 432R and 432F receive the fast mode control signals FM_END and FM_END_F among the second timing pulses PULSE_3 and the mode control signals FM_END, lock_state, FM_END_F, and lock_statef. And an inverter INV2 for receiving the output NAND gate NAND1 and the output signal of the NAND gate NAND1 and outputting the output signal as the normal mode delay shift control signals frclk_sl and ffclk_sl.

In addition, the fast mode delay shift control signal generators 434R and 434F receive and output the fast mode control signals FM_END and FM_END_F among the mode control signals FM_END, lock_state, FM_END_F, and lock_statef. And a NAND gate NAND2 for receiving and outputting an output signal of the third timing pulse PULSE_4 and the first inverter INV1, and a NAND gate NAND2 output signal for receiving a fast mode delay shift control signal ( Second inverter INV3 output as fastr_sl and fastf_sl) is provided.

That is, the delay shift control units 430R and 430F of the components of the register-controlled delayed fixed loop circuit DLL according to the embodiment of the present invention may use the fast mode control signals (F_END, lock_state, FM_END_F, lock_statef). When FM_END and FM_ENDF are activated with logic 'high', the normal mode delay shift control signal frclk_sl is output in response to the second timing pulse PULSE_3, and the mode control signals FM_END, lock_state, FM_END_F, and lock_statef are output. The fast mode delay shift control signal fast_sl is output in response to the third timing pulse PULSE_4 when the fast mode control signals FM_END and FM_ENDF are deactivated to logic 'low'.

For reference, the configuration of the delay shift controllers 430R and 130F illustrated in FIG. 5 is only a configuration necessary to derive the problems of the prior art-a configuration for generating a signal capable of selecting fast mode and normal mode operation. will be. Thus, the actual circuit is much more complicated than the diagram shown in FIG.

FIG. 6 is a timing diagram illustrating operations of a mode control unit and a delay shift control unit among the components of a register controlled delay locked loop (DLL) according to the embodiment of the present invention shown in FIG. 4.

Referring to FIG. 6, in the register controlled delay locked loop circuit DLL according to an exemplary embodiment of the present invention, the mode control signals FM_END and lock_state generated in response to the first timing pulse PULSE_2 in the mode controllers 420R and 420F. When the timing at which the fast mode control signals FM_END and FM_ENDF transition from logic 'low' to logic 'high' among the FM_END_F and lock_statef overlaps with a section in which the second timing pulse PULSE_3 is activated It can be seen that the normal mode delay shift control signal frclk_sl and the fast mode delay shift control signal fast_sl do not toggle at the same time.

In detail, the mode control units 420R and 420F correspond to the signals (fine, course, and FM_pdout) output from the phase comparators 400R and 400F, and the mode control signals FM_END, lock_state, FM_END_F, and lock_statef in the fast mode state. ), The fast mode control signals FM_END and FM_ENDF are kept in a logic 'low' inactive state. Similarly, when the fast mode is terminated and the normal mode is entered, the fast mode control signals FM_END and FM_ENDF are transferred from the logic 'low' state to the logic 'high' state and the logic 'high' (high). Maintain state.

In addition, when the fast mode control signals FM_END and FM_ENDF are logic 'low' in the fast mode, the fast mode delay shift control signal fast_sl is toggled in response to the third timing pulse PULSE_4. ①).

Similarly, when the fast mode control signals FM_END and FM_ENDF are logic 'high' and are in the normal mode, the normal mode delay shift control signal frclk_sl toggles in response to the second timing pulse PULSE_3. ②).

In addition, the fast mode control signals FM_END and FM_ENDF defining the boundary between the fast mode and the normal mode are configured to be logic 'high' in a logic 'low' state in response to toggling of the first timing pulse PULSE_2. High).

By the way, ideally, the logic level transition time of the fast mode control signals FM_END and FM_ENDF and the starting point of the toggling of the first timing pulse PULSE_2 should be exactly the same. The logic of the fast mode control signals FM_END and FM_ENDF is slightly later than the starting point of the toggling of the first timing pulse PULSE_2 since there is a time required to perform the operation in which the logic levels of the mode control signals FM_END and FM_ENDF transition. A level transition occurs (③).

At this time, since the period in which the first timing pulse PULSE_2 and the second timing pulse PULSE_3 remain active is equal to the value obtained by dividing the TCK of the external clock CLK in half, the frequency of the external clock CLK is relatively high. If the TCK value of the external clock CLK is relatively small and the activation period of the first timing pulse PULSE_2 is relatively short, as described above, at a point slightly later than the starting point of the toggling of the first timing pulse PULSE_2, as described above. When the logic level of the fast mode control signals FM_END and FM_ENDF transitions, a time point at which a logic level transition of the fast mode control signals FM_END and FM_ENDF occurs is entered into the activation section of the second timing pulse PULSE_3.

Thus, even when the logic level of the fast mode control signals FM_END and FM_ENDF transitions from logic 'low' to logic 'high' within the activation period of the second timing pulse PULSE_3, Since the fast mode delay shift control signal fast_sl does not toggle in response to the activation of the two timing pulses PULSE_3, the fast mode delay shift control signal fast_sl is not toggled.

That is, in the exemplary embodiment of the present invention, since the fast mode delay shift control signal fast_sl is toggled in response to the third timing pulse PULSE_4 which is activated later than the second timing pulse PULSE_3, the fast mode control signals FM_END and FM_ENDF. Toggle only the normal mode delay shift control signal frclk_sl even when the logic level of the control panel transitions from the logic 'low' to the logic 'high' within the activation period of the second timing pulse PULSE_3. Ring (④).

Therefore, as in the prior art, the fast mode delay shift control signal fast_sl is performed based on a time when the logic level of the fast mode control signals FM_END and FM_ENDF transitions from logic 'low' to logic 'high'. ) And the normal mode delay shift control signal frclk_sl can be prevented from being toggled.

As described above, according to the exemplary embodiment of the present invention, even when an external clock CLK having a relatively high frequency is input to the register controlled delay locked loop DLL, different pulses may be used in the fast mode and the normal mode. By controlling the driving, it is possible to prevent the fast mode operation and the normal mode operation from occurring at once. In other words, it is possible to stably switch the delay operation mode of the register controlled delay locked loop circuit DLL.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions and modifications are possible within the scope without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.

For example, in the above-described embodiment, a signal for controlling the normal mode operation in response to a pulse for toggling the relatively fast mode operation in response to a pulse that is relatively later toggled among different pulses is provided. The case of toggling has been described. However, the present invention provides a normal mode operation in response to a pulse that toggles a signal controlling a fast mode operation in response to a pulse that toggles relatively first, and relatively later. It also includes the case of toggling the signal to control the.

In addition, the above-described embodiment has described a case in which there are consecutive pulses toggling relatively earlier among different pulses and pulses toggling relatively later among the different pulses. This includes discontinuous cases where the later toggling pulses are not equal to one another.

In addition, the logic gate and the transistor illustrated in the above embodiment should be implemented in different positions and types depending on the polarity of the input signal.

1 is a block diagram showing a register controlled delay locked loop circuit (DLL) according to the prior art;

FIG. 2 is a circuit diagram illustrating in detail a delay shift control unit among components of a register controlled delay locked loop (DLL) according to the related art shown in FIG.

3 is a timing diagram showing the operation of the mode control unit and the delay shift control unit among the components of the register-controlled delay locked loop (DLL) according to the related art shown in FIG.

4 is a block diagram showing a register controlled delay locked loop circuit (DLL) in accordance with an embodiment of the present invention.

FIG. 5 is a circuit diagram showing in detail a delay shift control unit among the components of a register controlled delay locked loop (DLL) according to the embodiment of the present invention shown in FIG.

FIG. 6 is a timing diagram showing the operation of the mode control unit and the delay shift control unit among the components of the register controlled delay locked loop (DLL) according to the embodiment of the present invention shown in FIG.

* Explanation of symbols for main parts of the drawings

100R, 400R: Phase comparison unit (RISING)

100F, 400F: Phase comparator, 110: Control pulse generator

120R, 420R: Mode control unit (RISING)

120F, 420F: Mode control (FALLING)

130R, 430R: Delay Shift Control (RISING)

130F, 430F: Delay Shift Control (FALLING)

140R, 440R: Phase delay unit (RISING)

140F, 440F: Phase delay unit (FALLING)

150R, 450R: Delayed replication model (RISING)

150F, 450F: Delayed replication model (FALLING)

160A, 460A: Predatory Duty Government, 160B, 460B: Duty Duty Government

170, 470: delay locked loop circuit (DLL) driver

180A, 480A: Power down mode controller 180B, 480B: Clock buffer section

190, 490: delay locked loop (DLL) control unit

Claims (8)

In the register-controlled delay lock loop which supports a normal mode for performing delay shifting operations in units of delay units and a fast mode for performing delay group-including a plurality of delay units-in units of delay shifting operations, Phase comparison means for comparing phases of the source clock and the feedback clock; Control pulse generation means for generating a first timing pulse, a second timing pulse, and a third timing pulse sequentially activated in response to a control clock synchronized with the source clock; Mode control means for generating a mode control signal according to a comparison result of the phase comparing means in response to the first timing pulse; Outputting a normal mode delay shift control signal for controlling the normal mode operation in response to the second timing pulse and the mode control signal, and controlling the fast mode operation in response to the third timing pulse and the mode control signal Delay shift control means for outputting a fast mode delay shift control signal; Phase delay means for delay shifting the phase of the internal clock in units of a delay unit in response to the normal mode delay shift control signal and delay shifting the phase of the internal clock in units of a delay group in response to the fast mode delay shift control signal; And Delay replication model means for receiving the output signal of the phase delay means and outputting the feedback clock in consideration of the actual delay condition of the internal clock path; A register controlled delay locked loop circuit (DLL) having a. The method of claim 1, The delay shift control means, A normal mode delay shift control signal generation unit configured to generate a normal mode delay shift control signal for controlling the normal mode operation in response to the second timing pulse; And And a fast mode delay shift control signal generator for generating a fast mode delay shift control signal for controlling the fast mode operation in response to the third timing pulse. The method of claim 2, The normal mode delay shift control signal generator, A NAND gate configured to receive and output the second timing pulse and the mode control signal; And And an inverter which receives an output signal of the NAND gate and outputs the output signal as the normal mode delay shift control signal. The method of claim 2, The fast mode delay shift control signal generator, A first inverter configured to receive and output the mode control signal; A NAND gate receiving the third timing pulse and an output signal of the first inverter and outputting the input signals; And And a second inverter receiving the output signal of the NAND gate and outputting the output signal as the fast mode delay shift control signal. In the register-controlled delay lock loop which supports a normal mode for performing delay shifting operations in units of delay units and a fast mode for performing delay group-including a plurality of delay units-in units of delay shifting operations, Phase comparison means for comparing phases of the source clock and the feedback clock; Control pulse generation means for generating a first timing pulse, a second timing pulse, and a third timing pulse sequentially activated in response to a control clock synchronized with the source clock; Mode control means for generating a mode control signal according to a comparison result of the phase comparing means in response to the first timing pulse; Outputting a fast mode delay shift control signal for controlling the fast mode operation in response to the second timing pulse and the mode control signal, and controlling the normal mode operation in response to the third timing pulse and the mode control signal Delay shift control means for outputting a normal mode delay shift control signal; Phase delay means for delay shifting the phase of the internal clock in units of a delay unit in response to the normal mode delay shift control signal and delay shifting the phase of the internal clock in units of a delay group in response to the fast mode delay shift control signal; And Delay replication model means for receiving the output signal of the phase delay means and outputting the feedback clock in consideration of the actual delay condition of the internal clock path; A register controlled delay locked loop circuit (DLL) having a. The method of claim 5, The delay shift control means, A normal mode delay shift control signal generator configured to generate a normal mode delay shift control signal for controlling the normal mode operation in response to the third timing pulse; And And a fast mode delay shift control signal generator for generating a fast mode delay shift control signal for controlling the fast mode operation in response to the second timing pulse. The method of claim 6, The normal mode delay shift control signal generator, A NAND gate configured to receive and output the third timing pulse and the mode control signal; And And an inverter which receives an output signal of the NAND gate and outputs the output signal as the normal mode delay shift control signal. The method of claim 6, The fast mode delay shift control signal generator, A first inverter configured to receive and output the mode control signal; A NAND gate receiving the second timing pulse and the output signal of the first inverter and outputting the input signals; And And a second inverter receiving the output signal of the NAND gate and outputting the output signal as the fast mode delay shift control signal.

Images